1 | # |
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2 | # $Id$ |
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3 | # |
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4 | |
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5 | BSP NAME: helas403 |
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6 | BOARD: IMD, helas-ppc |
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7 | BUS: N/A |
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8 | CPU FAMILY: ppc |
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9 | CPU: PowerPC 403GA |
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10 | COPROCESSORS: N/A |
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11 | MODE: 32 bit mode |
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12 | |
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13 | DEBUG MONITOR: Modified Motorola FBUG |
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14 | |
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15 | PERIPHERALS |
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16 | =========== |
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17 | TIMERS: 403GA internal |
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18 | RESOLUTION: .04 microseconds |
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19 | SERIAL PORTS: 403GA internal |
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20 | REAL-TIME CLOCK: 403GA internal |
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21 | DMA: 403GA internal |
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22 | VIDEO: none |
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23 | SCSI: none |
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24 | NETWORKING: none |
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25 | |
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26 | DRIVER INFORMATION |
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27 | ================== |
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28 | CLOCK DRIVER: 403GA internal |
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29 | IOSUPP DRIVER: N/A |
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30 | SHMSUPP: N/A |
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31 | TIMER DRIVER: 403GA internal |
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32 | TTY DRIVER: 403GA internal |
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33 | |
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34 | STDIO |
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35 | ===== |
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36 | PORT: Console port 0 |
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37 | ELECTRICAL: RS-232 |
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38 | BAUD: 9600 |
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39 | BITS PER CHARACTER: 8 |
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40 | PARITY: None |
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41 | STOP BITS: 1 |
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42 | |
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43 | Notes |
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44 | ===== |
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45 | |
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46 | Board description |
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47 | ----------------- |
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48 | clock rate: 25 MHz |
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49 | bus width: 8-bit PROM, 32-bit DRAM |
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50 | ROM: Up to 512KByte (Am29F040), 90 nsec chip select 0 |
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51 | RAM: 4 to 32 MByte DRAM SIMM (autodetect), 70 nsec, |
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52 | no parity, at CS7 or CS6+CS7 (for two-bank-SIMMs) |
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53 | |
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54 | |
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55 | helas403 only supports single processor operations. |
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56 | |
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57 | Porting |
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58 | ------- |
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59 | This board support package is written for a typical PPC403GA |
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60 | system. The rough features of this board are described above. |
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61 | |
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62 | This BSP contains files for two startup methods: |
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63 | - Direct start from Flash after powerup (with code run out of flash): |
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64 | This is the default configuration, it uses the files |
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65 | flashentry/flashentry.s |
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66 | startup/linkcmds |
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67 | |
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68 | Please note, that this configuration is good to startup the system, |
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69 | but it will not gain maximum performance due to slow Flash access (8 |
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70 | bit wide only) |
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71 | |
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72 | - Start after software download into DRAM: |
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73 | This configuration will use: |
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74 | dlentry/dlentry.s |
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75 | startup/linkcmds.dl |
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76 | |
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77 | If you want to use the download configuration, it is sufficient to |
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78 | rename the file "startup/linkcmds.dl" to "startup/linkcmds", it will |
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79 | automatically reference the dlentry.s as entry code. (Renaming is not |
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80 | quite elegant, a more sophisticated solution will follow in future, |
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81 | any hints welcome ;-) |
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82 | |
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83 | For adapting this BSP to other boards, the following files should be |
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84 | modified: |
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85 | |
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86 | - c/src/lib/libbsp/powerpc/helas403/flashentry/flashentry.s |
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87 | for the memory controller configuration and other basic stuff |
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88 | |
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89 | - c/src/lib/libbsp/powerpc/helas403/startup/linkcmds[.dl] |
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90 | for the memory layout required |
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91 | |
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92 | - c/src/lib/libbsp/powerpc/helas403/startup/bspstart.c |
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93 | for adaption of BSP_Configuration. here you can select |
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94 | the clock source for the timers and the serial interface |
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95 | (system clock or external clock pin), the clock rates, initial |
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96 | baud rate and other stuff |
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97 | |
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98 | - c/src/lib/libbsp/powerpc/helas403/include/bsp.h |
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99 | some BSP-related constants |
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100 | |
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101 | The actual drivers are placed in |
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102 | - c/src/lib/libcpu/powerpc/ppc403/* |
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103 | well, they should be generic, so there _should_ be no reason |
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104 | to mess around there (but who knows...) |
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105 | |
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106 | |
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