source: rtems/c/src/lib/libbsp/powerpc/haleakala/irq/irq.h @ c499856

4.115
Last change on this file since c499856 was c499856, checked in by Chris Johns <chrisj@…>, on 03/20/14 at 21:10:47

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1/*===============================================================*\
2| Project: RTEMS Haleakala BSP                                    |
3| by Michael Hamel ADInstruments Ltd 2008                         |
4+-----------------------------------------------------------------+
5| The license and distribution terms for this file may be         |
6| found in the file LICENSE in this distribution or at            |
7|                                                                 |
8| http://www.rtems.org/license/LICENSE.                           |
9|                                                                 |
10\*===============================================================*/
11
12
13#ifndef Haleakala_IRQ_IRQ_H
14#define Haleakala_IRQ_IRQ_H
15
16/* Implemented for us in bsp_irq_dispatch_list */
17#define BSP_SHARED_HANDLER_SUPPORT      1
18
19#include <rtems/irq.h>
20
21#ifndef ASM
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27        /* Define UIC interrupt numbers; IRQs that cause an external interrupt that needs further decode.
28           These are arbitrary but it makes things easier if they match the CPU interrupt numbers */
29
30        /*
31
32                #define BSP_UIC_UART0_GP                (BSP_UIC_IRQ_LOWEST_OFFSET + 0)
33                #define BSP_UIC_UART1                   (BSP_UIC_IRQ_LOWEST_OFFSET + 1)
34                #define BSP_UIC_IIC0                    (BSP_UIC_IRQ_LOWEST_OFFSET + 2)
35                #define BSP_UIC_ExtMaster               (BSP_UIC_IRQ_LOWEST_OFFSET + 3)
36                #define BSP_UIC_PCI                             (BSP_UIC_IRQ_LOWEST_OFFSET + 4)
37                #define BSP_UIC_DMA0                    (BSP_UIC_IRQ_LOWEST_OFFSET + 5)
38                #define BSP_UIC_DMA1                    (BSP_UIC_IRQ_LOWEST_OFFSET + 6)
39                #define BSP_UIC_DMA2                    (BSP_UIC_IRQ_LOWEST_OFFSET + 7)
40                #define BSP_UIC_DMA3                    (BSP_UIC_IRQ_LOWEST_OFFSET + 8)
41                #define BSP_UIC_ENetWU                  (BSP_UIC_IRQ_LOWEST_OFFSET + 9)
42                #define BSP_UIC_MALSERR                 (BSP_UIC_IRQ_LOWEST_OFFSET + 10)
43                #define BSP_UIC_MALTXEOB                (BSP_UIC_IRQ_LOWEST_OFFSET + 11)
44                #define BSP_UIC_MALRXEOB                (BSP_UIC_IRQ_LOWEST_OFFSET + 12)
45                #define BSP_UIC_MALTXDE                 (BSP_UIC_IRQ_LOWEST_OFFSET + 13)
46                #define BSP_UIC_MALRXDE                 (BSP_UIC_IRQ_LOWEST_OFFSET + 14)
47                #define BSP_UIC_ENet                    (BSP_UIC_IRQ_LOWEST_OFFSET + 15)
48                #define BSP_UIC_PCISERR                 (BSP_UIC_IRQ_LOWEST_OFFSET + 16)
49                #define BSP_UIC_ECCERR                  (BSP_UIC_IRQ_LOWEST_OFFSET + 17)
50                #define BSP_UIC_PCIPower                (BSP_UIC_IRQ_LOWEST_OFFSET + 18)
51                #define BSP_UIC_IRQ0                    (BSP_UIC_IRQ_LOWEST_OFFSET + 25)
52                #define BSP_UIC_IRQ1                    (BSP_UIC_IRQ_LOWEST_OFFSET + 26)
53                #define BSP_UIC_IRQ2                    (BSP_UIC_IRQ_LOWEST_OFFSET + 27)
54                #define BSP_UIC_IRQ3                    (BSP_UIC_IRQ_LOWEST_OFFSET + 28)
55                #define BSP_UIC_IRQ4                    (BSP_UIC_IRQ_LOWEST_OFFSET + 29)
56                #define BSP_UIC_IRQ5                    (BSP_UIC_IRQ_LOWEST_OFFSET + 30)
57                #define BSP_UIC_IRQ6                    (BSP_UIC_IRQ_LOWEST_OFFSET + 31)
58
59                #define BSP_UIC_IRQ_NUMBER                      (32)
60
61        */
62        /* PPC405EX interrupt vectors */
63        #define BSP_UIC_UART1                   (BSP_UIC_IRQ_LOWEST_OFFSET + 1)
64        #define BSP_UIC_IIC0                    (BSP_UIC_IRQ_LOWEST_OFFSET + 2)
65        #define BSP_UIC_EIPPKP_READY    (BSP_UIC_IRQ_LOWEST_OFFSET + 3)
66        #define BSP_UIC_EIPPKP_TRNG             (BSP_UIC_IRQ_LOWEST_OFFSET + 4)
67        #define BSP_UIC_EBM                             (BSP_UIC_IRQ_LOWEST_OFFSET + 5)
68        #define BSP_UIC_OPBtoPLB                (BSP_UIC_IRQ_LOWEST_OFFSET + 6)
69        #define BSP_UIC_IIC1                    (BSP_UIC_IRQ_LOWEST_OFFSET + 7)
70        #define BSP_UIC_SPI                             (BSP_UIC_IRQ_LOWEST_OFFSET + 8)
71        #define BSP_UIC_IRQ0                    (BSP_UIC_IRQ_LOWEST_OFFSET + 9)
72        #define BSP_UIC_MALTXEOB                (BSP_UIC_IRQ_LOWEST_OFFSET + 10)
73        #define BSP_UIC_MALRXEOB                (BSP_UIC_IRQ_LOWEST_OFFSET + 11)
74        #define BSP_UIC_DMA0                    (BSP_UIC_IRQ_LOWEST_OFFSET + 12)
75        #define BSP_UIC_DMA1                    (BSP_UIC_IRQ_LOWEST_OFFSET + 13)
76        #define BSP_UIC_DMA2                    (BSP_UIC_IRQ_LOWEST_OFFSET + 14)
77        #define BSP_UIC_DMA3                    (BSP_UIC_IRQ_LOWEST_OFFSET + 15)
78        #define BSP_UIC_PCIe0AL                 (BSP_UIC_IRQ_LOWEST_OFFSET + 16)
79        #define BSP_UIC_PCIe0VPD                (BSP_UIC_IRQ_LOWEST_OFFSET + 17)
80        #define BSP_UIC_PCIe0HRst               (BSP_UIC_IRQ_LOWEST_OFFSET + 18)
81        #define BSP_UIC_EIPPKP_PKA              (BSP_UIC_IRQ_LOWEST_OFFSET + 19)
82        #define BSP_UIC_PCIe0TCR                (BSP_UIC_IRQ_LOWEST_OFFSET + 20)
83        #define BSP_UIC_PCIe0VCO                (BSP_UIC_IRQ_LOWEST_OFFSET + 21)
84        #define BSP_UIC_EIPPKP_TRNG_AL  (BSP_UIC_IRQ_LOWEST_OFFSET + 22)
85        #define BSP_UIC_EIP94                   (BSP_UIC_IRQ_LOWEST_OFFSET + 23)
86        #define BSP_UIC_EMAC0                   (BSP_UIC_IRQ_LOWEST_OFFSET + 24)
87        #define BSP_UIC_EMAC1                   (BSP_UIC_IRQ_LOWEST_OFFSET + 25)
88        #define BSP_UIC_UART0                   (BSP_UIC_IRQ_LOWEST_OFFSET + 26)
89        #define BSP_UIC_IRQ4                    (BSP_UIC_IRQ_LOWEST_OFFSET + 27)
90        #define BSP_UIC_UIC2_STD                (BSP_UIC_IRQ_LOWEST_OFFSET + 28)
91        #define BSP_UIC_UIC2_CRIT               (BSP_UIC_IRQ_LOWEST_OFFSET + 29)
92        #define BSP_UIC_UIC1_STD                (BSP_UIC_IRQ_LOWEST_OFFSET + 30)
93        #define BSP_UIC_UIC1_CRIT               (BSP_UIC_IRQ_LOWEST_OFFSET + 31)
94
95        #define BSP_UIC1_IRQ_LOWEST_OFFSET      (BSP_UIC_IRQ_LOWEST_OFFSET + 32)
96        #define BSP_UIC_MALSERR                 (BSP_UIC1_IRQ_LOWEST_OFFSET + 0)
97        #define BSP_UIC_MALTXDE                 (BSP_UIC1_IRQ_LOWEST_OFFSET + 1)
98        #define BSP_UIC_MALRXDE                 (BSP_UIC1_IRQ_LOWEST_OFFSET + 2)
99        #define BSP_UIC_PCIe0DCRErr             (BSP_UIC1_IRQ_LOWEST_OFFSET + 3)
100        #define BSP_UIC_PCIe1DCRErr             (BSP_UIC1_IRQ_LOWEST_OFFSET + 4)
101        #define BSP_UIC_ExtBus                  (BSP_UIC1_IRQ_LOWEST_OFFSET + 5)
102        #define BSP_UIC_NDFC                    (BSP_UIC1_IRQ_LOWEST_OFFSET + 6)
103        #define BSP_UIC_EIPKP_SLAVE             (BSP_UIC1_IRQ_LOWEST_OFFSET + 7)
104        #define BSP_UIC_GPT_TIMER5              (BSP_UIC1_IRQ_LOWEST_OFFSET + 8)
105        #define BSP_UIC_GPT_TIMER6              (BSP_UIC1_IRQ_LOWEST_OFFSET + 9)
106
107        #define BSP_UIC_GPT_TIMER0              (BSP_UIC1_IRQ_LOWEST_OFFSET + 16)
108        #define BSP_UIC_GPT_TIMER1              (BSP_UIC1_IRQ_LOWEST_OFFSET + 17)
109        #define BSP_UIC_IRQ7                    (BSP_UIC1_IRQ_LOWEST_OFFSET + 18)
110        #define BSP_UIC_IRQ8                    (BSP_UIC1_IRQ_LOWEST_OFFSET + 19)
111        #define BSP_UIC_IRQ9                    (BSP_UIC1_IRQ_LOWEST_OFFSET + 20)
112        #define BSP_UIC_GPT_TIMER2              (BSP_UIC1_IRQ_LOWEST_OFFSET + 21)
113        #define BSP_UIC_GPT_TIMER3              (BSP_UIC1_IRQ_LOWEST_OFFSET + 22)
114        #define BSP_UIC_GPT_TIMER4              (BSP_UIC1_IRQ_LOWEST_OFFSET + 23)
115        #define BSP_UIC_SERIAL_ROM              (BSP_UIC1_IRQ_LOWEST_OFFSET + 24)
116        #define BSP_UIC_GPT_DEC                 (BSP_UIC1_IRQ_LOWEST_OFFSET + 25)
117        #define BSP_UIC_IRQ2                    (BSP_UIC1_IRQ_LOWEST_OFFSET + 26)
118        #define BSP_UIC_IRQ5                    (BSP_UIC1_IRQ_LOWEST_OFFSET + 27)
119        #define BSP_UIC_IRQ6                    (BSP_UIC1_IRQ_LOWEST_OFFSET + 28)
120        #define BSP_UIC_EMAC0WU                 (BSP_UIC1_IRQ_LOWEST_OFFSET + 29)
121        #define BSP_UIC_IRQ1                    (BSP_UIC1_IRQ_LOWEST_OFFSET + 30)
122        #define BSP_UIC_EMAC1WU                 (BSP_UIC1_IRQ_LOWEST_OFFSET + 31)
123
124        #define BSP_UIC2_IRQ_LOWEST_OFFSET      (BSP_UIC_IRQ_LOWEST_OFFSET + 64)
125        #define BSP_UIC_PCIe0INTA               (BSP_UIC2_IRQ_LOWEST_OFFSET + 0)
126        #define BSP_UIC_PCIe0INTB               (BSP_UIC2_IRQ_LOWEST_OFFSET + 1)
127        #define BSP_UIC_PCIe0INTC               (BSP_UIC2_IRQ_LOWEST_OFFSET + 2)
128        #define BSP_UIC_PCIe0INTD               (BSP_UIC2_IRQ_LOWEST_OFFSET + 3)
129        #define BSP_UIC_IRQ3                    (BSP_UIC2_IRQ_LOWEST_OFFSET + 4)
130
131        #define BSP_UIC_USBOTG                  (BSP_UIC2_IRQ_LOWEST_OFFSET + 30)
132
133        #define BSP_UIC_IRQ_NUMBER                      (95)
134
135
136        #define BSP_UIC_IRQ_LOWEST_OFFSET       0
137        #define BSP_UIC_IRQ_MAX_OFFSET          (BSP_UIC_IRQ_LOWEST_OFFSET + BSP_UIC_IRQ_NUMBER - 1)
138
139        #define BSP_UART_COM1_IRQ               BSP_UIC_UART0 /* Required by shared/console/uart.c */
140        #define BSP_UART_COM2_IRQ               BSP_UIC_UART1
141
142        /* Define processor IRQ numbers; IRQs that are handled by the exception vectors */
143
144        #define BSP_PIT                         BSP_PROCESSOR_IRQ_LOWEST_OFFSET /* Required by ppc403/clock.c */
145        #define BSP_FIT                         BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 1
146        #define BSP_WDOG                        BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 2
147
148        #define BSP_PROCESSOR_IRQ_NUMBER            (3)
149        #define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_UIC_IRQ_MAX_OFFSET + 1)
150        #define BSP_PROCESSOR_IRQ_MAX_OFFSET    (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1)
151
152        /* Summary and totals */
153
154        #define BSP_IRQ_NUMBER                  (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1)
155        #define BSP_LOWEST_OFFSET               (BSP_UIC_IRQ_LOWEST_OFFSET)
156        #define BSP_MAX_OFFSET                  (BSP_IRQ_NUMBER - 1)
157
158        extern void BSP_rtems_irq_mng_init(unsigned cpuId);             // Implemented in irq_init.c
159        #include <bsp/irq_supp.h>
160
161        #ifdef __cplusplus
162        }
163        #endif
164#endif /* ASM */
165
166#endif /* Haleakala_IRQ_IRQ_H */
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