1 | /*===============================================================*\ |
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2 | | Project: RTEMS Haleakala BSP | |
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3 | | by Michael Hamel ADInstruments Ltd 2008 | |
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4 | +-----------------------------------------------------------------+ |
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5 | | The license and distribution terms for this file may be | |
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6 | | found in the file LICENSE in this distribution or at | |
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7 | | | |
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8 | | http://www.rtems.org/license/LICENSE. | |
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9 | | | |
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10 | \*===============================================================*/ |
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11 | |
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12 | |
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13 | #ifndef Haleakala_IRQ_IRQ_H |
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14 | #define Haleakala_IRQ_IRQ_H |
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15 | |
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16 | /* Implemented for us in bsp_irq_dispatch_list */ |
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17 | #define BSP_SHARED_HANDLER_SUPPORT 1 |
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18 | |
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19 | #include <rtems/irq.h> |
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20 | |
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21 | #ifndef ASM |
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22 | |
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23 | #ifdef __cplusplus |
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24 | extern "C" { |
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25 | #endif |
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26 | |
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27 | /* Define UIC interrupt numbers; IRQs that cause an external interrupt that needs further decode. |
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28 | These are arbitrary but it makes things easier if they match the CPU interrupt numbers */ |
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29 | |
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30 | /* |
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31 | |
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32 | #define BSP_UIC_UART0_GP (BSP_UIC_IRQ_LOWEST_OFFSET + 0) |
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33 | #define BSP_UIC_UART1 (BSP_UIC_IRQ_LOWEST_OFFSET + 1) |
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34 | #define BSP_UIC_IIC0 (BSP_UIC_IRQ_LOWEST_OFFSET + 2) |
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35 | #define BSP_UIC_ExtMaster (BSP_UIC_IRQ_LOWEST_OFFSET + 3) |
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36 | #define BSP_UIC_PCI (BSP_UIC_IRQ_LOWEST_OFFSET + 4) |
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37 | #define BSP_UIC_DMA0 (BSP_UIC_IRQ_LOWEST_OFFSET + 5) |
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38 | #define BSP_UIC_DMA1 (BSP_UIC_IRQ_LOWEST_OFFSET + 6) |
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39 | #define BSP_UIC_DMA2 (BSP_UIC_IRQ_LOWEST_OFFSET + 7) |
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40 | #define BSP_UIC_DMA3 (BSP_UIC_IRQ_LOWEST_OFFSET + 8) |
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41 | #define BSP_UIC_ENetWU (BSP_UIC_IRQ_LOWEST_OFFSET + 9) |
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42 | #define BSP_UIC_MALSERR (BSP_UIC_IRQ_LOWEST_OFFSET + 10) |
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43 | #define BSP_UIC_MALTXEOB (BSP_UIC_IRQ_LOWEST_OFFSET + 11) |
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44 | #define BSP_UIC_MALRXEOB (BSP_UIC_IRQ_LOWEST_OFFSET + 12) |
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45 | #define BSP_UIC_MALTXDE (BSP_UIC_IRQ_LOWEST_OFFSET + 13) |
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46 | #define BSP_UIC_MALRXDE (BSP_UIC_IRQ_LOWEST_OFFSET + 14) |
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47 | #define BSP_UIC_ENet (BSP_UIC_IRQ_LOWEST_OFFSET + 15) |
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48 | #define BSP_UIC_PCISERR (BSP_UIC_IRQ_LOWEST_OFFSET + 16) |
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49 | #define BSP_UIC_ECCERR (BSP_UIC_IRQ_LOWEST_OFFSET + 17) |
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50 | #define BSP_UIC_PCIPower (BSP_UIC_IRQ_LOWEST_OFFSET + 18) |
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51 | #define BSP_UIC_IRQ0 (BSP_UIC_IRQ_LOWEST_OFFSET + 25) |
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52 | #define BSP_UIC_IRQ1 (BSP_UIC_IRQ_LOWEST_OFFSET + 26) |
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53 | #define BSP_UIC_IRQ2 (BSP_UIC_IRQ_LOWEST_OFFSET + 27) |
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54 | #define BSP_UIC_IRQ3 (BSP_UIC_IRQ_LOWEST_OFFSET + 28) |
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55 | #define BSP_UIC_IRQ4 (BSP_UIC_IRQ_LOWEST_OFFSET + 29) |
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56 | #define BSP_UIC_IRQ5 (BSP_UIC_IRQ_LOWEST_OFFSET + 30) |
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57 | #define BSP_UIC_IRQ6 (BSP_UIC_IRQ_LOWEST_OFFSET + 31) |
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58 | |
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59 | #define BSP_UIC_IRQ_NUMBER (32) |
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60 | |
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61 | */ |
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62 | /* PPC405EX interrupt vectors */ |
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63 | #define BSP_UIC_UART1 (BSP_UIC_IRQ_LOWEST_OFFSET + 1) |
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64 | #define BSP_UIC_IIC0 (BSP_UIC_IRQ_LOWEST_OFFSET + 2) |
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65 | #define BSP_UIC_EIPPKP_READY (BSP_UIC_IRQ_LOWEST_OFFSET + 3) |
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66 | #define BSP_UIC_EIPPKP_TRNG (BSP_UIC_IRQ_LOWEST_OFFSET + 4) |
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67 | #define BSP_UIC_EBM (BSP_UIC_IRQ_LOWEST_OFFSET + 5) |
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68 | #define BSP_UIC_OPBtoPLB (BSP_UIC_IRQ_LOWEST_OFFSET + 6) |
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69 | #define BSP_UIC_IIC1 (BSP_UIC_IRQ_LOWEST_OFFSET + 7) |
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70 | #define BSP_UIC_SPI (BSP_UIC_IRQ_LOWEST_OFFSET + 8) |
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71 | #define BSP_UIC_IRQ0 (BSP_UIC_IRQ_LOWEST_OFFSET + 9) |
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72 | #define BSP_UIC_MALTXEOB (BSP_UIC_IRQ_LOWEST_OFFSET + 10) |
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73 | #define BSP_UIC_MALRXEOB (BSP_UIC_IRQ_LOWEST_OFFSET + 11) |
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74 | #define BSP_UIC_DMA0 (BSP_UIC_IRQ_LOWEST_OFFSET + 12) |
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75 | #define BSP_UIC_DMA1 (BSP_UIC_IRQ_LOWEST_OFFSET + 13) |
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76 | #define BSP_UIC_DMA2 (BSP_UIC_IRQ_LOWEST_OFFSET + 14) |
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77 | #define BSP_UIC_DMA3 (BSP_UIC_IRQ_LOWEST_OFFSET + 15) |
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78 | #define BSP_UIC_PCIe0AL (BSP_UIC_IRQ_LOWEST_OFFSET + 16) |
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79 | #define BSP_UIC_PCIe0VPD (BSP_UIC_IRQ_LOWEST_OFFSET + 17) |
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80 | #define BSP_UIC_PCIe0HRst (BSP_UIC_IRQ_LOWEST_OFFSET + 18) |
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81 | #define BSP_UIC_EIPPKP_PKA (BSP_UIC_IRQ_LOWEST_OFFSET + 19) |
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82 | #define BSP_UIC_PCIe0TCR (BSP_UIC_IRQ_LOWEST_OFFSET + 20) |
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83 | #define BSP_UIC_PCIe0VCO (BSP_UIC_IRQ_LOWEST_OFFSET + 21) |
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84 | #define BSP_UIC_EIPPKP_TRNG_AL (BSP_UIC_IRQ_LOWEST_OFFSET + 22) |
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85 | #define BSP_UIC_EIP94 (BSP_UIC_IRQ_LOWEST_OFFSET + 23) |
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86 | #define BSP_UIC_EMAC0 (BSP_UIC_IRQ_LOWEST_OFFSET + 24) |
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87 | #define BSP_UIC_EMAC1 (BSP_UIC_IRQ_LOWEST_OFFSET + 25) |
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88 | #define BSP_UIC_UART0 (BSP_UIC_IRQ_LOWEST_OFFSET + 26) |
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89 | #define BSP_UIC_IRQ4 (BSP_UIC_IRQ_LOWEST_OFFSET + 27) |
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90 | #define BSP_UIC_UIC2_STD (BSP_UIC_IRQ_LOWEST_OFFSET + 28) |
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91 | #define BSP_UIC_UIC2_CRIT (BSP_UIC_IRQ_LOWEST_OFFSET + 29) |
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92 | #define BSP_UIC_UIC1_STD (BSP_UIC_IRQ_LOWEST_OFFSET + 30) |
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93 | #define BSP_UIC_UIC1_CRIT (BSP_UIC_IRQ_LOWEST_OFFSET + 31) |
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94 | |
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95 | #define BSP_UIC1_IRQ_LOWEST_OFFSET (BSP_UIC_IRQ_LOWEST_OFFSET + 32) |
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96 | #define BSP_UIC_MALSERR (BSP_UIC1_IRQ_LOWEST_OFFSET + 0) |
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97 | #define BSP_UIC_MALTXDE (BSP_UIC1_IRQ_LOWEST_OFFSET + 1) |
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98 | #define BSP_UIC_MALRXDE (BSP_UIC1_IRQ_LOWEST_OFFSET + 2) |
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99 | #define BSP_UIC_PCIe0DCRErr (BSP_UIC1_IRQ_LOWEST_OFFSET + 3) |
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100 | #define BSP_UIC_PCIe1DCRErr (BSP_UIC1_IRQ_LOWEST_OFFSET + 4) |
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101 | #define BSP_UIC_ExtBus (BSP_UIC1_IRQ_LOWEST_OFFSET + 5) |
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102 | #define BSP_UIC_NDFC (BSP_UIC1_IRQ_LOWEST_OFFSET + 6) |
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103 | #define BSP_UIC_EIPKP_SLAVE (BSP_UIC1_IRQ_LOWEST_OFFSET + 7) |
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104 | #define BSP_UIC_GPT_TIMER5 (BSP_UIC1_IRQ_LOWEST_OFFSET + 8) |
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105 | #define BSP_UIC_GPT_TIMER6 (BSP_UIC1_IRQ_LOWEST_OFFSET + 9) |
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106 | |
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107 | #define BSP_UIC_GPT_TIMER0 (BSP_UIC1_IRQ_LOWEST_OFFSET + 16) |
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108 | #define BSP_UIC_GPT_TIMER1 (BSP_UIC1_IRQ_LOWEST_OFFSET + 17) |
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109 | #define BSP_UIC_IRQ7 (BSP_UIC1_IRQ_LOWEST_OFFSET + 18) |
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110 | #define BSP_UIC_IRQ8 (BSP_UIC1_IRQ_LOWEST_OFFSET + 19) |
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111 | #define BSP_UIC_IRQ9 (BSP_UIC1_IRQ_LOWEST_OFFSET + 20) |
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112 | #define BSP_UIC_GPT_TIMER2 (BSP_UIC1_IRQ_LOWEST_OFFSET + 21) |
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113 | #define BSP_UIC_GPT_TIMER3 (BSP_UIC1_IRQ_LOWEST_OFFSET + 22) |
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114 | #define BSP_UIC_GPT_TIMER4 (BSP_UIC1_IRQ_LOWEST_OFFSET + 23) |
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115 | #define BSP_UIC_SERIAL_ROM (BSP_UIC1_IRQ_LOWEST_OFFSET + 24) |
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116 | #define BSP_UIC_GPT_DEC (BSP_UIC1_IRQ_LOWEST_OFFSET + 25) |
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117 | #define BSP_UIC_IRQ2 (BSP_UIC1_IRQ_LOWEST_OFFSET + 26) |
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118 | #define BSP_UIC_IRQ5 (BSP_UIC1_IRQ_LOWEST_OFFSET + 27) |
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119 | #define BSP_UIC_IRQ6 (BSP_UIC1_IRQ_LOWEST_OFFSET + 28) |
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120 | #define BSP_UIC_EMAC0WU (BSP_UIC1_IRQ_LOWEST_OFFSET + 29) |
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121 | #define BSP_UIC_IRQ1 (BSP_UIC1_IRQ_LOWEST_OFFSET + 30) |
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122 | #define BSP_UIC_EMAC1WU (BSP_UIC1_IRQ_LOWEST_OFFSET + 31) |
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123 | |
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124 | #define BSP_UIC2_IRQ_LOWEST_OFFSET (BSP_UIC_IRQ_LOWEST_OFFSET + 64) |
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125 | #define BSP_UIC_PCIe0INTA (BSP_UIC2_IRQ_LOWEST_OFFSET + 0) |
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126 | #define BSP_UIC_PCIe0INTB (BSP_UIC2_IRQ_LOWEST_OFFSET + 1) |
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127 | #define BSP_UIC_PCIe0INTC (BSP_UIC2_IRQ_LOWEST_OFFSET + 2) |
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128 | #define BSP_UIC_PCIe0INTD (BSP_UIC2_IRQ_LOWEST_OFFSET + 3) |
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129 | #define BSP_UIC_IRQ3 (BSP_UIC2_IRQ_LOWEST_OFFSET + 4) |
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130 | |
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131 | #define BSP_UIC_USBOTG (BSP_UIC2_IRQ_LOWEST_OFFSET + 30) |
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132 | |
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133 | #define BSP_UIC_IRQ_NUMBER (95) |
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134 | |
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135 | |
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136 | #define BSP_UIC_IRQ_LOWEST_OFFSET 0 |
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137 | #define BSP_UIC_IRQ_MAX_OFFSET (BSP_UIC_IRQ_LOWEST_OFFSET + BSP_UIC_IRQ_NUMBER - 1) |
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138 | |
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139 | #define BSP_UART_COM1_IRQ BSP_UIC_UART0 /* Required by shared/console/uart.c */ |
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140 | #define BSP_UART_COM2_IRQ BSP_UIC_UART1 |
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141 | |
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142 | /* Define processor IRQ numbers; IRQs that are handled by the exception vectors */ |
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143 | |
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144 | #define BSP_PIT BSP_PROCESSOR_IRQ_LOWEST_OFFSET /* Required by ppc403/clock.c */ |
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145 | #define BSP_FIT BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 1 |
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146 | #define BSP_WDOG BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 2 |
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147 | |
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148 | #define BSP_PROCESSOR_IRQ_NUMBER (3) |
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149 | #define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_UIC_IRQ_MAX_OFFSET + 1) |
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150 | #define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1) |
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151 | |
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152 | /* Summary and totals */ |
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153 | |
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154 | #define BSP_IRQ_NUMBER (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1) |
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155 | #define BSP_LOWEST_OFFSET (BSP_UIC_IRQ_LOWEST_OFFSET) |
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156 | #define BSP_MAX_OFFSET (BSP_IRQ_NUMBER - 1) |
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157 | |
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158 | extern void BSP_rtems_irq_mng_init(unsigned cpuId); // Implemented in irq_init.c |
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159 | #include <bsp/irq_supp.h> |
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160 | |
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161 | #ifdef __cplusplus |
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162 | } |
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163 | #endif |
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164 | #endif /* ASM */ |
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165 | |
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166 | #endif /* Haleakala_IRQ_IRQ_H */ |
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