1 | /* |
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2 | * |
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3 | * |
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4 | * The license and distribution terms for this file may be |
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5 | * found in the file LICENSE in this distribution or at |
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6 | * http://www.rtems.org/license/LICENSE. |
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7 | * |
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8 | * Middleware support for PPC405 by M.Hamel ADInstruments Ltd 2008 |
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9 | */ |
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10 | |
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11 | #include <rtems.h> |
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12 | #include <bsp.h> |
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13 | #include <bsp/irq.h> |
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14 | #include <bsp/irq_supp.h> |
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15 | #include <bsp/vectors.h> |
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16 | #include <libcpu/powerpc-utility.h> |
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17 | |
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18 | |
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19 | /* PPC405EX UIC numbers */ |
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20 | #define UIC_DCR_BASE 0xc0 |
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21 | #define UIC0_SR (UIC_DCR_BASE+0x0) /* UIC status */ |
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22 | #define UIC0_SRS (UIC_DCR_BASE+0x1) /* UIC status set */ |
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23 | #define UIC0_ER (UIC_DCR_BASE+0x2) /* UIC enable */ |
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24 | #define UIC0_CR (UIC_DCR_BASE+0x3) /* UIC critical */ |
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25 | #define UIC0_PR (UIC_DCR_BASE+0x4) /* UIC polarity */ |
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26 | #define UIC0_TR (UIC_DCR_BASE+0x5) /* UIC triggering */ |
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27 | #define UIC0_MSR (UIC_DCR_BASE+0x6) /* UIC masked status */ |
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28 | #define UIC0_VR (UIC_DCR_BASE+0x7) /* UIC vector */ |
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29 | #define UIC0_VCR (UIC_DCR_BASE+0x8) /* UIC vector configuration */ |
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30 | |
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31 | #define UIC1_SR (UIC_DCR_BASE+0x10) /* UIC status */ |
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32 | #define UIC1_SRS (UIC_DCR_BASE+0x11) /* UIC status set */ |
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33 | #define UIC1_ER (UIC_DCR_BASE+0x12) /* UIC enable */ |
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34 | #define UIC1_CR (UIC_DCR_BASE+0x13) /* UIC critical */ |
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35 | #define UIC1_PR (UIC_DCR_BASE+0x14) /* UIC polarity */ |
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36 | #define UIC1_TR (UIC_DCR_BASE+0x15) /* UIC triggering */ |
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37 | #define UIC1_MSR (UIC_DCR_BASE+0x16) /* UIC masked status */ |
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38 | #define UIC1_VR (UIC_DCR_BASE+0x17) /* UIC vector */ |
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39 | #define UIC1_VCR (UIC_DCR_BASE+0x18) /* UIC vector configuration */ |
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40 | |
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41 | #define UIC2_SR (UIC_DCR_BASE+0x20) /* UIC status */ |
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42 | #define UIC2_SRS (UIC_DCR_BASE+0x21) /* UIC status set */ |
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43 | #define UIC2_ER (UIC_DCR_BASE+0x22) /* UIC enable */ |
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44 | #define UIC2_CR (UIC_DCR_BASE+0x23) /* UIC critical */ |
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45 | #define UIC2_PR (UIC_DCR_BASE+0x24) /* UIC polarity */ |
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46 | #define UIC2_TR (UIC_DCR_BASE+0x25) /* UIC triggering */ |
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47 | #define UIC2_MSR (UIC_DCR_BASE+0x26) /* UIC masked status */ |
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48 | #define UIC2_VR (UIC_DCR_BASE+0x27) /* UIC vector */ |
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49 | #define UIC2_VCR (UIC_DCR_BASE+0x28) /* UIC vector configuration */ |
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50 | |
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51 | enum { kUICWords = 3 }; |
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52 | |
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53 | static rtems_irq_connect_data* rtems_hdl_tblP; |
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54 | static rtems_irq_connect_data dflt_entry; |
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55 | |
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56 | static uint32_t gEnabledInts[kUICWords]; /* 1-bits mean enabled */ |
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57 | static uint32_t gIntInhibited[kUICWords]; /* 1-bits disable, overriding gEnabledInts because the interrupt |
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58 | is being processed in C_dispatch_irq_handler */ |
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59 | |
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60 | static inline int IsUICIRQ(const rtems_irq_number irqLine) |
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61 | { |
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62 | return (((int) irqLine <= BSP_UIC_IRQ_MAX_OFFSET) && |
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63 | ((int) irqLine >= BSP_UIC_IRQ_LOWEST_OFFSET) |
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64 | ); |
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65 | } |
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66 | |
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67 | static void WriteIState(void) |
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68 | /* Write the gEnabledInts state masked by gIntInhibited to the hardware */ |
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69 | { |
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70 | PPC_SET_DEVICE_CONTROL_REGISTER(UIC0_ER, |
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71 | gEnabledInts[0] & ~gIntInhibited[0]); |
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72 | PPC_SET_DEVICE_CONTROL_REGISTER(UIC1_ER, |
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73 | gEnabledInts[1] & ~gIntInhibited[1]); |
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74 | PPC_SET_DEVICE_CONTROL_REGISTER(UIC2_ER, |
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75 | gEnabledInts[2] & ~gIntInhibited[2]); |
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76 | } |
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77 | |
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78 | void |
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79 | BSP_enable_irq_at_pic(const rtems_irq_number irq) |
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80 | /* Enable an interrupt; this can be called from inside C_dispatch_irq_handler */ |
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81 | { |
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82 | if (IsUICIRQ(irq)) { |
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83 | /* Set relevant bit in the state, write state to the UIC */ |
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84 | gEnabledInts[irq>>5] |= (0x80000000 >> (irq & 0x1F)); |
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85 | WriteIState(); |
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86 | } |
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87 | } |
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88 | |
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89 | int |
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90 | BSP_disable_irq_at_pic(const rtems_irq_number irq) |
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91 | /* Enable an interrupt; this can be called from inside C_dispatch_irq_handler */ |
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92 | { |
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93 | if (IsUICIRQ(irq)) { |
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94 | uint32_t oldState; |
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95 | int iword = irq>>5; |
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96 | uint32_t mask = (0x80000000 >> (irq & 0x1F)); |
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97 | |
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98 | oldState = gEnabledInts[iword] & mask; |
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99 | gEnabledInts[iword] &= ~mask; |
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100 | WriteIState(); |
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101 | return oldState ? 1 : 0; |
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102 | } else |
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103 | return -1; |
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104 | } |
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105 | |
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106 | int |
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107 | BSP_setup_the_pic(rtems_irq_global_settings* config) |
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108 | { |
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109 | int i; |
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110 | |
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111 | dflt_entry = config->defaultEntry; |
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112 | rtems_hdl_tblP = config->irqHdlTbl; |
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113 | for (i=0; i<kUICWords; i++) |
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114 | gIntInhibited[i] = 0; |
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115 | |
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116 | /* disable all interrupts */ |
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117 | PPC_SET_DEVICE_CONTROL_REGISTER (UIC2_ER, 0x00000000); |
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118 | /* Set Critical / Non Critical interrupts */ |
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119 | PPC_SET_DEVICE_CONTROL_REGISTER (UIC2_CR, 0x00000000); |
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120 | /* Set Interrupt Polarities */ |
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121 | PPC_SET_DEVICE_CONTROL_REGISTER (UIC2_PR, 0xf7ffffff); |
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122 | /* Set Interrupt Trigger Levels */ |
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123 | PPC_SET_DEVICE_CONTROL_REGISTER (UIC2_TR, 0x01e1fff8); |
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124 | /* Set Vect base=0,INT31 Highest priority */ |
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125 | PPC_SET_DEVICE_CONTROL_REGISTER (UIC2_VR, 0x00000001); |
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126 | /* clear all interrupts */ |
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127 | PPC_SET_DEVICE_CONTROL_REGISTER (UIC2_SR, 0xffffffff); |
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128 | |
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129 | /* disable all interrupts */ |
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130 | PPC_SET_DEVICE_CONTROL_REGISTER (UIC1_ER, 0x00000000); |
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131 | /* Set Critical / Non Critical interrupts */ |
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132 | PPC_SET_DEVICE_CONTROL_REGISTER (UIC1_CR, 0x00000000); |
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133 | /* Set Interrupt Polarities */ |
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134 | PPC_SET_DEVICE_CONTROL_REGISTER (UIC1_PR, 0xfffac785); |
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135 | /* Set Interrupt Trigger Levels */ |
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136 | PPC_SET_DEVICE_CONTROL_REGISTER (UIC1_TR, 0x001d0040); |
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137 | /* Set Vect base=0,INT31 Highest priority */ |
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138 | PPC_SET_DEVICE_CONTROL_REGISTER (UIC1_VR, 0x00000001); |
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139 | /* clear all interrupts */ |
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140 | PPC_SET_DEVICE_CONTROL_REGISTER (UIC1_SR, 0xffffffff); |
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141 | |
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142 | /* Disable all interrupts except cascade UIC0 and UIC1 */ |
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143 | PPC_SET_DEVICE_CONTROL_REGISTER (UIC0_ER, 0x0000000a); |
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144 | /* Set Critical / Non Critical interrupts */ |
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145 | PPC_SET_DEVICE_CONTROL_REGISTER (UIC0_CR, 0x00000000); |
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146 | /* Set Interrupt Polarities */ |
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147 | PPC_SET_DEVICE_CONTROL_REGISTER (UIC0_PR, 0xffbfefef); |
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148 | /* Set Interrupt Trigger Levels */ |
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149 | PPC_SET_DEVICE_CONTROL_REGISTER (UIC0_TR, 0x00007000); |
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150 | /* Set Vect base=0,INT31 Highest priority */ |
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151 | PPC_SET_DEVICE_CONTROL_REGISTER (UIC0_VR, 0x00000001); |
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152 | /* clear all interrupts */ |
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153 | PPC_SET_DEVICE_CONTROL_REGISTER (UIC0_SR, 0xffffffff); |
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154 | |
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155 | return 1; |
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156 | } |
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157 | |
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158 | |
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159 | /* |
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160 | * High level IRQ handler called from shared_raw_irq_code_entry; decode and |
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161 | * dispatch. Note that this routine needs to be re-entrant |
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162 | * |
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163 | * No support for critical interrupts here yet |
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164 | */ |
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165 | |
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166 | int |
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167 | C_dispatch_irq_handler( BSP_Exception_frame* frame, unsigned int excNum ) |
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168 | { |
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169 | if (excNum == ASM_EXT_VECTOR) { |
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170 | uint32_t active[kUICWords]; |
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171 | |
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172 | /* Fetch the masked flags that tell us what external ints are active. |
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173 | Likely to be only one, but we need to handle more than one, |
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174 | OR the flags into gIntInhibited */ |
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175 | active[0] = PPC_DEVICE_CONTROL_REGISTER(UIC0_MSR); |
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176 | active[1] = PPC_DEVICE_CONTROL_REGISTER(UIC1_MSR); |
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177 | active[2] = PPC_DEVICE_CONTROL_REGISTER(UIC2_MSR); |
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178 | gIntInhibited[0] |= active[0]; |
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179 | gIntInhibited[1] |= active[1]; |
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180 | gIntInhibited[2] |= active[2]; |
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181 | |
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182 | /* ...and update the hardware so the active interrupts are disabled */ |
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183 | WriteIState(); |
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184 | |
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185 | /* Loop, calling bsp_irq_dispatch_list for each active interrupt */ |
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186 | while ((active[0] | active[1] | active[2]) != 0) { |
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187 | uint32_t index = -1; |
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188 | uint32_t bit, bmask; |
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189 | |
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190 | /* Find an active interrupt, searching 0..2, bit 0..bit 31 (IBM order) */ |
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191 | do { |
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192 | index++; |
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193 | asm volatile (" cntlzw %0, %1":"=r" (bit):"r" (active[index])); |
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194 | } while (bit==32); |
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195 | |
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196 | /* Call the matching handler */ |
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197 | bsp_irq_dispatch_list(rtems_hdl_tblP, (index*32)+bit, dflt_entry.hdl); |
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198 | |
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199 | /* Write a 1-bit to the appropriate status register to clear it */ |
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200 | bmask = 0x80000000 >> bit; |
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201 | switch (index) { |
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202 | case 0: |
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203 | PPC_SET_DEVICE_CONTROL_REGISTER(UIC0_SR, bmask); |
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204 | break; |
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205 | case 1: |
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206 | PPC_SET_DEVICE_CONTROL_REGISTER(UIC1_SR, bmask); |
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207 | break; |
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208 | case 2: |
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209 | PPC_SET_DEVICE_CONTROL_REGISTER(UIC2_SR, bmask); |
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210 | break; |
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211 | } |
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212 | |
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213 | /* Clear in the active record and gIntInhibited */ |
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214 | active[index] &= ~bmask; |
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215 | gIntInhibited[index] &= ~bmask; |
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216 | }; |
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217 | |
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218 | /* Update the hardware again so the interrupts we have handled are unmasked */ |
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219 | WriteIState(); |
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220 | return 0; |
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221 | |
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222 | } else if (excNum == ASM_DEC_VECTOR) { /* 0x1000 remapped by C_dispatch_dec_handler_bookE */ |
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223 | bsp_irq_dispatch_list(rtems_hdl_tblP, BSP_PIT, dflt_entry.hdl); |
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224 | return 0; |
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225 | |
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226 | } else if (excNum == ASM_BOOKE_FIT_VECTOR) { /* 0x1010 mapped to 0x13 by ppc_get_vector_addr */ |
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227 | bsp_irq_dispatch_list(rtems_hdl_tblP, BSP_FIT, dflt_entry.hdl); |
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228 | return 0; |
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229 | |
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230 | } else if (excNum == ASM_BOOKE_WDOG_VECTOR) { /* 0x1020 mapped to 0x14 by ppc_get_vector_addr */ |
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231 | bsp_irq_dispatch_list(rtems_hdl_tblP, BSP_WDOG, dflt_entry.hdl); |
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232 | return 0; |
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233 | |
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234 | } else |
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235 | return -1; /* unhandled interrupt, panic time */ |
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236 | } |
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237 | |
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