1 | /* dlentry.s |
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2 | * |
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3 | * This file contains the entry code for RTEMS programs starting |
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4 | * after download to RAM |
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5 | * |
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6 | * Author: Thomas Doerfler <td@imd.m.isar.de> |
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7 | * IMD Ingenieurbuero fuer Microcomputertechnik |
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8 | * |
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9 | * COPYRIGHT (c) 1998 by IMD |
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10 | * |
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11 | * Changes from IMD are covered by the original distributions terms. |
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12 | * This file has been derived from the papyrus BSP: |
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13 | * |
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14 | * This file contains the entry veneer for RTEMS programs |
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15 | * downloaded to Papyrus. |
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16 | * |
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17 | * Author: Andrew Bray <andy@i-cubed.co.uk> |
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18 | * |
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19 | * COPYRIGHT (c) 1995 by i-cubed ltd. |
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20 | * |
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21 | * To anyone who acknowledges that this file is provided "AS IS" |
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22 | * without any express or implied warranty: |
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23 | * permission to use, copy, modify, and distribute this file |
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24 | * for any purpose is hereby granted without fee, provided that |
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25 | * the above copyright notice and this notice appears in all |
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26 | * copies, and that the name of i-cubed limited not be used in |
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27 | * advertising or publicity pertaining to distribution of the |
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28 | * software without specific, written prior permission. |
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29 | * i-cubed limited makes no representations about the suitability |
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30 | * of this software for any purpose. |
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31 | * |
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32 | * $Id$ |
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33 | * |
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34 | * derived from "helas403/dlentry.S": |
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35 | * |
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36 | * Further changes to derive for the PPC405CR/GP/GPr/EX/EXr |
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37 | * by Michael Hamel ADInstruments Ltd 2008 |
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38 | * |
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39 | * |
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40 | * Id: dlentry.S,v 1.2 2000/08/02 16:30:57 joel Exp |
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41 | */ |
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42 | |
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43 | #include <rtems/asm.h> |
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44 | |
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45 | /* |
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46 | * The virtex ELF link scripts support three special sections: |
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47 | * .entry The actual entry point |
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48 | * .vectors The section containing the interrupt entry veneers. |
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49 | */ |
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50 | |
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51 | /* |
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52 | * Downloaded code loads the vectors separately to 0x00000100, |
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53 | * so .entry can be over 256 bytes. |
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54 | * |
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55 | * The other sections are linked in the following order: |
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56 | * .entry |
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57 | * .text |
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58 | * .data |
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59 | * .bss |
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60 | * see linker command file for section placement |
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61 | * |
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62 | * The initial stack is set to stack.end |
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63 | * |
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64 | * All the entry veneer has to do is to clear the BSS. |
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65 | */ |
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66 | |
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67 | /* |
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68 | * GDB likes to have debugging information for the entry veneer. |
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69 | * Here was some DWARF information. IMD removed it, because we |
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70 | * could not check, whether it was still correct. Sorry. |
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71 | |
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72 | */ |
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73 | |
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74 | |
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75 | .section .entry |
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76 | |
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77 | PUBLIC_VAR (start) |
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78 | PUBLIC_VAR (download_entry) |
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79 | PUBLIC_VAR (__rtems_entry_point) |
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80 | |
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81 | SYM(start): |
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82 | SYM(download_entry): |
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83 | SYM(__rtems_entry_point): |
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84 | |
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85 | .extern SYM (boot_card) |
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86 | |
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87 | bl .startup /* First word is branch to reset_entry */ |
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88 | |
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89 | |
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90 | /*--------------------------------------------------------------------------- |
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91 | * Parameters from linker |
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92 | *--------------------------------------------------------------------------*/ |
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93 | |
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94 | base_addr: |
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95 | toc_pointer: |
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96 | .long s.got |
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97 | bss_length: |
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98 | .long bss.size |
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99 | bss_addr: |
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100 | .long bss.start |
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101 | sbss_length: |
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102 | .long sbss.size |
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103 | sbss_addr: |
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104 | .long sbss.start |
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105 | stack_top: |
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106 | .long stack.end |
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107 | PUBLIC_VAR (text_addr) |
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108 | text_addr: |
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109 | .long text.start |
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110 | PUBLIC_VAR (text_length) |
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111 | text_length: |
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112 | .long text.size |
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113 | |
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114 | /*--------------------------------------------------------------------------- |
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115 | * Reset_entry. |
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116 | *--------------------------------------------------------------------------*/ |
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117 | .startup: |
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118 | /* Get entrypoint address in R1 so we can find linker variables */ |
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119 | mflr r1 |
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120 | |
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121 | /* Initialise procesor registers generally */ |
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122 | bl init405 |
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123 | |
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124 | /* Clear .bss and .sbss */ |
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125 | bl bssclr |
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126 | |
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127 | /*------------------------------------------------------------------- |
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128 | * C_setup. |
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129 | *------------------------------------------------------------------*/ |
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130 | lwz r1,stack_top - base_addr(r1) /* Now set R1 to stack_top */ |
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131 | addi r1,r1,-56-4 /* start stack at text_addr - 56 */ |
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132 | li r3,0 |
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133 | stw r3, 0(r1) /* Clear stack chain */ |
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134 | stw r3, 4(r1) |
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135 | stw r3, 8(r1) |
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136 | stw r3, 12(r1) |
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137 | |
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138 | bl __eabi /* Initialise EABI: sets up r2 & r13 */ |
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139 | |
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140 | lis r5,environ@ha |
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141 | la r5,environ@l(r5) /* environp */ |
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142 | li r4, 0 /* argv */ |
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143 | li r3, 0 /* argc */ |
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144 | |
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145 | b SYM (boot_card) /* call the first C routine */ |
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146 | |
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147 | /*--------------------------------------------------------------------------- |
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148 | * bssclr. |
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149 | *--------------------------------------------------------------------------*/ |
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150 | bssclr: lwz r2,bss_addr-base_addr(r1) /* start of bss set by loader */ |
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151 | lwz r3,bss_length-base_addr(r1) /* bss length */ |
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152 | srwi. r3,r3,2 /* div 4 to get # of words */ |
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153 | li r0,0 |
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154 | beq dosbss /* no bss */ |
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155 | mtctr r3 /* set ctr reg */ |
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156 | subi r2,r2,4 |
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157 | clear_bss: stwu r0,4(r2) |
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158 | bdnz clear_bss /* decrement counter and loop */ |
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159 | |
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160 | dosbss: lwz r2,sbss_addr-base_addr(r1) /* start of sbss set by loader */ |
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161 | lwz r3,sbss_length-base_addr(r1) /* sbss length */ |
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162 | slwi. r3,r3,2 /* div 4 to get # of words */ |
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163 | subi r2,r2,4 |
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164 | beqlr /* no sbss */ |
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165 | mtctr r3 /* set ctr reg */ |
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166 | clear_sbss: stwu r0,4(r2) |
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167 | bdnz clear_sbss /* decrement counter and loop */ |
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168 | |
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169 | blr /* return */ |
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170 | |
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171 | |
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172 | /*--------------------------------------------------------------------------- |
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173 | * Generic 405 register setup |
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174 | *--------------------------------------------------------------------------*/ |
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175 | init405: |
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176 | li r0, 0 |
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177 | mtmsr r0 |
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178 | mticcr r0 |
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179 | mtdccr r0 |
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180 | |
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181 | li r3,0x7FFC # 405EX-specific |
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182 | mtsgr r3 # Clear guarded mode on all storage except PCIe region |
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183 | |
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184 | mtsler r0 # Storage is all big-endian |
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185 | mtsu0r r0 # and uncompressed |
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186 | |
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187 | iccci r3,0 # Invalidate the instruction cache |
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188 | li r3,1 # Enable F800 0000 to FFFF FFFF |
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189 | oris r3,r3,0xC000 # Enable 0000 0000 to 0FFF FFFF |
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190 | mticcr r3 |
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191 | isync |
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192 | |
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193 | li r3,0 |
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194 | li r4,256 # 405 has 128 or 256 32-byte lines: do 256 |
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195 | mtctr r4 # set loop ctr |
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196 | dcloop: dccci 0,r3 # invalidate line |
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197 | addi r3,r3,0x20 # bump to next line |
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198 | bdnz dcloop |
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199 | mtdcwr r0 # Select write-back caching |
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200 | lis r3,0xC000 # Enable 0000 0000 to 0FFF FFFF |
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201 | # mtdccr r3 # Enable data cache |
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202 | |
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203 | mtevpr r0 |
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204 | mtesr r0 |
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205 | mtxer r0 |
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206 | |
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207 | lwarx r3,r0,r0 # get some data/set resv bit |
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208 | stwcx. r3,r0,r0 # store out and clear resv bit |
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209 | |
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210 | lis r3,0xDEAD |
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211 | ori r3,r3,0xBEEF # Make distintive uninitialised value |
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212 | mr r4, r3 |
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213 | mr r5, r3 |
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214 | mr r6, r3 |
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215 | mr r7, r3 |
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216 | mr r8, r3 |
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217 | mr r9, r3 |
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218 | mr r10, r3 |
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219 | mr r11, r3 |
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220 | mr r12, r3 |
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221 | mr r13, r3 |
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222 | mr r14, r3 |
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223 | mr r15, r3 |
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224 | mr r16, r3 |
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225 | mr r17, r3 |
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226 | mr r18, r3 |
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227 | mr r19, r3 |
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228 | mr r20, r3 |
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229 | mr r21, r3 |
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230 | mr r22, r3 |
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231 | mr r23, r3 |
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232 | mr r24, r3 |
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233 | mr r25, r3 |
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234 | mr r26, r3 |
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235 | mr r27, r3 |
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236 | mr r28, r3 |
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237 | mr r29, r3 |
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238 | mr r30, r3 |
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239 | mr r31, r3 |
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240 | |
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241 | blr |
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242 | |
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243 | .L_text_e: |
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244 | |
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245 | .comm environ,4,4 |
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