1 | /*===============================================================*\ |
---|
2 | | Project: RTEMS generic MPC83xx BSP | |
---|
3 | +-----------------------------------------------------------------+ |
---|
4 | | Partially based on the code references which are named below. | |
---|
5 | | Adaptions, modifications, enhancements and any recent parts of | |
---|
6 | | the code are: | |
---|
7 | | Copyright (c) 2005 | |
---|
8 | | Embedded Brains GmbH | |
---|
9 | | Obere Lagerstr. 30 | |
---|
10 | | D-82178 Puchheim | |
---|
11 | | Germany | |
---|
12 | | rtems@embedded-brains.de | |
---|
13 | +-----------------------------------------------------------------+ |
---|
14 | | The license and distribution terms for this file may be | |
---|
15 | | found in the file LICENSE in this distribution or at | |
---|
16 | | | |
---|
17 | | http://www.rtems.com/license/LICENSE. | |
---|
18 | | | |
---|
19 | +-----------------------------------------------------------------+ |
---|
20 | | this file contains the code to initialize the cpu | |
---|
21 | \*===============================================================*/ |
---|
22 | |
---|
23 | /* |
---|
24 | * $Id$ |
---|
25 | */ |
---|
26 | |
---|
27 | /***********************************************************************/ |
---|
28 | /* */ |
---|
29 | /* Module: cpuinit.c */ |
---|
30 | /* Date: 07/17/2003 */ |
---|
31 | /* Purpose: RTEMS MPC5x00 C level startup code */ |
---|
32 | /* */ |
---|
33 | /*---------------------------------------------------------------------*/ |
---|
34 | /* */ |
---|
35 | /* Description: This file contains additional functions for */ |
---|
36 | /* initializing the MPC5x00 CPU */ |
---|
37 | /* */ |
---|
38 | /*---------------------------------------------------------------------*/ |
---|
39 | /* */ |
---|
40 | /* Code */ |
---|
41 | /* References: MPC8260ads additional CPU initialization */ |
---|
42 | /* Module: cpuinit.c */ |
---|
43 | /* Project: RTEMS 4.6.0pre1 / MCF8260ads BSP */ |
---|
44 | /* Version 1.1 */ |
---|
45 | /* Date: 10/22/2002 */ |
---|
46 | /* */ |
---|
47 | /* Author(s) / Copyright(s): */ |
---|
48 | /* */ |
---|
49 | /* Written by Jay Monkman (jmonkman@frasca.com) */ |
---|
50 | /* */ |
---|
51 | /*---------------------------------------------------------------------*/ |
---|
52 | /* */ |
---|
53 | /* Partially based on the code references which are named above. */ |
---|
54 | /* Adaptions, modifications, enhancements and any recent parts of */ |
---|
55 | /* the code are under the right of */ |
---|
56 | /* */ |
---|
57 | /* IPR Engineering, Dachauer StraÃe 38, D-80335 MÃŒnchen */ |
---|
58 | /* Copyright(C) 2003 */ |
---|
59 | /* */ |
---|
60 | /*---------------------------------------------------------------------*/ |
---|
61 | /* */ |
---|
62 | /* IPR Engineering makes no representation or warranties with */ |
---|
63 | /* respect to the performance of this computer program, and */ |
---|
64 | /* specifically disclaims any responsibility for any damages, */ |
---|
65 | /* special or consequential, connected with the use of this program. */ |
---|
66 | /* */ |
---|
67 | /*---------------------------------------------------------------------*/ |
---|
68 | /* */ |
---|
69 | /* Version history: 1.0 */ |
---|
70 | /* */ |
---|
71 | /***********************************************************************/ |
---|
72 | |
---|
73 | #include <bsp.h> |
---|
74 | #include <rtems/powerpc/registers.h> |
---|
75 | #include <mpc83xx/mpc83xx.h> |
---|
76 | |
---|
77 | #include <libcpu/mmu.h> |
---|
78 | #include <libcpu/spr.h> |
---|
79 | #include <string.h> |
---|
80 | |
---|
81 | #define USE_IMMU |
---|
82 | |
---|
83 | /* Macros for HID0 access */ |
---|
84 | #define SET_HID0(r) __asm__ volatile ("mtspr 0x3F0,%0\n" ::"r"(r)) |
---|
85 | #define GET_HID0(r) __asm__ volatile ("mfspr %0,0x3F0\n" :"=r"(r)) |
---|
86 | |
---|
87 | #define DBAT_MTSPR(val,name) __MTSPR(val,name); |
---|
88 | #define SET_DBAT(n,uv,lv) {DBAT_MTSPR(lv,DBAT##n##L);DBAT_MTSPR(uv,DBAT##n##U);} |
---|
89 | #if defined(USE_IMMU ) |
---|
90 | #define IBAT_MTSPR(val,name) __MTSPR(val,name); |
---|
91 | #define SET_IBAT(n,uv,lv) {IBAT_MTSPR(lv,IBAT##n##L);IBAT_MTSPR(uv,IBAT##n##U);} |
---|
92 | #endif |
---|
93 | |
---|
94 | static void calc_dbat_regvals(BAT *bat_ptr, |
---|
95 | uint32_t base_addr, |
---|
96 | uint32_t size, |
---|
97 | boolean flg_w, |
---|
98 | boolean flg_i, |
---|
99 | boolean flg_m, |
---|
100 | boolean flg_g, |
---|
101 | boolean flg_bpp) |
---|
102 | { |
---|
103 | uint32_t block_mask; |
---|
104 | uint32_t end_addr; |
---|
105 | |
---|
106 | /* |
---|
107 | * determine block mask, that overlaps the whole block |
---|
108 | */ |
---|
109 | end_addr = base_addr+size-1; |
---|
110 | block_mask = 0xffffffff; |
---|
111 | while ((end_addr & block_mask) != (base_addr & block_mask)) { |
---|
112 | block_mask <<= 1; |
---|
113 | } |
---|
114 | |
---|
115 | bat_ptr->batu.bepi = base_addr >> (32-15); |
---|
116 | bat_ptr->batu.bl = ~(block_mask >> (28-11)); |
---|
117 | bat_ptr->batu.vs = 1; |
---|
118 | bat_ptr->batu.vp = 1; |
---|
119 | |
---|
120 | bat_ptr->batl.brpn = base_addr >> (32-15); |
---|
121 | bat_ptr->batl.w = flg_w; |
---|
122 | bat_ptr->batl.i = flg_i; |
---|
123 | bat_ptr->batl.m = flg_m; |
---|
124 | bat_ptr->batl.g = flg_g; |
---|
125 | bat_ptr->batl.pp = flg_bpp; |
---|
126 | } |
---|
127 | |
---|
128 | static void clear_mmu_regs(void) |
---|
129 | { |
---|
130 | uint32_t i; |
---|
131 | /* |
---|
132 | * clear segment registers |
---|
133 | */ |
---|
134 | for (i = 0;i < 16;i++) { |
---|
135 | asm volatile(" mtsrin %0, %1\n"::"r" (i * 0x1000),"r"(i<<(31-3))); |
---|
136 | } |
---|
137 | /* |
---|
138 | * clear TLBs |
---|
139 | */ |
---|
140 | for (i = 0;i < 32;i++) { |
---|
141 | asm volatile(" tlbie %0\n"::"r" (i << (31-19))); |
---|
142 | } |
---|
143 | } |
---|
144 | |
---|
145 | void cpu_init(void) |
---|
146 | { |
---|
147 | register unsigned long reg; |
---|
148 | BAT dbat,ibat; |
---|
149 | |
---|
150 | /* |
---|
151 | * clear MMU/Segment registers |
---|
152 | */ |
---|
153 | clear_mmu_regs(); |
---|
154 | /* |
---|
155 | * clear caches |
---|
156 | */ |
---|
157 | GET_HID0(reg); |
---|
158 | reg = (reg & ~(HID0_ILOCK | HID0_DLOCK)) | HID0_ICFI | HID0_DCI; |
---|
159 | SET_HID0(reg); |
---|
160 | reg &= ~(HID0_ICFI | HID0_DCI); |
---|
161 | SET_HID0(reg); |
---|
162 | |
---|
163 | /* |
---|
164 | * set up IBAT registers in MMU |
---|
165 | */ |
---|
166 | memset(&ibat,0,sizeof(ibat)); |
---|
167 | SET_IBAT(2,ibat.batu,ibat.batl); |
---|
168 | SET_IBAT(3,ibat.batu,ibat.batl); |
---|
169 | SET_IBAT(4,ibat.batu,ibat.batl); |
---|
170 | SET_IBAT(5,ibat.batu,ibat.batl); |
---|
171 | SET_IBAT(6,ibat.batu,ibat.batl); |
---|
172 | SET_IBAT(7,ibat.batu,ibat.batl); |
---|
173 | #ifdef HAS_UBOOT |
---|
174 | calc_dbat_regvals(&ibat,mpc83xx_uboot_board_info.bi_memstart,mpc83xx_uboot_board_info.bi_memsize,0,0,0,0,BPP_RX); |
---|
175 | #else /* HAS_UBOOT */ |
---|
176 | calc_dbat_regvals(&ibat,(uint32_t) bsp_ram_start,(uint32_t) bsp_ram_size,0,0,0,0,BPP_RX); |
---|
177 | #endif /* HAS_UBOOT */ |
---|
178 | |
---|
179 | SET_IBAT(0,ibat.batu,ibat.batl); |
---|
180 | |
---|
181 | #ifdef HAS_UBOOT |
---|
182 | calc_dbat_regvals(&ibat,mpc83xx_uboot_board_info.bi_flashstart,mpc83xx_uboot_board_info.bi_flashsize,0,0,0,0,BPP_RX); |
---|
183 | #else /* HAS_UBOOT */ |
---|
184 | calc_dbat_regvals(&ibat,(uint32_t) bsp_rom_start,(uint32_t) bsp_rom_size,0,0,0,0,BPP_RX); |
---|
185 | #endif /* HAS_UBOOT */ |
---|
186 | |
---|
187 | SET_IBAT(1,ibat.batu,ibat.batl); |
---|
188 | |
---|
189 | /* |
---|
190 | * set up DBAT registers in MMU |
---|
191 | */ |
---|
192 | memset(&dbat,0,sizeof(dbat)); |
---|
193 | SET_DBAT(3,dbat.batu,dbat.batl); |
---|
194 | SET_DBAT(4,dbat.batu,dbat.batl); |
---|
195 | SET_DBAT(5,dbat.batu,dbat.batl); |
---|
196 | SET_DBAT(6,dbat.batu,dbat.batl); |
---|
197 | SET_DBAT(7,dbat.batu,dbat.batl); |
---|
198 | |
---|
199 | #ifdef HAS_UBOOT |
---|
200 | calc_dbat_regvals(&dbat,mpc83xx_uboot_board_info.bi_memstart,mpc83xx_uboot_board_info.bi_memsize,0,0,0,0,BPP_RW); |
---|
201 | #else /* HAS_UBOOT */ |
---|
202 | calc_dbat_regvals(&dbat,(uint32_t) bsp_ram_start,(uint32_t) bsp_ram_size,0,0,0,0,BPP_RW); |
---|
203 | #endif /* HAS_UBOOT */ |
---|
204 | |
---|
205 | SET_DBAT(0,dbat.batu,dbat.batl); |
---|
206 | |
---|
207 | #ifdef HAS_UBOOT |
---|
208 | calc_dbat_regvals(&dbat,mpc83xx_uboot_board_info.bi_flashstart,mpc83xx_uboot_board_info.bi_flashsize,0,0,0,0,BPP_RX); |
---|
209 | #else /* HAS_UBOOT */ |
---|
210 | calc_dbat_regvals(&dbat,(uint32_t) bsp_rom_start,(uint32_t) bsp_rom_size,0,0,0,0,BPP_RX); |
---|
211 | #endif /* HAS_UBOOT */ |
---|
212 | |
---|
213 | SET_DBAT(1,dbat.batu,dbat.batl); |
---|
214 | |
---|
215 | #ifdef HAS_UBOOT |
---|
216 | calc_dbat_regvals(&dbat,mpc83xx_uboot_board_info.bi_immrbar,1024*1024,0,1,0,1,BPP_RW); |
---|
217 | #else /* HAS_UBOOT */ |
---|
218 | calc_dbat_regvals(&dbat,(uint32_t) IMMRBAR,1024*1024,0,1,0,1,BPP_RW); |
---|
219 | #endif /* HAS_UBOOT */ |
---|
220 | |
---|
221 | SET_DBAT(2,dbat.batu,dbat.batl); |
---|
222 | |
---|
223 | #ifdef MPC8313ERDB |
---|
224 | /* Enhanced Local Bus Controller (eLBC) */ |
---|
225 | calc_dbat_regvals( &dbat, 0xfa000000, 128 * 1024, 0, 1, 0, 1, BPP_RW); |
---|
226 | SET_DBAT( 3, dbat.batu, dbat.batl); |
---|
227 | #endif /* MPC8313ERDB */ |
---|
228 | |
---|
229 | /* |
---|
230 | * enable data/instruction MMU in MSR |
---|
231 | */ |
---|
232 | _write_MSR(_read_MSR() | MSR_DR | MSR_IR); |
---|
233 | |
---|
234 | /* |
---|
235 | * enable FPU in MSR |
---|
236 | */ |
---|
237 | _write_MSR(_read_MSR() | MSR_FP); |
---|
238 | |
---|
239 | /* |
---|
240 | * in HID0: |
---|
241 | * - enable dynamic power management |
---|
242 | * - enable machine check interrupts |
---|
243 | */ |
---|
244 | GET_HID0(reg); |
---|
245 | reg |= (HID0_EMCP | HID0_DPM) ; |
---|
246 | SET_HID0(reg); |
---|
247 | |
---|
248 | /* |
---|
249 | * enable timebase clock |
---|
250 | */ |
---|
251 | mpc83xx.syscon.spcr |= M83xx_SYSCON_SPCR_TBEN; |
---|
252 | } |
---|