1 | /*===============================================================*\ |
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2 | | Project: RTEMS generic MPC83xx BSP | |
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3 | +-----------------------------------------------------------------+ |
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4 | | Partially based on the code references which are named below. | |
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5 | | Adaptions, modifications, enhancements and any recent parts of | |
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6 | | the code are: | |
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7 | | Copyright (c) 2005 | |
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8 | | Embedded Brains GmbH | |
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9 | | Obere Lagerstr. 30 | |
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10 | | D-82178 Puchheim | |
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11 | | Germany | |
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12 | | rtems@embedded-brains.de | |
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13 | +-----------------------------------------------------------------+ |
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14 | | The license and distribution terms for this file may be | |
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15 | | found in the file LICENSE in this distribution or at | |
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16 | | | |
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17 | | http://www.rtems.com/license/LICENSE. | |
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18 | | | |
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19 | +-----------------------------------------------------------------+ |
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20 | | this file contains the code to initialize the cpu | |
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21 | \*===============================================================*/ |
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22 | /***********************************************************************/ |
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23 | /* */ |
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24 | /* Module: cpuinit.c */ |
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25 | /* Date: 07/17/2003 */ |
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26 | /* Purpose: RTEMS MPC5x00 C level startup code */ |
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27 | /* */ |
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28 | /*---------------------------------------------------------------------*/ |
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29 | /* */ |
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30 | /* Description: This file contains additional functions for */ |
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31 | /* initializing the MPC5x00 CPU */ |
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32 | /* */ |
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33 | /*---------------------------------------------------------------------*/ |
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34 | /* */ |
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35 | /* Code */ |
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36 | /* References: MPC8260ads additional CPU initialization */ |
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37 | /* Module: cpuinit.c */ |
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38 | /* Project: RTEMS 4.6.0pre1 / MCF8260ads BSP */ |
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39 | /* Version 1.1 */ |
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40 | /* Date: 10/22/2002 */ |
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41 | /* */ |
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42 | /* Author(s) / Copyright(s): */ |
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43 | /* */ |
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44 | /* Written by Jay Monkman (jmonkman@frasca.com) */ |
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45 | /* */ |
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46 | /*---------------------------------------------------------------------*/ |
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47 | /* */ |
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48 | /* Partially based on the code references which are named above. */ |
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49 | /* Adaptions, modifications, enhancements and any recent parts of */ |
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50 | /* the code are under the right of */ |
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51 | /* */ |
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52 | /* IPR Engineering, Dachauer StraÃe 38, D-80335 MÃŒnchen */ |
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53 | /* Copyright(C) 2003 */ |
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54 | /* */ |
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55 | /*---------------------------------------------------------------------*/ |
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56 | /* */ |
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57 | /* IPR Engineering makes no representation or warranties with */ |
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58 | /* respect to the performance of this computer program, and */ |
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59 | /* specifically disclaims any responsibility for any damages, */ |
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60 | /* special or consequential, connected with the use of this program. */ |
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61 | /* */ |
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62 | /*---------------------------------------------------------------------*/ |
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63 | /* */ |
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64 | /* Version history: 1.0 */ |
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65 | /* */ |
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66 | /***********************************************************************/ |
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67 | |
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68 | #include <bsp.h> |
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69 | #include <rtems/powerpc/registers.h> |
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70 | #include <mpc83xx/mpc83xx.h> |
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71 | |
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72 | #include <libcpu/mmu.h> |
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73 | #include <libcpu/spr.h> |
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74 | #include <string.h> |
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75 | |
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76 | #define USE_IMMU |
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77 | |
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78 | /* Macros for HID0 access */ |
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79 | #define SET_HID0(r) __asm__ volatile ("mtspr 0x3F0,%0\n" ::"r"(r)) |
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80 | #define GET_HID0(r) __asm__ volatile ("mfspr %0,0x3F0\n" :"=r"(r)) |
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81 | |
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82 | #define DBAT_MTSPR(val,name) __MTSPR(val,name); |
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83 | #define SET_DBAT(n,uv,lv) {DBAT_MTSPR(lv,DBAT##n##L);DBAT_MTSPR(uv,DBAT##n##U);} |
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84 | #if defined(USE_IMMU ) |
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85 | #define IBAT_MTSPR(val,name) __MTSPR(val,name); |
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86 | #define SET_IBAT(n,uv,lv) {IBAT_MTSPR(lv,IBAT##n##L);IBAT_MTSPR(uv,IBAT##n##U);} |
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87 | #endif |
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88 | |
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89 | void calc_dbat_regvals(BAT *bat_ptr, |
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90 | uint32_t base_addr, |
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91 | uint32_t size, |
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92 | boolean flg_w, |
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93 | boolean flg_i, |
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94 | boolean flg_m, |
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95 | boolean flg_g, |
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96 | boolean flg_bpp) |
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97 | { |
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98 | uint32_t block_mask; |
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99 | uint32_t end_addr; |
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100 | |
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101 | /* |
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102 | * determine block mask, that overlaps the whole block |
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103 | */ |
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104 | end_addr = base_addr+size-1; |
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105 | block_mask = ~0; |
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106 | while ((end_addr & block_mask) != (base_addr & block_mask)) { |
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107 | block_mask <<= 1; |
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108 | } |
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109 | |
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110 | bat_ptr->batu.bepi = base_addr >> (32-15); |
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111 | bat_ptr->batu.bl = ~(block_mask >> (28-11)); |
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112 | bat_ptr->batu.vs = 1; |
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113 | bat_ptr->batu.vp = 1; |
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114 | |
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115 | bat_ptr->batl.brpn = base_addr >> (32-15); |
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116 | bat_ptr->batl.w = flg_w; |
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117 | bat_ptr->batl.i = flg_i; |
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118 | bat_ptr->batl.m = flg_m; |
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119 | bat_ptr->batl.g = flg_g; |
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120 | bat_ptr->batl.pp = flg_bpp; |
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121 | } |
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122 | |
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123 | void clear_mmu_regs(void) |
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124 | { |
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125 | uint32_t i; |
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126 | /* |
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127 | * clear segment registers |
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128 | */ |
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129 | for (i = 0;i < 16;i++) { |
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130 | asm volatile(" mtsrin %0, %1\n"::"r" (i * 0x1000),"r"(i<<(31-3))); |
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131 | } |
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132 | /* |
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133 | * clear TLBs |
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134 | */ |
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135 | for (i = 0;i < 32;i++) { |
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136 | asm volatile(" tlbie %0\n"::"r" (i << (31-19))); |
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137 | } |
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138 | } |
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139 | |
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140 | void cpu_init(void) |
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141 | { |
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142 | register unsigned long reg; |
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143 | BAT dbat,ibat; |
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144 | |
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145 | /* |
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146 | * clear MMU/Segment registers |
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147 | */ |
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148 | clear_mmu_regs(); |
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149 | /* |
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150 | * clear caches |
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151 | */ |
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152 | GET_HID0(reg); |
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153 | reg |= (HID0_ICFI | HID0_DCI); |
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154 | SET_HID0(reg); |
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155 | reg &= ~(HID0_ICFI | HID0_DCI); |
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156 | SET_HID0(reg); |
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157 | |
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158 | /* |
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159 | * set up IBAT registers in MMU |
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160 | */ |
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161 | memset(&ibat,0,sizeof(ibat)); |
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162 | SET_IBAT(2,ibat.batu,ibat.batl); |
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163 | SET_IBAT(3,ibat.batu,ibat.batl); |
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164 | SET_IBAT(4,ibat.batu,ibat.batl); |
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165 | SET_IBAT(5,ibat.batu,ibat.batl); |
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166 | SET_IBAT(6,ibat.batu,ibat.batl); |
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167 | SET_IBAT(7,ibat.batu,ibat.batl); |
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168 | |
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169 | calc_dbat_regvals(&ibat,RAM_START,RAM_SIZE,0,0,0,0,BPP_RX); |
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170 | SET_IBAT(0,ibat.batu,ibat.batl); |
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171 | calc_dbat_regvals(&ibat,ROM_START,ROM_SIZE,0,0,0,0,BPP_RX); |
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172 | SET_IBAT(1,ibat.batu,ibat.batl); |
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173 | |
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174 | /* |
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175 | * set up DBAT registers in MMU |
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176 | */ |
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177 | memset(&dbat,0,sizeof(dbat)); |
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178 | SET_DBAT(3,dbat.batu,dbat.batl); |
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179 | SET_DBAT(4,dbat.batu,dbat.batl); |
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180 | SET_DBAT(5,dbat.batu,dbat.batl); |
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181 | SET_DBAT(6,dbat.batu,dbat.batl); |
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182 | SET_DBAT(7,dbat.batu,dbat.batl); |
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183 | |
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184 | calc_dbat_regvals(&dbat,RAM_START,RAM_SIZE,1,0,1,0,BPP_RW); |
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185 | SET_DBAT(0,dbat.batu,dbat.batl); |
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186 | |
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187 | calc_dbat_regvals(&dbat,ROM_START,ROM_SIZE,1,0,1,0,BPP_RX); |
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188 | SET_DBAT(1,dbat.batu,dbat.batl); |
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189 | |
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190 | calc_dbat_regvals(&dbat,IMMRBAR,1024*1024,1,1,1,1,BPP_RW); |
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191 | SET_DBAT(2,dbat.batu,dbat.batl); |
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192 | |
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193 | /* |
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194 | * enable data/instruction MMU in MSR |
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195 | */ |
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196 | _write_MSR(_read_MSR() | MSR_DR/* | MSR_IR*/); |
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197 | |
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198 | /* |
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199 | * enable FPU in MSR |
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200 | */ |
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201 | _write_MSR(_read_MSR() | MSR_FP); |
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202 | |
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203 | /* |
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204 | * in HID0: |
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205 | * - enable dynamic power management |
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206 | * - enable machine check interrupts |
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207 | */ |
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208 | GET_HID0(reg); |
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209 | reg |= (HID0_EMCP | HID0_DPM) ; |
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210 | SET_HID0(reg); |
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211 | |
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212 | /* |
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213 | * enable timebase clock |
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214 | */ |
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215 | mpc83xx.syscon.spcr |= M83xx_SYSCON_SPCR_TBEN; |
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216 | } |
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