1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup mpc83xx |
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5 | * |
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6 | * @brief Source for BSP startup code. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2008 |
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11 | * Embedded Brains GmbH |
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12 | * Obere Lagerstr. 30 |
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13 | * D-82178 Puchheim |
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14 | * Germany |
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15 | * rtems@embedded-brains.de |
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16 | * |
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17 | * The license and distribution terms for this file may be found in the file |
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18 | * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE. |
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19 | * |
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20 | * $Id$ |
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21 | */ |
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22 | |
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23 | #include <string.h> |
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24 | |
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25 | #include <rtems/libio.h> |
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26 | #include <rtems/libcsupport.h> |
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27 | #include <rtems/score/thread.h> |
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28 | |
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29 | #include <libcpu/powerpc-utility.h> |
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30 | |
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31 | #include <bsp.h> |
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32 | #include <bsp/irq-generic.h> |
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33 | #include <bsp/ppc_exc_bspsupp.h> |
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34 | |
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35 | #ifdef HAS_UBOOT |
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36 | |
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37 | /* |
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38 | * We want this in the data section, because the startup code clears the BSS |
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39 | * section after the initialization of the board info. |
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40 | */ |
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41 | bd_t mpc83xx_uboot_board_info = { .bi_baudrate = 123 }; |
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42 | |
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43 | /* Size in words */ |
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44 | const size_t mpc83xx_uboot_board_info_size = (sizeof( bd_t) + 3) / 4; |
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45 | |
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46 | #endif /* HAS_UBOOT */ |
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47 | |
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48 | /* Configuration parameters for console driver, ... */ |
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49 | unsigned int BSP_bus_frequency; |
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50 | |
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51 | /* Configuration parameters for clock driver, ... */ |
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52 | uint32_t bsp_clicks_per_usec; |
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53 | |
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54 | static char *BSP_heap_start, *BSP_heap_end; |
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55 | |
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56 | /* |
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57 | * Use the shared implementations of the following routines. |
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58 | * Look in rtems/c/src/lib/libbsp/shared/bsplibc.c. |
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59 | */ |
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60 | extern void cpu_init( void); |
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61 | |
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62 | void BSP_panic( char *s) |
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63 | { |
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64 | rtems_interrupt_level level; |
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65 | |
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66 | rtems_interrupt_disable( level); |
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67 | |
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68 | printk( "%s PANIC %s\n", _RTEMS_version, s); |
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69 | |
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70 | while (1) { |
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71 | /* Do nothing */ |
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72 | } |
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73 | } |
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74 | |
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75 | void _BSP_Fatal_error( unsigned n) |
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76 | { |
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77 | rtems_interrupt_level level; |
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78 | |
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79 | rtems_interrupt_disable( level); |
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80 | |
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81 | printk( "%s PANIC ERROR %u\n", _RTEMS_version, n); |
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82 | |
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83 | while (1) { |
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84 | /* Do nothing */ |
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85 | } |
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86 | } |
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87 | |
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88 | void bsp_pretasking_hook( void) |
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89 | { |
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90 | /* Initialize libc including the heap */ |
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91 | bsp_libc_init( BSP_heap_start, BSP_heap_end - BSP_heap_start, 0); |
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92 | } |
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93 | |
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94 | void bsp_calc_mem_layout() |
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95 | { |
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96 | size_t workspace_size = rtems_configuration_get_work_space_size(); |
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97 | |
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98 | /* We clear the workspace here */ |
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99 | Configuration.do_zero_of_workspace = 0; |
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100 | /* |
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101 | TODO |
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102 | mpc83xx_zero_4( bsp_workspace_start, workspace_size); |
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103 | */ |
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104 | mpc83xx_zero_4( bsp_interrupt_stack_start, bsp_ram_end - bsp_interrupt_stack_start); |
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105 | |
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106 | Configuration.work_space_start = bsp_workspace_start; |
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107 | |
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108 | BSP_heap_start = (char *) Configuration.work_space_start + workspace_size; |
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109 | |
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110 | #ifdef HAS_UBOOT |
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111 | BSP_heap_end = mpc83xx_uboot_board_info.bi_memstart + mpc83xx_uboot_board_info.bi_memsize; |
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112 | #else /* HAS_UBOOT */ |
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113 | BSP_heap_end = bsp_ram_end; |
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114 | #endif /* HAS_UBOOT */ |
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115 | } |
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116 | |
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117 | void bsp_start( void) |
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118 | { |
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119 | ppc_cpu_id_t myCpu; |
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120 | ppc_cpu_revision_t myCpuRevision; |
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121 | |
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122 | uint32_t interrupt_stack_start = (uint32_t) bsp_interrupt_stack_start; |
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123 | uint32_t interrupt_stack_size = (uint32_t) bsp_interrupt_stack_size; |
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124 | |
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125 | /* |
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126 | * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function |
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127 | * store the result in global variables so that it can be used latter... |
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128 | */ |
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129 | myCpu = get_ppc_cpu_type(); |
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130 | myCpuRevision = get_ppc_cpu_revision(); |
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131 | |
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132 | /* Determine heap and workspace placement */ |
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133 | bsp_calc_mem_layout(); |
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134 | |
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135 | cpu_init(); |
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136 | |
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137 | /* |
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138 | * This is evaluated during runtime, so it should be ok to set it |
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139 | * before we initialize the drivers. |
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140 | */ |
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141 | |
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142 | /* Initialize some device driver parameters */ |
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143 | |
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144 | #ifdef HAS_UBOOT |
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145 | BSP_bus_frequency = mpc83xx_uboot_board_info.bi_busfreq; |
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146 | #else /* HAS_UBOOT */ |
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147 | BSP_bus_frequency = BSP_CLKIN_FRQ * BSP_SYSPLL_MF / BSP_SYSPLL_CKID; |
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148 | #endif /* HAS_UBOOT */ |
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149 | |
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150 | bsp_clicks_per_usec = BSP_bus_frequency / 4000000; |
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151 | |
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152 | /* |
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153 | * Enable instruction and data caches. Do not force writethrough mode. |
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154 | */ |
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155 | |
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156 | #if INSTRUCTION_CACHE_ENABLE |
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157 | rtems_cache_enable_instruction(); |
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158 | #endif |
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159 | |
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160 | #if DATA_CACHE_ENABLE |
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161 | rtems_cache_enable_data(); |
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162 | #endif |
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163 | |
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164 | /* Initialize exception handler */ |
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165 | ppc_exc_initialize( |
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166 | PPC_INTERRUPT_DISABLE_MASK_DEFAULT, |
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167 | interrupt_stack_start, |
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168 | interrupt_stack_size |
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169 | ); |
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170 | |
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171 | /* Initalize interrupt support */ |
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172 | if (bsp_interrupt_initialize() != RTEMS_SUCCESSFUL) { |
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173 | BSP_panic("Cannot intitialize interrupt support\n"); |
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174 | } |
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175 | |
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176 | #ifdef SHOW_MORE_INIT_SETTINGS |
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177 | printk("Exit from bspstart\n"); |
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178 | #endif |
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179 | } |
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180 | |
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181 | /** |
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182 | * @brief Idle thread body. |
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183 | * |
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184 | * Replaces the one in c/src/exec/score/src/threadidlebody.c |
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185 | * The MSR[POW] bit is set to put the CPU into the low power mode |
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186 | * defined in HID0. HID0 is set during starup in start.S. |
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187 | */ |
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188 | Thread _Thread_Idle_body( uint32_t ignored) |
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189 | { |
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190 | |
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191 | while (1) { |
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192 | asm volatile ( |
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193 | "mfmsr 3;" |
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194 | "oris 3, 3, 4;" |
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195 | "sync;" |
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196 | "mtmsr 3;" |
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197 | "isync;" |
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198 | "ori 3, 3, 0;" |
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199 | "ori 3, 3, 0" |
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200 | ); |
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201 | } |
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202 | |
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203 | return NULL; |
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204 | } |
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