source: rtems/c/src/lib/libbsp/powerpc/gen83xx/startup/bspstart.c @ 574fb67

4.104.114.9
Last change on this file since 574fb67 was 574fb67, checked in by Thomas Doerfler <Thomas.Doerfler@…>, on Jul 14, 2008 at 4:15:28 PM

updated gen83xx BSP
updated haleakala BSP
added MPC55xx BSP

  • Property mode set to 100644
File size: 4.3 KB
RevLine 
[574fb67]1/**
2 * @file
3 *
4 * @ingroup mpc83xx
5 *
6 * @brief Source for BSP startup code.
7 */
[f610e83f]8
[dfef80e8]9/*
[574fb67]10 * Copyright (c) 2008
11 * Embedded Brains GmbH
12 * Obere Lagerstr. 30
13 * D-82178 Puchheim
14 * Germany
15 * rtems@embedded-brains.de
16 *
17 * The license and distribution terms for this file may be found in the file
18 * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
19 *
20 * $Id$
[dfef80e8]21 */
22
[574fb67]23#include <string.h>
[f610e83f]24
25#include <rtems/libio.h>
26#include <rtems/libcsupport.h>
27#include <rtems/score/thread.h>
28
[574fb67]29#include <libcpu/powerpc-utility.h>
[f610e83f]30
[574fb67]31#include <bsp.h>
32#include <bsp/irq-generic.h>
33#include <bsp/ppc_exc_bspsupp.h>
[f610e83f]34
[574fb67]35#ifdef HAS_UBOOT
[f610e83f]36
37/*
[574fb67]38 * We want this in the data section, because the startup code clears the BSS
39 * section after the initialization of the board info.
[f610e83f]40 */
[574fb67]41bd_t mpc83xx_uboot_board_info = { .bi_baudrate = 123 };
42
43/* Size in words */
44const size_t mpc83xx_uboot_board_info_size = (sizeof( bd_t) + 3) / 4;
45
46#endif /* HAS_UBOOT */
47
48/* Configuration parameters for console driver, ... */
[42bf1b9]49unsigned int BSP_bus_frequency;
[f610e83f]50
[574fb67]51/* Configuration parameters for clock driver, ... */
52uint32_t bsp_clicks_per_usec;
53
54static char *BSP_heap_start, *BSP_heap_end;
[07e9642c]55
[f610e83f]56/*
57 *  Use the shared implementations of the following routines.
[67a9b24a]58 *  Look in rtems/c/src/lib/libbsp/shared/bsplibc.c.
[f610e83f]59 */
[574fb67]60extern void cpu_init( void);
[f610e83f]61
[574fb67]62void BSP_panic( char *s)
63{
64        rtems_interrupt_level level;
[f610e83f]65
[574fb67]66        rtems_interrupt_disable( level);
67
68        printk( "%s PANIC %s\n", _RTEMS_version, s);
69
70        while (1) {
71                /* Do nothing */
72        }
73}
74
75void _BSP_Fatal_error( unsigned n)
[f610e83f]76{
[574fb67]77        rtems_interrupt_level level;
[f610e83f]78
[574fb67]79        rtems_interrupt_disable( level);
80
81        printk( "%s PANIC ERROR %u\n", _RTEMS_version, n);
82
83        while (1) {
84                /* Do nothing */
85        }
86}
87
88void bsp_pretasking_hook( void)
89{
90        /* Initialize libc including the heap */
91        bsp_libc_init( BSP_heap_start, BSP_heap_end - BSP_heap_start, 0);
[f610e83f]92}
93
94void bsp_calc_mem_layout()
95{
[574fb67]96        size_t workspace_size = rtems_configuration_get_work_space_size();
[f610e83f]97
[574fb67]98        /* We clear the workspace here */
99        Configuration.do_zero_of_workspace = 0;
100        /*
101        TODO
102        mpc83xx_zero_4( bsp_workspace_start, workspace_size);
103         */
104        mpc83xx_zero_4( bsp_interrupt_stack_start, bsp_ram_end - bsp_interrupt_stack_start);
[f610e83f]105
[574fb67]106        Configuration.work_space_start = bsp_workspace_start;
[f610e83f]107
[574fb67]108        BSP_heap_start = (char *) Configuration.work_space_start + workspace_size;
109
110#ifdef HAS_UBOOT
111        BSP_heap_end = mpc83xx_uboot_board_info.bi_memstart + mpc83xx_uboot_board_info.bi_memsize;
112#else /* HAS_UBOOT */
113        BSP_heap_end = bsp_ram_end;
114#endif /* HAS_UBOOT */
115}
116
117void bsp_start( void)
[f610e83f]118{
[574fb67]119        ppc_cpu_id_t myCpu;
120        ppc_cpu_revision_t myCpuRevision;
121
122        uint32_t interrupt_stack_start = (uint32_t) bsp_interrupt_stack_start;
123        uint32_t interrupt_stack_size = (uint32_t) bsp_interrupt_stack_size;
124
125        /*
126         * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function
127         * store the result in global variables so that it can be used latter...
128         */
129        myCpu = get_ppc_cpu_type();
130        myCpuRevision = get_ppc_cpu_revision();
131
132        /* Determine heap and workspace placement */
133        bsp_calc_mem_layout();
134
135        cpu_init();
136
137        /*
138         * This is evaluated during runtime, so it should be ok to set it
139         * before we initialize the drivers.
140         */
141
142        /* Initialize some device driver parameters */
143
144#ifdef HAS_UBOOT
145        BSP_bus_frequency = mpc83xx_uboot_board_info.bi_busfreq;
146#else /* HAS_UBOOT */
147        BSP_bus_frequency = BSP_CLKIN_FRQ * BSP_SYSPLL_MF / BSP_SYSPLL_CKID;
148#endif /* HAS_UBOOT */
149
150        bsp_clicks_per_usec = BSP_bus_frequency / 4000000;
151
152        /*
153         * Enable instruction and data caches. Do not force writethrough mode.
154         */
155
[f610e83f]156#if INSTRUCTION_CACHE_ENABLE
[574fb67]157        rtems_cache_enable_instruction();
[f610e83f]158#endif
[574fb67]159
[f610e83f]160#if DATA_CACHE_ENABLE
[574fb67]161        rtems_cache_enable_data();
[f610e83f]162#endif
163
[574fb67]164        /* Initialize exception handler */
165        ppc_exc_initialize(
166                PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
167                interrupt_stack_start,
168                interrupt_stack_size
169        );
[f610e83f]170
[574fb67]171        /* Initalize interrupt support */
172        if (bsp_interrupt_initialize() != RTEMS_SUCCESSFUL) {
173                BSP_panic("Cannot intitialize interrupt support\n");
174        }
[f610e83f]175
176#ifdef SHOW_MORE_INIT_SETTINGS
[574fb67]177        printk("Exit from bspstart\n");
[f610e83f]178#endif
[574fb67]179}
[f610e83f]180
[574fb67]181/**
182 * @brief Idle thread body.
[f610e83f]183 *
[574fb67]184 * Replaces the one in c/src/exec/score/src/threadidlebody.c
185 * The MSR[POW] bit is set to put the CPU into the low power mode
186 * defined in HID0.  HID0 is set during starup in start.S.
[f610e83f]187 */
[574fb67]188Thread _Thread_Idle_body( uint32_t ignored)
189{
[f610e83f]190
[574fb67]191        while (1) {
192                asm volatile (
193                        "mfmsr 3;"
194                        "oris 3, 3, 4;"
195                        "sync;"
196                        "mtmsr 3;"
197                        "isync;"
198                        "ori 3, 3, 0;"
199                        "ori 3, 3, 0"
200                );
201        }
202
203        return NULL;
204}
Note: See TracBrowser for help on using the repository browser.