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start.S @ f610e83f

4.104.114.84.95

Last change on this file since f610e83f was f610e83f, checked in by Thomas Doerfler <Thomas.Doerfler@…>, on 07/10/07 at 16:00:28
compilable release of virtex/gen83xx/gen5200 powerpc adaptations. Merged many different versions of new exception handling code to shared sources.
Property mode set to `100644`
File size: 10.3 KB

Line
1	/===============================================================\
2	\| Project: RTEMS generic MPC83xx BSP \|
3	+-----------------------------------------------------------------+
4	\| Copyright (c) 2007 \|
5	\| Embedded Brains GmbH \|
6	\| Obere Lagerstr. 30 \|
7	\| D-82178 Puchheim \|
8	\| Germany \|
9	\| rtems@embedded-brains.de \|
10	+-----------------------------------------------------------------+
11	\| The license and distribution terms for this file may be \|
12	\| found in the file LICENSE in this distribution or at \|
13	\| \|
14	\| http://www.rtems.com/license/LICENSE. \|
15	\| \|
16	+-----------------------------------------------------------------+
17	\| this file contains the startup assembly code \|
18	\===============================================================/
19	/* $Id$ */
20
21	#include <rtems/asm.h>
22	#include <rtems/powerpc/cache.h>
23	#include <rtems/powerpc/registers.h>
24	#include <mpc83xx/mpc83xx.h>
25	#include <bsp.h>
26
27	/* Macro definitions to load a register with a 32-bit address.
28	Both functions identically. Sometimes one mnemonic is more
29	appropriate than the other.
30	reg -> register to load
31	value -> value to be loaded
32	LA reg,value ("Load Address")
33	LWI reg,value ("Load Word Immediate") */
34
35	.macro LA reg, value
36	lis \reg , \value@h
37	ori \reg , \reg, \value@l
38	.endm
39
40	.macro LWI reg, value
41	lis \reg , (\value)@h
42	ori \reg , \reg, (\value)@l
43	.endm
44
45	.macro SET_IMM_REGW base, reg2, offset, value
46	LA \reg2, \value
47	stw \reg2,\offset(\base)
48	.endm
49
50	/* Macro definitions to test, set or clear a single
51	bit or bit pattern in a given 32bit GPR.
52	reg1 -> register content to be tested
53	reg2 -> 2nd register only needed for computation
54	mask -> any bit pattern */
55
56	.macro TSTBITS reg1, reg2, reg3, mask /* Match is indicated by EQ=0 (CR) */
57	LWI \reg3, \mask /* Unmatch is indicated by EQ=1 (CR) */
58	and \reg1, \reg1, \reg3
59	and \reg2, \reg2, \reg3
60	cmplw \reg1, \reg2
61	sync
62	.endm
63
64	.macro SETBITS reg1, reg2, mask
65	LWI \reg2, \mask
66	or \reg1, \reg1, \reg2
67	sync
68	.endm
69
70	.macro CLRBITS reg1, reg2, mask
71	LWI \reg2, \mask
72	andc \reg1, \reg1, \reg2
73	sync
74	.endm
75
76	.extern _bss_start
77	.extern _bss_size
78	.extern _data_start
79	.extern _data_size
80	.extern _text_start
81	.extern _text_size
82	/.extern _s_got/
83	.extern boot_card
84	.extern MBAR
85
86	.section ".vectors"
87	PUBLIC_VAR (reset_vec)
88	reset_vec:
89	bl start
90	.section ".entry"
91	PUBLIC_VAR (start)
92	start:
93	/*
94	* FIXME: basic CPU setup:
95	* init MSR
96	*/
97	mfmsr r30
98	SETBITS r30, r29, MSR_ME\|MSR_RI
99	CLRBITS r30, r29, MSR_IP\|MSR_EE
100	mtmsr r30 /* Set RI/ME, Clr EE in MSR */
101	/*
102	* check, wether we are starting from ROM
103	* detect this using the absolute code address:
104	* when the upper 4 bits are 0xF, then we are in ROM
105	*/
106	bl 1f
107	1: mflr r28
108	LWI r29,0xF0000000
109	TSTBITS r28,r29,r30,0xF0000000
110	bne start_rom_skip
111	/*
112	* ROM startup: remap IMMR to 0xE0000000
113	* use special sequence from MPC8349EA RM Rev 1, 5.2.4.1.1 "Updating IMMRBAR"
114	*/
115	LWI r30,IMMRBAR_DEFAULT
116	LWI r31,IMMRBAR
117	lwz r29,0(r30)
118	stw r31,0(r30)
119	lwz r29,0(r28) /* read from ROM... */
120	isync
121	lwz r29,0(r31) /* read from IMMRBAR... */
122	isync
123	/*
124	* NOTE: now r31 points to onchip registers
125
126	/*
127	* ROM startup: init local access windows
128	*/
129	#ifdef LBLAWBAR0_VAL
130	SET_IMM_REGW r31,r30,LBLAWBAR0_OFF,LBLAWBAR0_VAL
131	#endif
132	#ifdef LBLAWAR0_VAL
133	SET_IMM_REGW r31,r30,LBLAWAR0_OFF,LBLAWAR0_VAL
134	#endif
135	#ifdef LBLAWBAR1_VAL
136	SET_IMM_REGW r31,r30,LBLAWBAR1_OFF,LBLAWBAR1_VAL
137	#endif
138	#ifdef LBLAWAR1_VAL
139	SET_IMM_REGW r31,r30,LBLAWAR1_OFF,LBLAWAR1_VAL
140	#endif
141	#ifdef LBLAWBAR2_VAL
142	SET_IMM_REGW r31,r30,LBLAWBAR2_OFF,LBLAWBAR2_VAL
143	#endif
144	#ifdef LBLAWAR2_VAL
145	SET_IMM_REGW r31,r30,LBLAWAR2_OFF,LBLAWAR2_VAL
146	#endif
147	#ifdef LBLAWBAR3_VAL
148	SET_IMM_REGW r31,r30,LBLAWBAR3_OFF,LBLAWBAR3_VAL
149	#endif
150	#ifdef LBLAWAR3_VAL
151	SET_IMM_REGW r31,r30,LBLAWAR3_OFF,LBLAWAR3_VAL
152	#endif
153	/*
154	* ROM startup: init bus system
155	*/
156	#ifdef BR0_VAL
157	SET_IMM_REGW r31,r30,BR0_OFF,BR0_VAL
158	#endif
159	#ifdef OR0_VAL
160	SET_IMM_REGW r31,r30,OR0_OFF,OR0_VAL
161	#endif
162	#ifdef BR1_VAL
163	SET_IMM_REGW r31,r30,BR1_OFF,BR1_VAL
164	#endif
165	#ifdef OR1_VAL
166	SET_IMM_REGW r31,r30,OR1_OFF,OR1_VAL
167	#endif
168	#ifdef BR2_VAL
169	SET_IMM_REGW r31,r30,BR2_OFF,BR2_VAL
170	#endif
171	#ifdef OR2_VAL
172	SET_IMM_REGW r31,r30,OR2_OFF,OR2_VAL
173	#endif
174	#ifdef BR3_VAL
175	SET_IMM_REGW r31,r30,BR3_OFF,BR3_VAL
176	#endif
177	#ifdef OR3_VAL
178	SET_IMM_REGW r31,r30,OR3_OFF,OR3_VAL
179	#endif
180	/*
181	* ROM startup: init SDRAM access window
182	*/
183	#ifdef DDRLAWBAR0_VAL
184	SET_IMM_REGW r31,r30,DDRLAWBAR0_OFF,DDRLAWBAR0_VAL
185	#endif
186	#ifdef DDRLAWAR0_VAL
187	SET_IMM_REGW r31,r30,DDRLAWAR0_OFF,DDRLAWAR0_VAL
188	#endif
189	#ifdef DDRLAWBAR1_VAL
190	SET_IMM_REGW r31,r30,DDRLAWBAR1_OFF,DDRLAWBAR1_VAL
191	#endif
192	#ifdef DDRLAWAR1_VAL
193	SET_IMM_REGW r31,r30,DDRLAWAR1_OFF,DDRLAWAR1_VAL
194	#endif
195	/*
196	* ROM startup: init SDRAM
197	*/
198	#ifdef CS0_BNDS_VAL
199	SET_IMM_REGW r31,r30,CS0_BNDS_OFF,CS0_BNDS_VAL
200	#endif
201	#ifdef CS1_BNDS_VAL
202	SET_IMM_REGW r31,r30,CS1_BNDS_OFF,CS1_BNDS_VAL
203	#endif
204	#ifdef CS2_BNDS_VAL
205	SET_IMM_REGW r31,r30,CS2_BNDS_OFF,CS2_BNDS_VAL
206	#endif
207	#ifdef CS3_BNDS_VAL
208	SET_IMM_REGW r31,r30,CS3_BNDS_OFF,CS3_BNDS_VAL
209	#endif
210	#ifdef CS0_CONFIG_VAL
211	SET_IMM_REGW r31,r30,CS0_CONFIG_OFF,CS0_CONFIG_VAL
212	#endif
213	#ifdef CS1_CONFIG_VAL
214	SET_IMM_REGW r31,r30,CS1_CONFIG_OFF,CS1_CONFIG_VAL
215	#endif
216	#ifdef CS2_CONFIG_VAL
217	SET_IMM_REGW r31,r30,CS2_CONFIG_OFF,CS2_CONFIG_VAL
218	#endif
219	#ifdef CS3_CONFIG_VAL
220	SET_IMM_REGW r31,r30,CS3_CONFIG_OFF,CS3_CONFIG_VAL
221	#endif
222	#ifdef TIMING_CFG_3_VAL
223	SET_IMM_REGW r31,r30,TIMING_CFG_3_OFF,TIMING_CFG_3_VAL
224	#endif
225	#ifdef TIMING_CFG_0_VAL
226	SET_IMM_REGW r31,r30,TIMING_CFG_0_OFF,TIMING_CFG_0_VAL
227	#endif
228	#ifdef TIMING_CFG_1_VAL
229	SET_IMM_REGW r31,r30,TIMING_CFG_1_OFF,TIMING_CFG_1_VAL
230	#endif
231	#ifdef TIMING_CFG_2_VAL
232	SET_IMM_REGW r31,r30,TIMING_CFG_2_OFF,TIMING_CFG_2_VAL
233	#endif
234	#ifdef DDR_SDRAM_CFG_VAL
235	SET_IMM_REGW r31,r30,DDR_SDRAM_CFG_OFF,DDR_SDRAM_CFG_VAL
236	#endif
237	#ifdef DDR_SDRAM_CFG_2_VAL
238	SET_IMM_REGW r31,r30,DDR_SDRAM_CFG_2_OFF,DDR_SDRAM_CFG_2_VAL
239	#endif
240	#ifdef DDR_SDRAM_MODE_VAL
241	SET_IMM_REGW r31,r30,DDR_SDRAM_MODE_OFF,DDR_SDRAM_MODE_VAL
242	#endif
243	#ifdef DDR_SDRAM_MODE_2_VAL
244	SET_IMM_REGW r31,r30,DDR_SDRAM_MODE_2_OFF,DDR_SDRAM_MODE_2_VAL
245	#endif
246	#ifdef DDR_SDRAM_MD_CNTL_VAL
247	SET_IMM_REGW r31,r30,DDR_SDRAM_MD_CNTL_OFF,DDR_SDRAM_MD_CNTL_VAL
248	#endif
249	#ifdef DDR_SDRAM_MD_ITVL_VAL
250	SET_IMM_REGW r31,r30,DDR_SDRAM_MD_ITVL_OFF,DDR_SDRAM_MD_ITVL_VAL
251	#endif
252	#ifdef DDR_SDRAM_CLK_CNTL_VAL
253	SET_IMM_REGW r31,r30,DDR_SDRAM_CLK_CNTL_OFF,DDR_SDRAM_CLK_CNTL_VAL
254	#endif
255	#ifdef DDR_SDRAM_INIT_ADDR_VAL
256	SET_IMM_REGW r31,r30,DDR_SDRAM_INIT_ADDR_OFF,DDR_SDRAM_INIT_ADDR_VAL
257	#endif
258	/*
259	* FIXME: ROM startup: perform mode set commands etc for SDRAM
260	*/
261	/*
262	* ROM startup: copy code to SDRAM
263	*/
264	LA r30, _text_start /* get start address of text section in RAM */
265	add r30, r20, r30 /* get start address of text section in ROM (add reloc offset) */
266	LA r29, _text_start /* get start address of text section in RAM */
267	LA r28, _text_size /* get size of RAM image */
268	bl copy_image /* copy text section from ROM to RAM location */
269
270	/*
271	* FIXME: ROM startup: copy data to SDRAM
272	*/
273	LA r30, _data_start /* get start address of data section in RAM */
274	add r30, r20, r30 /* get start address of data section in ROM (add reloc offset) */
275	LA r29, _data_start /* get start address of data section in RAM */
276	LA r28, _data_size /* get size of RAM image */
277	bl copy_image /* copy initialized data section from ROM to RAM location */
278	start_rom_skip:
279	/*
280	* ROM startup: clear bss in SDRAM
281	*/
282	LWI r30, _bss_start /* get start address of bss section */
283	LWI r29, _bss_size /* get size of bss section */
284	bl clr_mem /* Clear the bss section */
285	/*
286	* ROM startup: jump to code copy in SDRAM
287	*/
288	LA r29, start_code_in_ram /* get compile time address of label */
289	mtlr r29
290	blr /* now further execution RAM */
291	start_code_in_ram:
292	/*
293	* call boot_card
294	*/
295	/* set stack pointer (common for RAM/ROM startup) */
296	LA r1, _text_start
297	addi r1, r1, -0x10 /* Set up stack pointer = beginning of text section - 0x10 */
298	/* clear arguments and do further init. in C (common for RAM/ROM startup) */
299	xor r3, r3, r3
300	xor r4, r4, r4 /* Clear argc and argv */
301	bl SYM (boot_card) /* Call the first C routine */
302
303	twiddle:
304	/* We don't expect to return from boot_card but if we do */
305	/* wait here for watchdog to kick us into hard reset */
306	b twiddle
307
308	copy_image:
309	mr r27, r28
310	srwi r28, r28, 2
311	mtctr r28
312
313	slwi r28, r28, 2
314	sub r27, r27, r28 /* maybe some residual bytes */
315	copy_image_word:
316	lswi r28, r30, 0x04
317
318	stswi r28, r29, 0x04 /* do word copy ROM -> RAM */
319
320
321	addi r30, r30, 0x04 /* increment source pointer */
322	addi r29, r29, 0x04 /* increment destination pointer */
323
324	bdnz copy_image_word /* decrement ctr and branch if not 0 */
325
326	cmpwi r27, 0x00 /* copy image finished ? */
327	beq copy_image_end;
328	mtctr r27 /* reload counter for residual bytes */
329	copy_image_byte:
330	lswi r28, r30, 0x01
331
332	stswi r28, r29, 0x01 /* do byte copy ROM -> RAM */
333
334
335	addi r30, r30, 0x01 /* increment source pointer */
336	addi r29, r29, 0x01 /* increment destination pointer */
337
338	bdnz copy_image_byte /* decrement ctr and branch if not 0 */
339
340	copy_image_end:
341	blr
342
343	clr_mem:
344	mr r28, r29
345	srwi r29, r29, 2
346	mtctr r29 /* set ctr reg */
347
348
349	slwi r29, r29, 2
350	sub r28, r28, r29 /* maybe some residual bytes */
351	xor r29, r29, r29
352
353
354	clr_mem_word:
355	stswi r29, r30, 0x04 /* store r29 (word) to r30 memory location */
356	addi r30, r30, 0x04 /* increment r30 */
357
358	bdnz clr_mem_word /* dec counter and loop */
359
360
361	cmpwi r28, 0x00 /* clear mem. finished ? */
362	beq clr_mem_end;
363	mtctr r28 /* reload counter for residual bytes */
364	clr_mem_byte:
365	stswi r29, r30, 0x01 /* store r29 (byte) to r30 memory location */
366	addi r30, r30, 0x01 /* update r30 */
367
368	bdnz clr_mem_byte /* dec counter and loop */
369
370	clr_mem_end:
371	blr /* return */

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