1 | /*===============================================================*\ |
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2 | | Project: RTEMS generic MPC83xx BSP | |
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3 | +-----------------------------------------------------------------+ |
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4 | | Copyright (c) 2007 | |
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5 | | Embedded Brains GmbH | |
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6 | | Obere Lagerstr. 30 | |
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7 | | D-82178 Puchheim | |
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8 | | Germany | |
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9 | | rtems@embedded-brains.de | |
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10 | +-----------------------------------------------------------------+ |
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11 | | The license and distribution terms for this file may be | |
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12 | | found in the file LICENSE in this distribution or at | |
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13 | | | |
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14 | | http://www.rtems.com/license/LICENSE. | |
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15 | | | |
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16 | +-----------------------------------------------------------------+ |
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17 | | this file contains the startup assembly code | |
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18 | \*===============================================================*/ |
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19 | |
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20 | |
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21 | #include <libcpu/powerpc-utility.h> |
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22 | #include <rtems/powerpc/cache.h> |
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23 | #include <bsp.h> |
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24 | #include <mpc83xx/mpc83xx.h> |
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25 | |
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26 | .macro SET_IMM_REGW base, reg2, offset, value |
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27 | LA \reg2, \value |
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28 | stw \reg2,\offset(\base) |
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29 | .endm |
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30 | |
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31 | #define REP8(l) l ; l; l; l; l; l; l; l; |
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32 | |
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33 | .extern boot_card |
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34 | .extern MBAR |
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35 | |
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36 | #if defined(RESET_CONF_WRD_L) |
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37 | .section ".resconf","ax" |
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38 | PUBLIC_VAR (reset_conf_words) |
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39 | reset_conf_words: |
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40 | REP8( .byte ((RESET_CONF_WRD_L >> 24) & 0xff)) |
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41 | REP8( .byte ((RESET_CONF_WRD_L >> 16) & 0xff)) |
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42 | REP8( .byte ((RESET_CONF_WRD_L >> 8) & 0xff)) |
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43 | REP8( .byte ((RESET_CONF_WRD_L >> 0) & 0xff)) |
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44 | |
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45 | REP8( .byte ((RESET_CONF_WRD_H >> 24) & 0xff)) |
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46 | REP8( .byte ((RESET_CONF_WRD_H >> 16) & 0xff)) |
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47 | REP8( .byte ((RESET_CONF_WRD_H >> 8) & 0xff)) |
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48 | REP8( .byte ((RESET_CONF_WRD_H >> 0) & 0xff)) |
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49 | #endif |
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50 | |
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51 | .section ".vectors","ax" |
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52 | PUBLIC_VAR (reset_vec) |
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53 | reset_vec: |
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54 | bl rom_entry |
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55 | |
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56 | .section ".entry" |
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57 | PUBLIC_VAR (start) |
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58 | start: |
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59 | |
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60 | /* Reset time base */ |
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61 | li r0, 0 |
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62 | mtspr TBWU, r0 |
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63 | mtspr TBWL, r0 |
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64 | |
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65 | #ifdef HAS_UBOOT |
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66 | mr r14, r3 |
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67 | #endif /* HAS_UBOOT */ |
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68 | |
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69 | /* |
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70 | * basic CPU setup: |
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71 | * init MSR |
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72 | */ |
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73 | mfmsr r30 |
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74 | SETBITS r30, r29, MSR_ME|MSR_RI |
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75 | CLRBITS r30, r29, MSR_IP|MSR_EE |
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76 | mtmsr r30 /* Set RI/ME, Clr EE in MSR */ |
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77 | |
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78 | b start_rom_skip |
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79 | |
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80 | PUBLIC_VAR (rom_entry) |
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81 | rom_entry: |
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82 | /* |
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83 | * basic CPU setup: |
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84 | * init MSR |
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85 | */ |
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86 | mfmsr r30 |
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87 | SETBITS r30, r29, MSR_ME|MSR_RI |
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88 | CLRBITS r30, r29, MSR_IP|MSR_EE |
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89 | mtmsr r30 /* Set RI/ME, Clr EE in MSR */ |
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90 | |
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91 | /* |
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92 | * ROM startup: remap IMMR to 0xE0000000 |
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93 | * use special sequence from MPC8349EA RM Rev 1, 5.2.4.1.1 "Updating IMMRBAR" |
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94 | */ |
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95 | LWI r30,IMMRBAR_DEFAULT |
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96 | LWI r31,IMMRBAR |
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97 | lwz r29,0(r30) |
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98 | stw r31,0(r30) |
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99 | #if 0 |
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100 | lwz r29,0(r28) /* read from ROM... */ |
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101 | #endif |
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102 | isync |
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103 | lwz r29,0(r31) /* read from IMMRBAR... */ |
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104 | isync |
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105 | /* |
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106 | * NOTE: now r31 points to onchip registers |
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107 | */ |
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108 | /* |
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109 | * we start from 0x100, so ROM is currently mapped to |
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110 | * 0x00000000.. |
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111 | * in the next step, ROM will be remapped to its final location |
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112 | * at 0xfe000000... (using LBLAWBAR1 with LBLAWBAR0 value) |
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113 | * and we jump to that location. |
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114 | * then we remove the ROM mapping to zero |
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115 | */ |
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116 | #ifdef LBLAWBAR0_VAL |
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117 | SET_IMM_REGW r31,r30,LBLAWBAR1_OFF,LBLAWBAR0_VAL |
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118 | #endif |
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119 | #ifdef LBLAWAR0_VAL |
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120 | SET_IMM_REGW r31,r30,LBLAWAR1_OFF,LBLAWAR0_VAL |
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121 | #endif |
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122 | |
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123 | |
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124 | /* |
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125 | * ROM startup: jump to code final ROM location |
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126 | */ |
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127 | LA r20, bsp_rom_start /* ROM-RAM reloc in r20 */ |
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128 | LA r29, start_code_in_rom /* get compile time addr of label */ |
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129 | add r29,r20,r29 /* compute exec address */ |
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130 | mtlr r29 |
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131 | blr /* now further execution in upper ROM */ |
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132 | |
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133 | start_code_in_rom: |
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134 | |
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135 | #ifdef LBLAWBAR0_VAL |
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136 | SET_IMM_REGW r31,r30,LBLAWBAR0_OFF,LBLAWBAR0_VAL |
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137 | #endif |
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138 | #ifdef LBLAWAR0_VAL |
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139 | SET_IMM_REGW r31,r30,LBLAWAR0_OFF,LBLAWAR0_VAL |
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140 | #endif |
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141 | #ifdef LBLAWBAR1_VAL |
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142 | SET_IMM_REGW r31,r30,LBLAWBAR1_OFF,LBLAWBAR1_VAL |
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143 | #endif |
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144 | #ifdef LBLAWAR1_VAL |
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145 | SET_IMM_REGW r31,r30,LBLAWAR1_OFF,LBLAWAR1_VAL |
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146 | #endif |
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147 | #ifdef LBLAWBAR2_VAL |
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148 | SET_IMM_REGW r31,r30,LBLAWBAR2_OFF,LBLAWBAR2_VAL |
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149 | #endif |
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150 | #ifdef LBLAWAR2_VAL |
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151 | SET_IMM_REGW r31,r30,LBLAWAR2_OFF,LBLAWAR2_VAL |
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152 | #endif |
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153 | #ifdef LBLAWBAR3_VAL |
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154 | SET_IMM_REGW r31,r30,LBLAWBAR3_OFF,LBLAWBAR3_VAL |
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155 | #endif |
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156 | #ifdef LBLAWAR3_VAL |
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157 | SET_IMM_REGW r31,r30,LBLAWAR3_OFF,LBLAWAR3_VAL |
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158 | #endif |
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159 | /* |
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160 | * ROM startup: init bus system |
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161 | */ |
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162 | #ifdef BR0_VAL |
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163 | SET_IMM_REGW r31,r30,BR0_OFF,BR0_VAL |
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164 | #endif |
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165 | #ifdef OR0_VAL |
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166 | SET_IMM_REGW r31,r30,OR0_OFF,OR0_VAL |
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167 | #endif |
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168 | #ifdef BR1_VAL |
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169 | SET_IMM_REGW r31,r30,BR1_OFF,BR1_VAL |
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170 | #endif |
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171 | #ifdef OR1_VAL |
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172 | SET_IMM_REGW r31,r30,OR1_OFF,OR1_VAL |
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173 | #endif |
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174 | #ifdef BR2_VAL |
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175 | SET_IMM_REGW r31,r30,BR2_OFF,BR2_VAL |
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176 | #endif |
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177 | #ifdef OR2_VAL |
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178 | SET_IMM_REGW r31,r30,OR2_OFF,OR2_VAL |
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179 | #endif |
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180 | #ifdef BR3_VAL |
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181 | SET_IMM_REGW r31,r30,BR3_OFF,BR3_VAL |
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182 | #endif |
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183 | #ifdef OR3_VAL |
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184 | SET_IMM_REGW r31,r30,OR3_OFF,OR3_VAL |
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185 | #endif |
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186 | #ifdef BR4_VAL |
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187 | SET_IMM_REGW r31,r30,BR4_OFF,BR4_VAL |
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188 | #endif |
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189 | #ifdef OR4_VAL |
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190 | SET_IMM_REGW r31,r30,OR4_OFF,OR4_VAL |
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191 | #endif |
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192 | #ifdef BR5_VAL |
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193 | SET_IMM_REGW r31,r30,BR5_OFF,BR5_VAL |
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194 | #endif |
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195 | #ifdef OR5_VAL |
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196 | SET_IMM_REGW r31,r30,OR5_OFF,OR5_VAL |
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197 | #endif |
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198 | /* |
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199 | * ROM startup: init SDRAM access window |
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200 | */ |
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201 | #ifdef DDRLAWBAR0_VAL |
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202 | SET_IMM_REGW r31,r30,DDRLAWBAR0_OFF,DDRLAWBAR0_VAL |
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203 | #endif |
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204 | #ifdef DDRLAWAR0_VAL |
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205 | SET_IMM_REGW r31,r30,DDRLAWAR0_OFF,DDRLAWAR0_VAL |
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206 | #endif |
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207 | #ifdef DDRLAWBAR1_VAL |
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208 | SET_IMM_REGW r31,r30,DDRLAWBAR1_OFF,DDRLAWBAR1_VAL |
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209 | #endif |
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210 | #ifdef DDRLAWAR1_VAL |
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211 | SET_IMM_REGW r31,r30,DDRLAWAR1_OFF,DDRLAWAR1_VAL |
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212 | #endif |
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213 | /* |
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214 | * ROM startup: init refresh interval |
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215 | */ |
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216 | #ifdef MRPTR_VAL |
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217 | SET_IMM_REGW r31,r30,MRPTR_OFF,MRPTR_VAL |
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218 | #endif |
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219 | /* |
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220 | * ROM startup: init SDRAM |
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221 | */ |
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222 | #ifdef LSRT_VAL |
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223 | SET_IMM_REGW r31,r30, LSRT_OFF, LSRT_VAL |
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224 | #endif |
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225 | #ifdef LSDMR_VAL |
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226 | SET_IMM_REGW r31,r30, LSDMR_OFF, LSDMR_VAL |
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227 | #endif |
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228 | #ifdef CS0_BNDS_VAL |
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229 | SET_IMM_REGW r31,r30,CS0_BNDS_OFF,CS0_BNDS_VAL |
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230 | #endif |
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231 | #ifdef CS1_BNDS_VAL |
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232 | SET_IMM_REGW r31,r30,CS1_BNDS_OFF,CS1_BNDS_VAL |
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233 | #endif |
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234 | #ifdef CS2_BNDS_VAL |
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235 | SET_IMM_REGW r31,r30,CS2_BNDS_OFF,CS2_BNDS_VAL |
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236 | #endif |
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237 | #ifdef CS3_BNDS_VAL |
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238 | SET_IMM_REGW r31,r30,CS3_BNDS_OFF,CS3_BNDS_VAL |
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239 | #endif |
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240 | #ifdef CS0_CONFIG_VAL |
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241 | SET_IMM_REGW r31,r30,CS0_CONFIG_OFF,CS0_CONFIG_VAL |
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242 | #endif |
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243 | #ifdef CS1_CONFIG_VAL |
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244 | SET_IMM_REGW r31,r30,CS1_CONFIG_OFF,CS1_CONFIG_VAL |
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245 | #endif |
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246 | #ifdef CS2_CONFIG_VAL |
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247 | SET_IMM_REGW r31,r30,CS2_CONFIG_OFF,CS2_CONFIG_VAL |
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248 | #endif |
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249 | #ifdef CS3_CONFIG_VAL |
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250 | SET_IMM_REGW r31,r30,CS3_CONFIG_OFF,CS3_CONFIG_VAL |
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251 | #endif |
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252 | #ifdef TIMING_CFG_3_VAL |
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253 | SET_IMM_REGW r31,r30,TIMING_CFG_3_OFF,TIMING_CFG_3_VAL |
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254 | #endif |
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255 | #ifdef TIMING_CFG_0_VAL |
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256 | SET_IMM_REGW r31,r30,TIMING_CFG_0_OFF,TIMING_CFG_0_VAL |
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257 | #endif |
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258 | #ifdef TIMING_CFG_1_VAL |
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259 | SET_IMM_REGW r31,r30,TIMING_CFG_1_OFF,TIMING_CFG_1_VAL |
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260 | #endif |
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261 | #ifdef TIMING_CFG_2_VAL |
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262 | SET_IMM_REGW r31,r30,TIMING_CFG_2_OFF,TIMING_CFG_2_VAL |
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263 | #endif |
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264 | #ifdef DDRCDR_VAL |
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265 | SET_IMM_REGW r31,r30,DDRCDR_OFF,DDRCDR_VAL |
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266 | #endif |
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267 | #ifdef DDR_SDRAM_CFG_2_VAL |
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268 | SET_IMM_REGW r31,r30,DDR_SDRAM_CFG_2_OFF,DDR_SDRAM_CFG_2_VAL |
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269 | #endif |
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270 | #ifdef DDR_SDRAM_MODE_VAL |
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271 | SET_IMM_REGW r31,r30,DDR_SDRAM_MODE_OFF,DDR_SDRAM_MODE_VAL |
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272 | #endif |
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273 | #ifdef DDR_SDRAM_MODE_2_VAL |
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274 | SET_IMM_REGW r31,r30,DDR_SDRAM_MODE_2_OFF,DDR_SDRAM_MODE_2_VAL |
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275 | #endif |
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276 | #ifdef DDR_SDRAM_MD_CNTL_VAL |
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277 | SET_IMM_REGW r31,r30,DDR_SDRAM_MD_CNTL_OFF,DDR_SDRAM_MD_CNTL_VAL |
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278 | #endif |
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279 | #ifdef DDR_SDRAM_MD_ITVL_VAL |
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280 | SET_IMM_REGW r31,r30,DDR_SDRAM_MD_ITVL_OFF,DDR_SDRAM_MD_ITVL_VAL |
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281 | #endif |
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282 | #ifdef DDR_SDRAM_CLK_CNTL_VAL |
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283 | SET_IMM_REGW r31,r30,DDR_SDRAM_CLK_CNTL_OFF,DDR_SDRAM_CLK_CNTL_VAL |
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284 | #endif |
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285 | #ifdef DDR_SDRAM_CFG_2_VAL |
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286 | SET_IMM_REGW r31,r30,DDR_SDRAM_CFG_2_OFF,DDR_SDRAM_CFG_2_VAL|DDR_SDRAM_CFG_2_D_INIT |
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287 | #endif |
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288 | |
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289 | #ifdef DDR_ERR_DISABLE_VAL |
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290 | /* |
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291 | * disable detect of RAM errors |
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292 | */ |
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293 | SET_IMM_REGW r31,r30,DDR_ERR_DISABLE_OFF,DDR_ERR_DISABLE_VAL |
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294 | #endif |
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295 | #ifdef DDR_SDRAM_DATA_INIT_VAL |
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296 | /* |
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297 | * set this value to initialize memory |
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298 | */ |
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299 | SET_IMM_REGW r31,r30,DDR_SDRAM_DATA_INIT_OFF,DDR_SDRAM_DATA_INIT_VAL |
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300 | #endif |
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301 | #ifdef DDR_SDRAM_INIT_ADDR_VAL |
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302 | SET_IMM_REGW r31,r30,DDR_SDRAM_INIT_ADDR_OFF,DDR_SDRAM_INIT_ADDR_VAL |
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303 | #endif |
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304 | #ifdef DDR_SDRAM_CFG_VAL |
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305 | /* |
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306 | * config DDR SDRAM |
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307 | */ |
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308 | SET_IMM_REGW r31,r30,DDR_SDRAM_CFG_OFF,DDR_SDRAM_CFG_VAL & ~DDR_SDRAM_CFG_MEM_EN |
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309 | /* |
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310 | * FIXME: wait 200us |
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311 | */ |
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312 | /* |
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313 | * enable DDR SDRAM |
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314 | */ |
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315 | SET_IMM_REGW r31,r30,DDR_SDRAM_CFG_OFF,DDR_SDRAM_CFG_VAL | DDR_SDRAM_CFG_MEM_EN |
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316 | /* |
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317 | * wait, until DDR_SDRAM_CFG_2_D_INIT is cleared |
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318 | */ |
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319 | 1: lwz r30,DDR_SDRAM_CFG_2_OFF(r31) |
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320 | andi. r30,r30,DDR_SDRAM_CFG_2_D_INIT |
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321 | bne 1b |
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322 | #endif |
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323 | #ifdef DDR_ERR_DISABLE_VAL2 |
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324 | /* |
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325 | * enable detect of some RAM errors |
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326 | */ |
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327 | SET_IMM_REGW r31,r30,DDR_ERR_DISABLE_OFF,DDR_ERR_DISABLE_VAL2 |
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328 | #endif |
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329 | #ifdef DDR_SDRAM_INTERVAL_VAL |
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330 | /* |
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331 | * set the refresh interval |
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332 | */ |
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333 | SET_IMM_REGW r31,r30,DDR_SDRAM_INTERVAL_OFF,DDR_SDRAM_INTERVAL_VAL |
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334 | #endif |
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335 | start_rom_skip: |
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336 | /* |
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337 | * determine current execution address offset |
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338 | */ |
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339 | bl start_rom_skip1 |
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340 | start_rom_skip1: |
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341 | mflr r20 |
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342 | LA r30,start_rom_skip1 |
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343 | sub. r20,r20,r30 |
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344 | /* |
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345 | * execution address offset == 0? |
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346 | * then do not relocate code and data |
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347 | */ |
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348 | beq start_code_in_ram |
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349 | /* |
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350 | * ROM or relocatable startup: copy startup code to SDRAM |
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351 | */ |
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352 | /* get start address of text section in RAM */ |
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353 | LA r29, bsp_section_text_start |
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354 | /* get start address of text section in ROM (add reloc offset) */ |
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355 | add r30, r20, r29 |
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356 | /* get size of startup code */ |
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357 | LA r28, end_reloc_startup |
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358 | LA r31, bsp_section_text_start |
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359 | sub 28,r28,r31 |
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360 | /* copy startup code from ROM to RAM location */ |
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361 | bl copy_image |
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362 | |
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363 | /* |
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364 | * ROM startup: jump to code copy in SDRAM |
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365 | */ |
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366 | /* get compile time address of label */ |
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367 | LA r29, copy_rest_of_text |
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368 | mtlr r29 |
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369 | blr /* now further execution RAM */ |
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370 | copy_rest_of_text: |
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371 | LWI r31,IMMRBAR |
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372 | #ifdef LCRR_VAL |
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373 | SET_IMM_REGW r31,r30,LCRR_OFF,LCRR_VAL |
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374 | #endif |
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375 | /* |
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376 | * ROM or relocatable startup: copy rest of code to SDRAM |
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377 | */ |
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378 | /* get start address of rest of code in RAM */ |
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379 | LA r29, end_reloc_startup |
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380 | /* get start address of text section in ROM (add reloc offset) */ |
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381 | add r30, r20, r29 |
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382 | /* get size of rest of code */ |
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383 | LA r28, bsp_section_text_start |
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384 | LA r31, bsp_section_text_size |
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385 | add r28,r28,r31 |
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386 | sub r28,r28,r29 |
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387 | bl copy_image /* copy text section from ROM to RAM location */ |
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388 | |
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389 | /* |
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390 | * ROM or relocatable startup: copy data to SDRAM |
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391 | */ |
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392 | /* get start address of data section in RAM */ |
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393 | LA r29, bsp_section_data_start |
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394 | /* get start address of data section in ROM (add reloc offset) */ |
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395 | add r30, r20, r29 |
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396 | /* get size of RAM image */ |
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397 | LA r28, bsp_section_data_size |
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398 | /* copy initialized data section from ROM to RAM location */ |
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399 | bl copy_image |
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400 | |
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401 | start_code_in_ram: |
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402 | |
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403 | /* |
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404 | * ROM/RAM startup: clear bss in SDRAM |
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405 | */ |
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406 | LA r3, bsp_section_bss_start /* get start address of bss section */ |
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407 | LWI r4, bsp_section_bss_size /* get size of bss section */ |
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408 | bl mpc83xx_zero_4 /* Clear the bss section */ |
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409 | |
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410 | #ifdef HAS_UBOOT |
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411 | mr r3, r14 |
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412 | bl bsp_uboot_copy_board_info |
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413 | #endif /* HAS_UBOOT */ |
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414 | /* |
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415 | * call boot_card |
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416 | */ |
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417 | |
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418 | /* Set stack pointer (common for RAM/ROM startup) */ |
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419 | LA r1, bsp_section_text_start |
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420 | addi r1, r1, -0x10 /* Set up stack pointer = beginning of text section - 0x10 */ |
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421 | |
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422 | /* Create NULL */ |
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423 | li r0, 0 |
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424 | |
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425 | /* Return address */ |
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426 | stw r0, 4(r1) |
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427 | |
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428 | /* Back chain */ |
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429 | stw r0, 0(r1) |
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430 | |
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431 | /* Read-only small data */ |
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432 | LA r2, _SDA2_BASE_ |
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433 | |
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434 | /* Read-write small data */ |
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435 | LA r13, _SDA_BASE_ |
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436 | |
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437 | /* clear arguments and do further init. in C (common for RAM/ROM startup) */ |
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438 | |
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439 | /* Clear cmdline */ |
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440 | xor r3, r3, r3 |
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441 | |
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442 | bl SYM (boot_card) /* Call the first C routine */ |
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443 | |
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444 | twiddle: |
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445 | /* We don't expect to return from boot_card but if we do */ |
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446 | /* wait here for watchdog to kick us into hard reset */ |
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447 | b twiddle |
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448 | |
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449 | copy_image: |
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450 | mr r27, r28 |
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451 | srwi r28, r28, 2 |
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452 | mtctr r28 |
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453 | |
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454 | slwi r28, r28, 2 |
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455 | sub r27, r27, r28 /* maybe some residual bytes */ |
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456 | copy_image_word: |
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457 | lswi r28, r30, 0x04 |
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458 | |
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459 | stswi r28, r29, 0x04 /* do word copy ROM -> RAM */ |
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460 | |
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461 | |
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462 | addi r30, r30, 0x04 /* increment source pointer */ |
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463 | addi r29, r29, 0x04 /* increment destination pointer */ |
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464 | |
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465 | bdnz copy_image_word /* decrement ctr and branch if not 0 */ |
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466 | |
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467 | cmpwi r27, 0x00 /* copy image finished ? */ |
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468 | beq copy_image_end; |
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469 | mtctr r27 /* reload counter for residual bytes */ |
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470 | copy_image_byte: |
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471 | lswi r28, r30, 0x01 |
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472 | |
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473 | stswi r28, r29, 0x01 /* do byte copy ROM -> RAM */ |
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474 | |
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475 | |
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476 | addi r30, r30, 0x01 /* increment source pointer */ |
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477 | addi r29, r29, 0x01 /* increment destination pointer */ |
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478 | |
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479 | bdnz copy_image_byte /* decrement ctr and branch if not 0 */ |
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480 | |
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481 | copy_image_end: |
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482 | blr |
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483 | |
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484 | |
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485 | /** |
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486 | * @fn int mpc83xx_zero_4( void *dest, size_t n) |
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487 | * |
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488 | * @brief Zero all @a n bytes starting at @a dest with 4 byte writes. |
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489 | * |
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490 | * The address @a dest has to be aligned on 4 byte boundaries. The size @a n |
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491 | * must be evenly divisible by 4. |
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492 | */ |
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493 | GLOBAL_FUNCTION mpc83xx_zero_4 |
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494 | /* Create zero */ |
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495 | xor r0, r0, r0 |
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496 | |
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497 | /* Set offset */ |
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498 | xor r5, r5, r5 |
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499 | |
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500 | /* Loop counter for the first bytes up to 16 bytes */ |
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501 | rlwinm. r9, r4, 30, 30, 31 |
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502 | beq mpc83xx_zero_4_more |
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503 | mtctr r9 |
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504 | |
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505 | mpc83xx_zero_4_head: |
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506 | |
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507 | stwx r0, r3, r5 |
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508 | addi r5, r5, 4 |
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509 | bdnz mpc83xx_zero_4_head |
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510 | |
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511 | mpc83xx_zero_4_more: |
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512 | |
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513 | /* More than 16 bytes? */ |
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514 | srwi. r9, r4, 4 |
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515 | beqlr |
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516 | mtctr r9 |
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517 | |
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518 | /* Set offsets */ |
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519 | addi r6, r5, 4 |
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520 | addi r7, r5, 8 |
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521 | addi r8, r5, 12 |
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522 | |
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523 | mpc83xx_zero_4_tail: |
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524 | |
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525 | stwx r0, r3, r5 |
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526 | addi r5, r5, 16 |
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527 | stwx r0, r3, r6 |
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528 | addi r6, r6, 16 |
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529 | stwx r0, r3, r7 |
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530 | addi r7, r7, 16 |
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531 | stwx r0, r3, r8 |
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532 | addi r8, r8, 16 |
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533 | bdnz mpc83xx_zero_4_tail |
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534 | |
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535 | /* Return */ |
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536 | blr |
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537 | |
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538 | end_reloc_startup: |
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