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4.115

Last change on this file since 9b4422a2 was 9b4422a2, checked in by Joel Sherrill <joel.sherrill@…>, on 05/03/12 at 15:09:24

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Line
1	/===============================================================\
2	\| Project: RTEMS generic MPC83xx BSP \|
3	+-----------------------------------------------------------------+
4	\| Copyright (c) 2007 \|
5	\| Embedded Brains GmbH \|
6	\| Obere Lagerstr. 30 \|
7	\| D-82178 Puchheim \|
8	\| Germany \|
9	\| rtems@embedded-brains.de \|
10	+-----------------------------------------------------------------+
11	\| The license and distribution terms for this file may be \|
12	\| found in the file LICENSE in this distribution or at \|
13	\| \|
14	\| http://www.rtems.com/license/LICENSE. \|
15	\| \|
16	+-----------------------------------------------------------------+
17	\| this file contains the startup assembly code \|
18	\===============================================================/
19
20
21	#include <libcpu/powerpc-utility.h>
22	#include <rtems/powerpc/cache.h>
23	#include <bsp.h>
24	#include <mpc83xx/mpc83xx.h>
25
26	.macro SET_IMM_REGW base, reg2, offset, value
27	LA \reg2, \value
28	stw \reg2,\offset(\base)
29	.endm
30
31	#define REP8(l) l ; l; l; l; l; l; l; l;
32
33	.extern boot_card
34	.extern MBAR
35
36	#if defined(RESET_CONF_WRD_L)
37	.section ".resconf","ax"
38	PUBLIC_VAR (reset_conf_words)
39	reset_conf_words:
40	REP8( .byte ((RESET_CONF_WRD_L >> 24) & 0xff))
41	REP8( .byte ((RESET_CONF_WRD_L >> 16) & 0xff))
42	REP8( .byte ((RESET_CONF_WRD_L >> 8) & 0xff))
43	REP8( .byte ((RESET_CONF_WRD_L >> 0) & 0xff))
44
45	REP8( .byte ((RESET_CONF_WRD_H >> 24) & 0xff))
46	REP8( .byte ((RESET_CONF_WRD_H >> 16) & 0xff))
47	REP8( .byte ((RESET_CONF_WRD_H >> 8) & 0xff))
48	REP8( .byte ((RESET_CONF_WRD_H >> 0) & 0xff))
49	#endif
50
51	.section ".vectors","ax"
52	PUBLIC_VAR (reset_vec)
53	reset_vec:
54	bl rom_entry
55
56	.section ".entry"
57	PUBLIC_VAR (start)
58	start:
59
60	/* Reset time base */
61	li r0, 0
62	mtspr TBWU, r0
63	mtspr TBWL, r0
64
65	#ifdef HAS_UBOOT
66	mr r14, r3
67	#endif /* HAS_UBOOT */
68
69	/*
70	* basic CPU setup:
71	* init MSR
72	*/
73	mfmsr r30
74	SETBITS r30, r29, MSR_ME\|MSR_RI
75	CLRBITS r30, r29, MSR_IP\|MSR_EE
76	mtmsr r30 /* Set RI/ME, Clr EE in MSR */
77
78	b start_rom_skip
79
80	PUBLIC_VAR (rom_entry)
81	rom_entry:
82	/*
83	* basic CPU setup:
84	* init MSR
85	*/
86	mfmsr r30
87	SETBITS r30, r29, MSR_ME\|MSR_RI
88	CLRBITS r30, r29, MSR_IP\|MSR_EE
89	mtmsr r30 /* Set RI/ME, Clr EE in MSR */
90
91	/*
92	* ROM startup: remap IMMR to 0xE0000000
93	* use special sequence from MPC8349EA RM Rev 1, 5.2.4.1.1 "Updating IMMRBAR"
94	*/
95	LWI r30,IMMRBAR_DEFAULT
96	LWI r31,IMMRBAR
97	lwz r29,0(r30)
98	stw r31,0(r30)
99	#if 0
100	lwz r29,0(r28) /* read from ROM... */
101	#endif
102	isync
103	lwz r29,0(r31) /* read from IMMRBAR... */
104	isync
105	/*
106	* NOTE: now r31 points to onchip registers
107	*/
108	/*
109	* we start from 0x100, so ROM is currently mapped to
110	* 0x00000000..
111	* in the next step, ROM will be remapped to its final location
112	* at 0xfe000000... (using LBLAWBAR1 with LBLAWBAR0 value)
113	* and we jump to that location.
114	* then we remove the ROM mapping to zero
115	*/
116	#ifdef LBLAWBAR0_VAL
117	SET_IMM_REGW r31,r30,LBLAWBAR1_OFF,LBLAWBAR0_VAL
118	#endif
119	#ifdef LBLAWAR0_VAL
120	SET_IMM_REGW r31,r30,LBLAWAR1_OFF,LBLAWAR0_VAL
121	#endif
122
123
124	/*
125	* ROM startup: jump to code final ROM location
126	*/
127	LA r20, bsp_rom_start /* ROM-RAM reloc in r20 */
128	LA r29, start_code_in_rom /* get compile time addr of label */
129	add r29,r20,r29 /* compute exec address */
130	mtlr r29
131	blr /* now further execution in upper ROM */
132
133	start_code_in_rom:
134
135	#ifdef LBLAWBAR0_VAL
136	SET_IMM_REGW r31,r30,LBLAWBAR0_OFF,LBLAWBAR0_VAL
137	#endif
138	#ifdef LBLAWAR0_VAL
139	SET_IMM_REGW r31,r30,LBLAWAR0_OFF,LBLAWAR0_VAL
140	#endif
141	#ifdef LBLAWBAR1_VAL
142	SET_IMM_REGW r31,r30,LBLAWBAR1_OFF,LBLAWBAR1_VAL
143	#endif
144	#ifdef LBLAWAR1_VAL
145	SET_IMM_REGW r31,r30,LBLAWAR1_OFF,LBLAWAR1_VAL
146	#endif
147	#ifdef LBLAWBAR2_VAL
148	SET_IMM_REGW r31,r30,LBLAWBAR2_OFF,LBLAWBAR2_VAL
149	#endif
150	#ifdef LBLAWAR2_VAL
151	SET_IMM_REGW r31,r30,LBLAWAR2_OFF,LBLAWAR2_VAL
152	#endif
153	#ifdef LBLAWBAR3_VAL
154	SET_IMM_REGW r31,r30,LBLAWBAR3_OFF,LBLAWBAR3_VAL
155	#endif
156	#ifdef LBLAWAR3_VAL
157	SET_IMM_REGW r31,r30,LBLAWAR3_OFF,LBLAWAR3_VAL
158	#endif
159	/*
160	* ROM startup: init bus system
161	*/
162	#ifdef BR0_VAL
163	SET_IMM_REGW r31,r30,BR0_OFF,BR0_VAL
164	#endif
165	#ifdef OR0_VAL
166	SET_IMM_REGW r31,r30,OR0_OFF,OR0_VAL
167	#endif
168	#ifdef BR1_VAL
169	SET_IMM_REGW r31,r30,BR1_OFF,BR1_VAL
170	#endif
171	#ifdef OR1_VAL
172	SET_IMM_REGW r31,r30,OR1_OFF,OR1_VAL
173	#endif
174	#ifdef BR2_VAL
175	SET_IMM_REGW r31,r30,BR2_OFF,BR2_VAL
176	#endif
177	#ifdef OR2_VAL
178	SET_IMM_REGW r31,r30,OR2_OFF,OR2_VAL
179	#endif
180	#ifdef BR3_VAL
181	SET_IMM_REGW r31,r30,BR3_OFF,BR3_VAL
182	#endif
183	#ifdef OR3_VAL
184	SET_IMM_REGW r31,r30,OR3_OFF,OR3_VAL
185	#endif
186	#ifdef BR4_VAL
187	SET_IMM_REGW r31,r30,BR4_OFF,BR4_VAL
188	#endif
189	#ifdef OR4_VAL
190	SET_IMM_REGW r31,r30,OR4_OFF,OR4_VAL
191	#endif
192	#ifdef BR5_VAL
193	SET_IMM_REGW r31,r30,BR5_OFF,BR5_VAL
194	#endif
195	#ifdef OR5_VAL
196	SET_IMM_REGW r31,r30,OR5_OFF,OR5_VAL
197	#endif
198	/*
199	* ROM startup: init SDRAM access window
200	*/
201	#ifdef DDRLAWBAR0_VAL
202	SET_IMM_REGW r31,r30,DDRLAWBAR0_OFF,DDRLAWBAR0_VAL
203	#endif
204	#ifdef DDRLAWAR0_VAL
205	SET_IMM_REGW r31,r30,DDRLAWAR0_OFF,DDRLAWAR0_VAL
206	#endif
207	#ifdef DDRLAWBAR1_VAL
208	SET_IMM_REGW r31,r30,DDRLAWBAR1_OFF,DDRLAWBAR1_VAL
209	#endif
210	#ifdef DDRLAWAR1_VAL
211	SET_IMM_REGW r31,r30,DDRLAWAR1_OFF,DDRLAWAR1_VAL
212	#endif
213	/*
214	* ROM startup: init refresh interval
215	*/
216	#ifdef MRPTR_VAL
217	SET_IMM_REGW r31,r30,MRPTR_OFF,MRPTR_VAL
218	#endif
219	/*
220	* ROM startup: init SDRAM
221	*/
222	#ifdef LSRT_VAL
223	SET_IMM_REGW r31,r30, LSRT_OFF, LSRT_VAL
224	#endif
225	#ifdef LSDMR_VAL
226	SET_IMM_REGW r31,r30, LSDMR_OFF, LSDMR_VAL
227	#endif
228	#ifdef CS0_BNDS_VAL
229	SET_IMM_REGW r31,r30,CS0_BNDS_OFF,CS0_BNDS_VAL
230	#endif
231	#ifdef CS1_BNDS_VAL
232	SET_IMM_REGW r31,r30,CS1_BNDS_OFF,CS1_BNDS_VAL
233	#endif
234	#ifdef CS2_BNDS_VAL
235	SET_IMM_REGW r31,r30,CS2_BNDS_OFF,CS2_BNDS_VAL
236	#endif
237	#ifdef CS3_BNDS_VAL
238	SET_IMM_REGW r31,r30,CS3_BNDS_OFF,CS3_BNDS_VAL
239	#endif
240	#ifdef CS0_CONFIG_VAL
241	SET_IMM_REGW r31,r30,CS0_CONFIG_OFF,CS0_CONFIG_VAL
242	#endif
243	#ifdef CS1_CONFIG_VAL
244	SET_IMM_REGW r31,r30,CS1_CONFIG_OFF,CS1_CONFIG_VAL
245	#endif
246	#ifdef CS2_CONFIG_VAL
247	SET_IMM_REGW r31,r30,CS2_CONFIG_OFF,CS2_CONFIG_VAL
248	#endif
249	#ifdef CS3_CONFIG_VAL
250	SET_IMM_REGW r31,r30,CS3_CONFIG_OFF,CS3_CONFIG_VAL
251	#endif
252	#ifdef TIMING_CFG_3_VAL
253	SET_IMM_REGW r31,r30,TIMING_CFG_3_OFF,TIMING_CFG_3_VAL
254	#endif
255	#ifdef TIMING_CFG_0_VAL
256	SET_IMM_REGW r31,r30,TIMING_CFG_0_OFF,TIMING_CFG_0_VAL
257	#endif
258	#ifdef TIMING_CFG_1_VAL
259	SET_IMM_REGW r31,r30,TIMING_CFG_1_OFF,TIMING_CFG_1_VAL
260	#endif
261	#ifdef TIMING_CFG_2_VAL
262	SET_IMM_REGW r31,r30,TIMING_CFG_2_OFF,TIMING_CFG_2_VAL
263	#endif
264	#ifdef DDRCDR_VAL
265	SET_IMM_REGW r31,r30,DDRCDR_OFF,DDRCDR_VAL
266	#endif
267	#ifdef DDR_SDRAM_CFG_2_VAL
268	SET_IMM_REGW r31,r30,DDR_SDRAM_CFG_2_OFF,DDR_SDRAM_CFG_2_VAL
269	#endif
270	#ifdef DDR_SDRAM_MODE_VAL
271	SET_IMM_REGW r31,r30,DDR_SDRAM_MODE_OFF,DDR_SDRAM_MODE_VAL
272	#endif
273	#ifdef DDR_SDRAM_MODE_2_VAL
274	SET_IMM_REGW r31,r30,DDR_SDRAM_MODE_2_OFF,DDR_SDRAM_MODE_2_VAL
275	#endif
276	#ifdef DDR_SDRAM_MD_CNTL_VAL
277	SET_IMM_REGW r31,r30,DDR_SDRAM_MD_CNTL_OFF,DDR_SDRAM_MD_CNTL_VAL
278	#endif
279	#ifdef DDR_SDRAM_MD_ITVL_VAL
280	SET_IMM_REGW r31,r30,DDR_SDRAM_MD_ITVL_OFF,DDR_SDRAM_MD_ITVL_VAL
281	#endif
282	#ifdef DDR_SDRAM_CLK_CNTL_VAL
283	SET_IMM_REGW r31,r30,DDR_SDRAM_CLK_CNTL_OFF,DDR_SDRAM_CLK_CNTL_VAL
284	#endif
285	#ifdef DDR_SDRAM_CFG_2_VAL
286	SET_IMM_REGW r31,r30,DDR_SDRAM_CFG_2_OFF,DDR_SDRAM_CFG_2_VAL\|DDR_SDRAM_CFG_2_D_INIT
287	#endif
288
289	#ifdef DDR_ERR_DISABLE_VAL
290	/*
291	* disable detect of RAM errors
292	*/
293	SET_IMM_REGW r31,r30,DDR_ERR_DISABLE_OFF,DDR_ERR_DISABLE_VAL
294	#endif
295	#ifdef DDR_SDRAM_DATA_INIT_VAL
296	/*
297	* set this value to initialize memory
298	*/
299	SET_IMM_REGW r31,r30,DDR_SDRAM_DATA_INIT_OFF,DDR_SDRAM_DATA_INIT_VAL
300	#endif
301	#ifdef DDR_SDRAM_INIT_ADDR_VAL
302	SET_IMM_REGW r31,r30,DDR_SDRAM_INIT_ADDR_OFF,DDR_SDRAM_INIT_ADDR_VAL
303	#endif
304	#ifdef DDR_SDRAM_CFG_VAL
305	/*
306	* config DDR SDRAM
307	*/
308	SET_IMM_REGW r31,r30,DDR_SDRAM_CFG_OFF,DDR_SDRAM_CFG_VAL & ~DDR_SDRAM_CFG_MEM_EN
309	/*
310	* FIXME: wait 200us
311	*/
312	/*
313	* enable DDR SDRAM
314	*/
315	SET_IMM_REGW r31,r30,DDR_SDRAM_CFG_OFF,DDR_SDRAM_CFG_VAL \| DDR_SDRAM_CFG_MEM_EN
316	/*
317	* wait, until DDR_SDRAM_CFG_2_D_INIT is cleared
318	*/
319	1: lwz r30,DDR_SDRAM_CFG_2_OFF(r31)
320	andi. r30,r30,DDR_SDRAM_CFG_2_D_INIT
321	bne 1b
322	#endif
323	#ifdef DDR_ERR_DISABLE_VAL2
324	/*
325	* enable detect of some RAM errors
326	*/
327	SET_IMM_REGW r31,r30,DDR_ERR_DISABLE_OFF,DDR_ERR_DISABLE_VAL2
328	#endif
329	#ifdef DDR_SDRAM_INTERVAL_VAL
330	/*
331	* set the refresh interval
332	*/
333	SET_IMM_REGW r31,r30,DDR_SDRAM_INTERVAL_OFF,DDR_SDRAM_INTERVAL_VAL
334	#endif
335	start_rom_skip:
336	/*
337	* determine current execution address offset
338	*/
339	bl start_rom_skip1
340	start_rom_skip1:
341	mflr r20
342	LA r30,start_rom_skip1
343	sub. r20,r20,r30
344	/*
345	* execution address offset == 0?
346	* then do not relocate code and data
347	*/
348	beq start_code_in_ram
349	/*
350	* ROM or relocatable startup: copy startup code to SDRAM
351	*/
352	/* get start address of text section in RAM */
353	LA r29, bsp_section_text_start
354	/* get start address of text section in ROM (add reloc offset) */
355	add r30, r20, r29
356	/* get size of startup code */
357	LA r28, end_reloc_startup
358	LA r31, bsp_section_text_start
359	sub 28,r28,r31
360	/* copy startup code from ROM to RAM location */
361	bl copy_image
362
363	/*
364	* ROM startup: jump to code copy in SDRAM
365	*/
366	/* get compile time address of label */
367	LA r29, copy_rest_of_text
368	mtlr r29
369	blr /* now further execution RAM */
370	copy_rest_of_text:
371	#ifdef LCRR_VAL
372	SET_IMM_REGW r31,r30,LCRR_OFF,LCRR_VAL
373	#endif
374	/*
375	* ROM or relocatable startup: copy rest of code to SDRAM
376	*/
377	/* get start address of rest of code in RAM */
378	LA r29, end_reloc_startup
379	/* get start address of text section in ROM (add reloc offset) */
380	add r30, r20, r29
381	/* get size of rest of code */
382	LA r28, bsp_section_text_start
383	LA r31, bsp_section_text_size
384	add r28,r28,r31
385	sub r28,r28,r29
386	bl copy_image /* copy text section from ROM to RAM location */
387
388	/*
389	* ROM or relocatable startup: copy data to SDRAM
390	*/
391	/* get start address of data section in RAM */
392	LA r29, bsp_section_data_start
393	/* get start address of data section in ROM (add reloc offset) */
394	add r30, r20, r29
395	/* get size of RAM image */
396	LA r28, bsp_section_data_size
397	/* copy initialized data section from ROM to RAM location */
398	bl copy_image
399
400	start_code_in_ram:
401
402	/*
403	* ROM/RAM startup: clear bss in SDRAM
404	*/
405	LA r3, bsp_section_bss_start /* get start address of bss section */
406	LWI r4, bsp_section_bss_size /* get size of bss section */
407	bl mpc83xx_zero_4 /* Clear the bss section */
408
409	#ifdef HAS_UBOOT
410	mr r3, r14
411	bl bsp_uboot_copy_board_info
412	#endif /* HAS_UBOOT */
413	/*
414	* call boot_card
415	*/
416
417	/* Set stack pointer (common for RAM/ROM startup) */
418	LA r1, bsp_section_text_start
419	addi r1, r1, -0x10 /* Set up stack pointer = beginning of text section - 0x10 */
420
421	/* Create NULL */
422	li r0, 0
423
424	/* Return address */
425	stw r0, 4(r1)
426
427	/* Back chain */
428	stw r0, 0(r1)
429
430	/* Read-only small data */
431	LA r2, _SDA2_BASE_
432
433	/* Read-write small data */
434	LA r13, _SDA_BASE_
435
436	/* clear arguments and do further init. in C (common for RAM/ROM startup) */
437
438	/* Clear cmdline */
439	xor r3, r3, r3
440
441	bl SYM (boot_card) /* Call the first C routine */
442
443	twiddle:
444	/* We don't expect to return from boot_card but if we do */
445	/* wait here for watchdog to kick us into hard reset */
446	b twiddle
447
448	copy_image:
449	mr r27, r28
450	srwi r28, r28, 2
451	mtctr r28
452
453	slwi r28, r28, 2
454	sub r27, r27, r28 /* maybe some residual bytes */
455	copy_image_word:
456	lswi r28, r30, 0x04
457
458	stswi r28, r29, 0x04 /* do word copy ROM -> RAM */
459
460
461	addi r30, r30, 0x04 /* increment source pointer */
462	addi r29, r29, 0x04 /* increment destination pointer */
463
464	bdnz copy_image_word /* decrement ctr and branch if not 0 */
465
466	cmpwi r27, 0x00 /* copy image finished ? */
467	beq copy_image_end;
468	mtctr r27 /* reload counter for residual bytes */
469	copy_image_byte:
470	lswi r28, r30, 0x01
471
472	stswi r28, r29, 0x01 /* do byte copy ROM -> RAM */
473
474
475	addi r30, r30, 0x01 /* increment source pointer */
476	addi r29, r29, 0x01 /* increment destination pointer */
477
478	bdnz copy_image_byte /* decrement ctr and branch if not 0 */
479
480	copy_image_end:
481	blr
482
483
484	/**
485	* @fn int mpc83xx_zero_4( void *dest, size_t n)
486	*
487	* @brief Zero all @a n bytes starting at @a dest with 4 byte writes.
488	*
489	* The address @a dest has to be aligned on 4 byte boundaries. The size @a n
490	* must be evenly divisible by 4.
491	*/
492	GLOBAL_FUNCTION mpc83xx_zero_4
493	/* Create zero */
494	xor r0, r0, r0
495
496	/* Set offset */
497	xor r5, r5, r5
498
499	/* Loop counter for the first bytes up to 16 bytes */
500	rlwinm. r9, r4, 30, 30, 31
501	beq mpc83xx_zero_4_more
502	mtctr r9
503
504	mpc83xx_zero_4_head:
505
506	stwx r0, r3, r5
507	addi r5, r5, 4
508	bdnz mpc83xx_zero_4_head
509
510	mpc83xx_zero_4_more:
511
512	/* More than 16 bytes? */
513	srwi. r9, r4, 4
514	beqlr
515	mtctr r9
516
517	/* Set offsets */
518	addi r6, r5, 4
519	addi r7, r5, 8
520	addi r8, r5, 12
521
522	mpc83xx_zero_4_tail:
523
524	stwx r0, r3, r5
525	addi r5, r5, 16
526	stwx r0, r3, r6
527	addi r6, r6, 16
528	stwx r0, r3, r7
529	addi r7, r7, 16
530	stwx r0, r3, r8
531	addi r8, r8, 16
532	bdnz mpc83xx_zero_4_tail
533
534	/* Return */
535	blr
536
537	end_reloc_startup:

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