| 1 | /*===============================================================*\ |
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| 2 | | Project: RTEMS generic MPC83xx BSP | |
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| 3 | +-----------------------------------------------------------------+ |
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| 4 | | Copyright (c) 2007 | |
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| 5 | | Embedded Brains GmbH | |
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| 6 | | Obere Lagerstr. 30 | |
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| 7 | | D-82178 Puchheim | |
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| 8 | | Germany | |
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| 9 | | rtems@embedded-brains.de | |
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| 10 | +-----------------------------------------------------------------+ |
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| 11 | | The license and distribution terms for this file may be | |
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| 12 | | found in the file LICENSE in this distribution or at | |
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| 13 | | | |
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| 14 | | http://www.rtems.com/license/LICENSE. | |
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| 15 | | | |
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| 16 | +-----------------------------------------------------------------+ |
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| 17 | | this file contains the startup assembly code | |
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| 18 | \*===============================================================*/ |
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| 19 | /* $Id$ */ |
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| 20 | |
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| 21 | #include <libcpu/powerpc-utility.h> |
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| 22 | #include <rtems/powerpc/cache.h> |
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| 23 | #include <bsp.h> |
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| 24 | #include <mpc83xx/mpc83xx.h> |
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| 25 | |
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| 26 | .macro SET_IMM_REGW base, reg2, offset, value |
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| 27 | LA \reg2, \value |
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| 28 | stw \reg2,\offset(\base) |
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| 29 | .endm |
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| 30 | |
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| 31 | #define REP8(l) l ; l; l; l; l; l; l; l; |
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| 32 | |
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| 33 | .extern boot_card |
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| 34 | .extern MBAR |
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| 35 | |
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| 36 | #if defined(RESET_CONF_WRD_L) |
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| 37 | .section ".resconf","ax" |
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| 38 | PUBLIC_VAR (reset_conf_words) |
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| 39 | reset_conf_words: |
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| 40 | REP8( .byte ((RESET_CONF_WRD_L >> 24) & 0xff)) |
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| 41 | REP8( .byte ((RESET_CONF_WRD_L >> 16) & 0xff)) |
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| 42 | REP8( .byte ((RESET_CONF_WRD_L >> 8) & 0xff)) |
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| 43 | REP8( .byte ((RESET_CONF_WRD_L >> 0) & 0xff)) |
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| 44 | |
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| 45 | REP8( .byte ((RESET_CONF_WRD_H >> 24) & 0xff)) |
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| 46 | REP8( .byte ((RESET_CONF_WRD_H >> 16) & 0xff)) |
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| 47 | REP8( .byte ((RESET_CONF_WRD_H >> 8) & 0xff)) |
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| 48 | REP8( .byte ((RESET_CONF_WRD_H >> 0) & 0xff)) |
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| 49 | #endif |
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| 50 | |
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| 51 | .section ".vectors","ax" |
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| 52 | PUBLIC_VAR (reset_vec) |
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| 53 | reset_vec: |
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| 54 | bl rom_entry |
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| 55 | |
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| 56 | .section ".entry" |
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| 57 | PUBLIC_VAR (start) |
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| 58 | start: |
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| 59 | |
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| 60 | #ifdef HAS_UBOOT |
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| 61 | |
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| 62 | .extern mpc83xx_uboot_board_info |
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| 63 | .extern mpc83xx_uboot_board_info_size |
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| 64 | |
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| 65 | /* Reset time base */ |
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| 66 | li r0, 0 |
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| 67 | mtspr TBWU, r0 |
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| 68 | mtspr TBWL, r0 |
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| 69 | |
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| 70 | /* Copy board info */ |
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| 71 | LA r6, mpc83xx_uboot_board_info |
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| 72 | LW r5, mpc83xx_uboot_board_info_size |
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| 73 | mtctr r5 |
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| 74 | |
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| 75 | copy_uboot_board_info: |
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| 76 | |
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| 77 | lwz r5, 0(r3) |
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| 78 | addi r3, r3, 4 |
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| 79 | stw r5, 0(r6) |
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| 80 | addi r6, r6, 4 |
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| 81 | bdnz copy_uboot_board_info |
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| 82 | |
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| 83 | #endif /* HAS_UBOOT */ |
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| 84 | |
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| 85 | /* |
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| 86 | * basic CPU setup: |
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| 87 | * init MSR |
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| 88 | */ |
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| 89 | mfmsr r30 |
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| 90 | SETBITS r30, r29, MSR_ME|MSR_RI |
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| 91 | CLRBITS r30, r29, MSR_IP|MSR_EE |
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| 92 | mtmsr r30 /* Set RI/ME, Clr EE in MSR */ |
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| 93 | |
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| 94 | b start_rom_skip |
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| 95 | |
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| 96 | PUBLIC_VAR (rom_entry) |
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| 97 | rom_entry: |
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| 98 | /* |
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| 99 | * basic CPU setup: |
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| 100 | * init MSR |
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| 101 | */ |
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| 102 | mfmsr r30 |
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| 103 | SETBITS r30, r29, MSR_ME|MSR_RI |
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| 104 | CLRBITS r30, r29, MSR_IP|MSR_EE |
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| 105 | mtmsr r30 /* Set RI/ME, Clr EE in MSR */ |
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| 106 | |
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| 107 | /* |
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| 108 | * ROM startup: remap IMMR to 0xE0000000 |
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| 109 | * use special sequence from MPC8349EA RM Rev 1, 5.2.4.1.1 "Updating IMMRBAR" |
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| 110 | */ |
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| 111 | LWI r30,IMMRBAR_DEFAULT |
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| 112 | LWI r31,IMMRBAR |
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| 113 | lwz r29,0(r30) |
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| 114 | stw r31,0(r30) |
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| 115 | #if 0 |
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| 116 | lwz r29,0(r28) /* read from ROM... */ |
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| 117 | #endif |
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| 118 | isync |
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| 119 | lwz r29,0(r31) /* read from IMMRBAR... */ |
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| 120 | isync |
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| 121 | /* |
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| 122 | * NOTE: now r31 points to onchip registers |
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| 123 | */ |
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| 124 | /* |
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| 125 | * we start from 0x100, so ROM is currently mapped to |
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| 126 | * 0x00000000.. |
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| 127 | * in the next step, ROM will be remapped to its final location |
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| 128 | * at 0xfe000000... (using LBLAWBAR1 with LBLAWBAR0 value) |
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| 129 | * and we jump to that location. |
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| 130 | * then we remove the ROM mapping to zero |
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| 131 | */ |
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| 132 | #ifdef LBLAWBAR0_VAL |
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| 133 | SET_IMM_REGW r31,r30,LBLAWBAR1_OFF,LBLAWBAR0_VAL |
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| 134 | #endif |
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| 135 | #ifdef LBLAWAR0_VAL |
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| 136 | SET_IMM_REGW r31,r30,LBLAWAR1_OFF,LBLAWAR0_VAL |
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| 137 | #endif |
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| 138 | |
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| 139 | |
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| 140 | /* |
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| 141 | * ROM startup: jump to code final ROM location |
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| 142 | */ |
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| 143 | LA r20, bsp_rom_start /* ROM-RAM reloc in r20 */ |
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| 144 | LA r29, start_code_in_rom /* get compile time addr of label */ |
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| 145 | add r29,r20,r29 /* compute exec address */ |
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| 146 | mtlr r29 |
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| 147 | blr /* now further execution in upper ROM */ |
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| 148 | |
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| 149 | start_code_in_rom: |
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| 150 | |
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| 151 | #ifdef LBLAWBAR0_VAL |
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| 152 | SET_IMM_REGW r31,r30,LBLAWBAR0_OFF,LBLAWBAR0_VAL |
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| 153 | #endif |
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| 154 | #ifdef LBLAWAR0_VAL |
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| 155 | SET_IMM_REGW r31,r30,LBLAWAR0_OFF,LBLAWAR0_VAL |
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| 156 | #endif |
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| 157 | #ifdef LBLAWBAR1_VAL |
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| 158 | SET_IMM_REGW r31,r30,LBLAWBAR1_OFF,LBLAWBAR1_VAL |
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| 159 | #endif |
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| 160 | #ifdef LBLAWAR1_VAL |
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| 161 | SET_IMM_REGW r31,r30,LBLAWAR1_OFF,LBLAWAR1_VAL |
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| 162 | #endif |
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| 163 | #ifdef LBLAWBAR2_VAL |
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| 164 | SET_IMM_REGW r31,r30,LBLAWBAR2_OFF,LBLAWBAR2_VAL |
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| 165 | #endif |
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| 166 | #ifdef LBLAWAR2_VAL |
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| 167 | SET_IMM_REGW r31,r30,LBLAWAR2_OFF,LBLAWAR2_VAL |
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| 168 | #endif |
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| 169 | #ifdef LBLAWBAR3_VAL |
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| 170 | SET_IMM_REGW r31,r30,LBLAWBAR3_OFF,LBLAWBAR3_VAL |
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| 171 | #endif |
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| 172 | #ifdef LBLAWAR3_VAL |
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| 173 | SET_IMM_REGW r31,r30,LBLAWAR3_OFF,LBLAWAR3_VAL |
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| 174 | #endif |
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| 175 | /* |
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| 176 | * ROM startup: init bus system |
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| 177 | */ |
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| 178 | #ifdef BR0_VAL |
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| 179 | SET_IMM_REGW r31,r30,BR0_OFF,BR0_VAL |
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| 180 | #endif |
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| 181 | #ifdef OR0_VAL |
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| 182 | SET_IMM_REGW r31,r30,OR0_OFF,OR0_VAL |
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| 183 | #endif |
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| 184 | #ifdef BR1_VAL |
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| 185 | SET_IMM_REGW r31,r30,BR1_OFF,BR1_VAL |
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| 186 | #endif |
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| 187 | #ifdef OR1_VAL |
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| 188 | SET_IMM_REGW r31,r30,OR1_OFF,OR1_VAL |
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| 189 | #endif |
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| 190 | #ifdef BR2_VAL |
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| 191 | SET_IMM_REGW r31,r30,BR2_OFF,BR2_VAL |
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| 192 | #endif |
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| 193 | #ifdef OR2_VAL |
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| 194 | SET_IMM_REGW r31,r30,OR2_OFF,OR2_VAL |
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| 195 | #endif |
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| 196 | #ifdef BR3_VAL |
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| 197 | SET_IMM_REGW r31,r30,BR3_OFF,BR3_VAL |
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| 198 | #endif |
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| 199 | #ifdef OR3_VAL |
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| 200 | SET_IMM_REGW r31,r30,OR3_OFF,OR3_VAL |
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| 201 | #endif |
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| 202 | #ifdef BR4_VAL |
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| 203 | SET_IMM_REGW r31,r30,BR4_OFF,BR4_VAL |
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| 204 | #endif |
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| 205 | #ifdef OR4_VAL |
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| 206 | SET_IMM_REGW r31,r30,OR4_OFF,OR4_VAL |
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| 207 | #endif |
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| 208 | #ifdef BR5_VAL |
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| 209 | SET_IMM_REGW r31,r30,BR5_OFF,BR5_VAL |
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| 210 | #endif |
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| 211 | #ifdef OR5_VAL |
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| 212 | SET_IMM_REGW r31,r30,OR5_OFF,OR5_VAL |
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| 213 | #endif |
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| 214 | /* |
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| 215 | * ROM startup: init SDRAM access window |
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| 216 | */ |
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| 217 | #ifdef DDRLAWBAR0_VAL |
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| 218 | SET_IMM_REGW r31,r30,DDRLAWBAR0_OFF,DDRLAWBAR0_VAL |
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| 219 | #endif |
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| 220 | #ifdef DDRLAWAR0_VAL |
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| 221 | SET_IMM_REGW r31,r30,DDRLAWAR0_OFF,DDRLAWAR0_VAL |
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| 222 | #endif |
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| 223 | #ifdef DDRLAWBAR1_VAL |
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| 224 | SET_IMM_REGW r31,r30,DDRLAWBAR1_OFF,DDRLAWBAR1_VAL |
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| 225 | #endif |
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| 226 | #ifdef DDRLAWAR1_VAL |
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| 227 | SET_IMM_REGW r31,r30,DDRLAWAR1_OFF,DDRLAWAR1_VAL |
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| 228 | #endif |
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| 229 | /* |
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| 230 | * ROM startup: init refresh interval |
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| 231 | */ |
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| 232 | #ifdef MRPTR_VAL |
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| 233 | SET_IMM_REGW r31,r30,MRPTR_OFF,MRPTR_VAL |
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| 234 | #endif |
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| 235 | /* |
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| 236 | * ROM startup: init SDRAM |
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| 237 | */ |
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| 238 | #ifdef LSRT_VAL |
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| 239 | SET_IMM_REGW r31,r30, LSRT_OFF, LSRT_VAL |
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| 240 | #endif |
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| 241 | #ifdef LSDMR_VAL |
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| 242 | SET_IMM_REGW r31,r30, LSDMR_OFF, LSDMR_VAL |
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| 243 | #endif |
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| 244 | #ifdef CS0_BNDS_VAL |
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| 245 | SET_IMM_REGW r31,r30,CS0_BNDS_OFF,CS0_BNDS_VAL |
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| 246 | #endif |
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| 247 | #ifdef CS1_BNDS_VAL |
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| 248 | SET_IMM_REGW r31,r30,CS1_BNDS_OFF,CS1_BNDS_VAL |
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| 249 | #endif |
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| 250 | #ifdef CS2_BNDS_VAL |
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| 251 | SET_IMM_REGW r31,r30,CS2_BNDS_OFF,CS2_BNDS_VAL |
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| 252 | #endif |
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| 253 | #ifdef CS3_BNDS_VAL |
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| 254 | SET_IMM_REGW r31,r30,CS3_BNDS_OFF,CS3_BNDS_VAL |
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| 255 | #endif |
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| 256 | #ifdef CS0_CONFIG_VAL |
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| 257 | SET_IMM_REGW r31,r30,CS0_CONFIG_OFF,CS0_CONFIG_VAL |
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| 258 | #endif |
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| 259 | #ifdef CS1_CONFIG_VAL |
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| 260 | SET_IMM_REGW r31,r30,CS1_CONFIG_OFF,CS1_CONFIG_VAL |
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| 261 | #endif |
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| 262 | #ifdef CS2_CONFIG_VAL |
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| 263 | SET_IMM_REGW r31,r30,CS2_CONFIG_OFF,CS2_CONFIG_VAL |
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| 264 | #endif |
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| 265 | #ifdef CS3_CONFIG_VAL |
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| 266 | SET_IMM_REGW r31,r30,CS3_CONFIG_OFF,CS3_CONFIG_VAL |
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| 267 | #endif |
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| 268 | #ifdef TIMING_CFG_3_VAL |
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| 269 | SET_IMM_REGW r31,r30,TIMING_CFG_3_OFF,TIMING_CFG_3_VAL |
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| 270 | #endif |
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| 271 | #ifdef TIMING_CFG_0_VAL |
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| 272 | SET_IMM_REGW r31,r30,TIMING_CFG_0_OFF,TIMING_CFG_0_VAL |
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| 273 | #endif |
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| 274 | #ifdef TIMING_CFG_1_VAL |
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| 275 | SET_IMM_REGW r31,r30,TIMING_CFG_1_OFF,TIMING_CFG_1_VAL |
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| 276 | #endif |
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| 277 | #ifdef TIMING_CFG_2_VAL |
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| 278 | SET_IMM_REGW r31,r30,TIMING_CFG_2_OFF,TIMING_CFG_2_VAL |
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| 279 | #endif |
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| 280 | #ifdef DDRCDR_VAL |
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| 281 | SET_IMM_REGW r31,r30,DDRCDR_OFF,DDRCDR_VAL |
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| 282 | #endif |
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| 283 | #ifdef DDR_SDRAM_CFG_2_VAL |
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| 284 | SET_IMM_REGW r31,r30,DDR_SDRAM_CFG_2_OFF,DDR_SDRAM_CFG_2_VAL |
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| 285 | #endif |
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| 286 | #ifdef DDR_SDRAM_MODE_VAL |
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| 287 | SET_IMM_REGW r31,r30,DDR_SDRAM_MODE_OFF,DDR_SDRAM_MODE_VAL |
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| 288 | #endif |
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| 289 | #ifdef DDR_SDRAM_MODE_2_VAL |
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| 290 | SET_IMM_REGW r31,r30,DDR_SDRAM_MODE_2_OFF,DDR_SDRAM_MODE_2_VAL |
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| 291 | #endif |
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| 292 | #ifdef DDR_SDRAM_MD_CNTL_VAL |
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| 293 | SET_IMM_REGW r31,r30,DDR_SDRAM_MD_CNTL_OFF,DDR_SDRAM_MD_CNTL_VAL |
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| 294 | #endif |
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| 295 | #ifdef DDR_SDRAM_MD_ITVL_VAL |
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| 296 | SET_IMM_REGW r31,r30,DDR_SDRAM_MD_ITVL_OFF,DDR_SDRAM_MD_ITVL_VAL |
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| 297 | #endif |
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| 298 | #ifdef DDR_SDRAM_CLK_CNTL_VAL |
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| 299 | SET_IMM_REGW r31,r30,DDR_SDRAM_CLK_CNTL_OFF,DDR_SDRAM_CLK_CNTL_VAL |
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| 300 | #endif |
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| 301 | #ifdef DDR_SDRAM_CFG_2_VAL |
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| 302 | SET_IMM_REGW r31,r30,DDR_SDRAM_CFG_2_OFF,DDR_SDRAM_CFG_2_VAL|DDR_SDRAM_CFG_2_D_INIT |
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| 303 | #endif |
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| 304 | |
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| 305 | #ifdef DDR_ERR_DISABLE_VAL |
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| 306 | /* |
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| 307 | * disable detect of RAM errors |
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| 308 | */ |
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| 309 | SET_IMM_REGW r31,r30,DDR_ERR_DISABLE_OFF,DDR_ERR_DISABLE_VAL |
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| 310 | #endif |
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| 311 | #ifdef DDR_SDRAM_DATA_INIT_VAL |
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| 312 | /* |
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| 313 | * set this value to initialize memory |
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| 314 | */ |
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| 315 | SET_IMM_REGW r31,r30,DDR_SDRAM_DATA_INIT_OFF,DDR_SDRAM_DATA_INIT_VAL |
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| 316 | #endif |
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| 317 | #ifdef DDR_SDRAM_INIT_ADDR_VAL |
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| 318 | SET_IMM_REGW r31,r30,DDR_SDRAM_INIT_ADDR_OFF,DDR_SDRAM_INIT_ADDR_VAL |
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| 319 | #endif |
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| 320 | #ifdef DDR_SDRAM_CFG_VAL |
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| 321 | /* |
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| 322 | * config DDR SDRAM |
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| 323 | */ |
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| 324 | SET_IMM_REGW r31,r30,DDR_SDRAM_CFG_OFF,DDR_SDRAM_CFG_VAL & ~DDR_SDRAM_CFG_MEM_EN |
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| 325 | /* |
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| 326 | * FIXME: wait 200us |
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| 327 | */ |
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| 328 | /* |
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| 329 | * enable DDR SDRAM |
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| 330 | */ |
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| 331 | SET_IMM_REGW r31,r30,DDR_SDRAM_CFG_OFF,DDR_SDRAM_CFG_VAL | DDR_SDRAM_CFG_MEM_EN |
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| 332 | /* |
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| 333 | * wait, until DDR_SDRAM_CFG_2_D_INIT is cleared |
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| 334 | */ |
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| 335 | 1: lwz r30,DDR_SDRAM_CFG_2_OFF(r31) |
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| 336 | andi. r30,r30,DDR_SDRAM_CFG_2_D_INIT |
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| 337 | bne 1b |
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| 338 | #endif |
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| 339 | #ifdef DDR_ERR_DISABLE_VAL2 |
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| 340 | /* |
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| 341 | * enable detect of some RAM errors |
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| 342 | */ |
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| 343 | SET_IMM_REGW r31,r30,DDR_ERR_DISABLE_OFF,DDR_ERR_DISABLE_VAL2 |
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| 344 | #endif |
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| 345 | #ifdef DDR_SDRAM_INTERVAL_VAL |
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| 346 | /* |
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| 347 | * set the refresh interval |
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| 348 | */ |
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| 349 | SET_IMM_REGW r31,r30,DDR_SDRAM_INTERVAL_OFF,DDR_SDRAM_INTERVAL_VAL |
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| 350 | #endif |
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| 351 | start_rom_skip: |
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| 352 | /* |
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| 353 | * determine current execution address offset |
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| 354 | */ |
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| 355 | bl start_rom_skip1 |
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| 356 | start_rom_skip1: |
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| 357 | mflr r20 |
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| 358 | LA r30,start_rom_skip1 |
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| 359 | sub. r20,r20,r30 |
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| 360 | /* |
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| 361 | * execution address offset == 0? |
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| 362 | * then do not relocate code and data |
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| 363 | */ |
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| 364 | beq start_code_in_ram |
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| 365 | /* |
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| 366 | * ROM or relocatable startup: copy startup code to SDRAM |
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| 367 | */ |
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| 368 | /* get start address of text section in RAM */ |
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| 369 | LA r29, bsp_section_text_start |
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| 370 | /* get start address of text section in ROM (add reloc offset) */ |
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| 371 | add r30, r20, r29 |
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| 372 | /* get size of startup code */ |
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| 373 | LA r28, end_reloc_startup |
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| 374 | LA r31, bsp_section_text_start |
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| 375 | sub 28,r28,r31 |
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| 376 | /* copy startup code from ROM to RAM location */ |
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| 377 | bl copy_image |
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| 378 | |
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| 379 | /* |
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| 380 | * ROM startup: jump to code copy in SDRAM |
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| 381 | */ |
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| 382 | /* get compile time address of label */ |
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| 383 | LA r29, copy_rest_of_text |
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| 384 | mtlr r29 |
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| 385 | blr /* now further execution RAM */ |
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| 386 | copy_rest_of_text: |
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| 387 | #ifdef LCRR_VAL |
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| 388 | SET_IMM_REGW r31,r30,LCRR_OFF,LCRR_VAL |
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| 389 | #endif |
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| 390 | /* |
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| 391 | * ROM or relocatable startup: copy rest of code to SDRAM |
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| 392 | */ |
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| 393 | /* get start address of rest of code in RAM */ |
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| 394 | LA r29, end_reloc_startup |
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| 395 | /* get start address of text section in ROM (add reloc offset) */ |
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| 396 | add r30, r20, r29 |
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| 397 | /* get size of rest of code */ |
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| 398 | LA r28, bsp_section_text_start |
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| 399 | LA r31, bsp_section_text_size |
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| 400 | add r28,r28,r31 |
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| 401 | sub r28,r28,r29 |
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| 402 | bl copy_image /* copy text section from ROM to RAM location */ |
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| 403 | |
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| 404 | /* |
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| 405 | * ROM or relocatable startup: copy data to SDRAM |
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| 406 | */ |
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| 407 | /* get start address of data section in RAM */ |
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| 408 | LA r29, bsp_section_data_start |
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| 409 | /* get start address of data section in ROM (add reloc offset) */ |
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| 410 | add r30, r20, r29 |
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| 411 | /* get size of RAM image */ |
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| 412 | LA r28, bsp_section_data_size |
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| 413 | /* copy initialized data section from ROM to RAM location */ |
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| 414 | bl copy_image |
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| 415 | |
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| 416 | start_code_in_ram: |
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| 417 | |
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| 418 | /* |
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| 419 | * ROM/RAM startup: clear bss in SDRAM |
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| 420 | */ |
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| 421 | LA r3, bsp_section_bss_start /* get start address of bss section */ |
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| 422 | LWI r4, bsp_section_bss_size /* get size of bss section */ |
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| 423 | bl mpc83xx_zero_4 /* Clear the bss section */ |
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| 424 | /* |
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| 425 | * call boot_card |
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| 426 | */ |
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| 427 | |
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| 428 | /* Set stack pointer (common for RAM/ROM startup) */ |
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| 429 | LA r1, bsp_section_text_start |
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| 430 | addi r1, r1, -0x10 /* Set up stack pointer = beginning of text section - 0x10 */ |
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| 431 | |
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| 432 | /* Create NULL */ |
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| 433 | li r0, 0 |
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| 434 | |
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| 435 | /* Return address */ |
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| 436 | stw r0, 4(r1) |
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| 437 | |
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| 438 | /* Back chain */ |
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| 439 | stw r0, 0(r1) |
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| 440 | |
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| 441 | /* Read-only small data */ |
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| 442 | LA r2, _SDA2_BASE_ |
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| 443 | |
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| 444 | /* Read-write small data */ |
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| 445 | LA r13, _SDA_BASE_ |
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| 446 | |
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| 447 | /* clear arguments and do further init. in C (common for RAM/ROM startup) */ |
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| 448 | |
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| 449 | /* Clear argc, argv and envp */ |
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| 450 | xor r3, r3, r3 |
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| 451 | xor r4, r4, r4 |
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| 452 | xor r5, r5, r5 |
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| 453 | |
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| 454 | bl SYM (boot_card) /* Call the first C routine */ |
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| 455 | |
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| 456 | twiddle: |
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| 457 | /* We don't expect to return from boot_card but if we do */ |
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| 458 | /* wait here for watchdog to kick us into hard reset */ |
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| 459 | b twiddle |
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| 460 | |
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| 461 | copy_image: |
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| 462 | mr r27, r28 |
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| 463 | srwi r28, r28, 2 |
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| 464 | mtctr r28 |
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| 465 | |
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| 466 | slwi r28, r28, 2 |
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| 467 | sub r27, r27, r28 /* maybe some residual bytes */ |
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| 468 | copy_image_word: |
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| 469 | lswi r28, r30, 0x04 |
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| 470 | |
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| 471 | stswi r28, r29, 0x04 /* do word copy ROM -> RAM */ |
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| 472 | |
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| 473 | |
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| 474 | addi r30, r30, 0x04 /* increment source pointer */ |
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| 475 | addi r29, r29, 0x04 /* increment destination pointer */ |
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| 476 | |
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| 477 | bdnz copy_image_word /* decrement ctr and branch if not 0 */ |
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| 478 | |
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| 479 | cmpwi r27, 0x00 /* copy image finished ? */ |
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| 480 | beq copy_image_end; |
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| 481 | mtctr r27 /* reload counter for residual bytes */ |
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| 482 | copy_image_byte: |
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| 483 | lswi r28, r30, 0x01 |
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| 484 | |
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| 485 | stswi r28, r29, 0x01 /* do byte copy ROM -> RAM */ |
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| 486 | |
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| 487 | |
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| 488 | addi r30, r30, 0x01 /* increment source pointer */ |
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| 489 | addi r29, r29, 0x01 /* increment destination pointer */ |
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| 490 | |
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| 491 | bdnz copy_image_byte /* decrement ctr and branch if not 0 */ |
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| 492 | |
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| 493 | copy_image_end: |
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| 494 | blr |
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| 495 | |
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| 496 | |
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| 497 | /** |
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| 498 | * @fn int mpc83xx_zero_4( void *dest, size_t n) |
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| 499 | * |
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| 500 | * @brief Zero all @a n bytes starting at @a dest with 4 byte writes. |
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| 501 | * |
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| 502 | * The address @a dest has to be aligned on 4 byte boundaries. The size @a n |
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| 503 | * must be evenly divisible by 4. |
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| 504 | */ |
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| 505 | GLOBAL_FUNCTION mpc83xx_zero_4 |
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| 506 | /* Create zero */ |
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| 507 | xor r0, r0, r0 |
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| 508 | |
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| 509 | /* Set offset */ |
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| 510 | xor r5, r5, r5 |
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| 511 | |
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| 512 | /* Loop counter for the first bytes up to 16 bytes */ |
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| 513 | rlwinm. r9, r4, 30, 30, 31 |
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| 514 | beq mpc83xx_zero_4_more |
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| 515 | mtctr r9 |
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| 516 | |
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| 517 | mpc83xx_zero_4_head: |
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| 518 | |
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| 519 | stwx r0, r3, r5 |
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| 520 | addi r5, r5, 4 |
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| 521 | bdnz mpc83xx_zero_4_head |
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| 522 | |
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| 523 | mpc83xx_zero_4_more: |
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| 524 | |
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| 525 | /* More than 16 bytes? */ |
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| 526 | srwi. r9, r4, 4 |
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| 527 | beqlr |
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| 528 | mtctr r9 |
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| 529 | |
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| 530 | /* Set offsets */ |
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| 531 | addi r6, r5, 4 |
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| 532 | addi r7, r5, 8 |
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| 533 | addi r8, r5, 12 |
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| 534 | |
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| 535 | mpc83xx_zero_4_tail: |
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| 536 | |
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| 537 | stwx r0, r3, r5 |
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| 538 | addi r5, r5, 16 |
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| 539 | stwx r0, r3, r6 |
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| 540 | addi r6, r6, 16 |
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| 541 | stwx r0, r3, r7 |
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| 542 | addi r7, r7, 16 |
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| 543 | stwx r0, r3, r8 |
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| 544 | addi r8, r8, 16 |
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| 545 | bdnz mpc83xx_zero_4_tail |
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| 546 | |
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| 547 | /* Return */ |
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| 548 | blr |
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| 549 | |
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| 550 | end_reloc_startup: |
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