[f610e83f] | 1 | /*===============================================================*\ |
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| 2 | | Project: RTEMS support for MPC83xx | |
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| 3 | +-----------------------------------------------------------------+ |
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| 4 | | Copyright (c) 2007 | |
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| 5 | | Embedded Brains GmbH | |
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| 6 | | Obere Lagerstr. 30 | |
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| 7 | | D-82178 Puchheim | |
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| 8 | | Germany | |
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| 9 | | rtems@embedded-brains.de | |
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| 10 | +-----------------------------------------------------------------+ |
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| 11 | | The license and distribution terms for this file may be | |
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| 12 | | found in the file LICENSE in this distribution or at | |
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| 13 | | | |
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| 14 | | http://www.rtems.com/license/LICENSE. | |
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| 15 | | | |
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| 16 | +-----------------------------------------------------------------+ |
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| 17 | | this file contains the board specific portion | |
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| 18 | | of the network interface driver | |
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| 19 | \*===============================================================*/ |
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| 20 | |
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| 21 | #include <rtems.h> |
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| 22 | #include <rtems/rtems_bsdnet.h> |
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[3df08660] | 23 | #include <rtems/rtems_bsdnet_internal.h> |
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[f610e83f] | 24 | #include <bsp.h> |
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[ce0922e] | 25 | #include <bsp/tsec.h> |
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| 26 | #include <bsp/u-boot.h> |
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[f610e83f] | 27 | #include <mpc83xx/mpc83xx.h> |
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[0e1d590c] | 28 | #include <string.h> |
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| 29 | #include <libcpu/spr.h> |
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[f610e83f] | 30 | |
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| 31 | #define TSEC_IFMODE_RGMII 0 |
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| 32 | #define TSEC_IFMODE_GMII 1 |
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[42bf1b9] | 33 | |
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[574fb67] | 34 | #if defined( MPC8313ERDB) |
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| 35 | |
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[214cbd9] | 36 | #define TSEC_IFMODE TSEC_IFMODE_RGMII |
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[42bf1b9] | 37 | |
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[574fb67] | 38 | #elif defined( MPC8349EAMDS) |
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| 39 | |
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[677cf05f] | 40 | #define TSEC_IFMODE TSEC_IFMODE_GMII |
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[574fb67] | 41 | |
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| 42 | #elif defined( HSC_CM01) |
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| 43 | |
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[f610e83f] | 44 | #define TSEC_IFMODE TSEC_IFMODE_RGMII |
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[574fb67] | 45 | |
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| 46 | #else |
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| 47 | |
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| 48 | #warning No TSEC configuration available |
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| 49 | |
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[42bf1b9] | 50 | #endif |
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[f610e83f] | 51 | |
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[0e1d590c] | 52 | /* System Version Register */ |
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| 53 | #define SVR 286 |
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| 54 | SPR_RO( SVR) |
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| 55 | |
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| 56 | /* Processor Version Register */ |
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| 57 | SPR_RO( PVR) |
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| 58 | |
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[f610e83f] | 59 | /*=========================================================================*\ |
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| 60 | | Function: | |
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| 61 | \*-------------------------------------------------------------------------*/ |
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| 62 | int BSP_tsec_attach |
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| 63 | ( |
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| 64 | /*-------------------------------------------------------------------------*\ |
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| 65 | | Purpose: | |
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| 66 | | attach or detach the driver | |
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| 67 | +---------------------------------------------------------------------------+ |
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| 68 | | Input Parameters: | |
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| 69 | \*-------------------------------------------------------------------------*/ |
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| 70 | struct rtems_bsdnet_ifconfig *config, /* interface configuration */ |
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| 71 | int attaching /* 0 = detach, else attach */ |
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| 72 | ) |
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| 73 | /*-------------------------------------------------------------------------*\ |
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| 74 | | Return Value: | |
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| 75 | | 1, if success | |
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| 76 | \*=========================================================================*/ |
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| 77 | { |
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[0e1d590c] | 78 | tsec_config tsec_cfg; |
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[f610e83f] | 79 | int unitNumber; |
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[ce0922e] | 80 | char *unitName; |
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[0e1d590c] | 81 | uint32_t svr = _read_SVR(); |
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| 82 | uint32_t pvr = _read_PVR(); |
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| 83 | |
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| 84 | memset(&tsec_cfg, 0, sizeof(tsec_cfg)); |
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| 85 | config->drv_ctrl = &tsec_cfg; |
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[f610e83f] | 86 | |
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| 87 | /* |
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| 88 | * Parse driver name |
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| 89 | */ |
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[ce0922e] | 90 | if((unitNumber = rtems_bsdnet_parse_driver_name(config, &unitName)) < 0) { |
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[f610e83f] | 91 | return 0; |
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| 92 | } |
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[0e1d590c] | 93 | |
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| 94 | tsec_cfg.reg_ptr = &mpc83xx.tsec [unitNumber - 1]; |
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| 95 | tsec_cfg.mdio_ptr = &mpc83xx.tsec [0]; |
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| 96 | |
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[f610e83f] | 97 | if (attaching) { |
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[42bf1b9] | 98 | #if (TSEC_IFMODE==TSEC_IFMODE_GMII) |
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[4b23c94] | 99 | #if !defined(HSC_CM01) |
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| 100 | |
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| 101 | /* |
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| 102 | * do not change system I/O configuration registers on HSC board |
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| 103 | * because should initialize from RCW |
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| 104 | */ |
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| 105 | |
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| 106 | |
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[f610e83f] | 107 | if (unitNumber == 1) { |
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| 108 | /* |
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[ac7af4a] | 109 | * init system I/O configuration registers |
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| 110 | * to ensure proper pin functions |
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[f610e83f] | 111 | */ |
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[59be902] | 112 | mpc83xx.syscon.sicrh = mpc83xx.syscon.sicrh & ~0x1F800000; |
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[f610e83f] | 113 | /* |
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| 114 | * init port registers (GPIO2DIR) for TSEC1 |
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| 115 | */ |
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| 116 | mpc83xx.gpio[1].gpdir = ((mpc83xx.gpio[1].gpdir & ~0x00000FFF) |
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| 117 | | 0x0000001f); |
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| 118 | } |
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[42bf1b9] | 119 | if (unitNumber == 2) { |
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[59be902] | 120 | /* |
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[ac7af4a] | 121 | * init system I/O configuration registers |
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| 122 | * to ensure proper pin functions |
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[59be902] | 123 | */ |
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| 124 | mpc83xx.syscon.sicrh = mpc83xx.syscon.sicrh & ~0x007f8000; |
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[42bf1b9] | 125 | /* |
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| 126 | * init port registers (GPIO2DIR) for TSEC2 |
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| 127 | */ |
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| 128 | mpc83xx.gpio[0].gpdir = ((mpc83xx.gpio[0].gpdir & ~0x000FFFFF) |
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| 129 | | 0x00087881); |
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| 130 | } |
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[4b23c94] | 131 | #endif /* !defined(HSC_CM01) */ |
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[42bf1b9] | 132 | #endif |
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| 133 | #if (TSEC_IFMODE==TSEC_IFMODE_RGMII) |
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| 134 | |
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[f610e83f] | 135 | /* |
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[42bf1b9] | 136 | * Nothing special needed for TSEC1 operation |
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[f610e83f] | 137 | */ |
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[ac7af4a] | 138 | #endif |
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[f610e83f] | 139 | } |
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| 140 | /* |
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| 141 | * add MAC address into config->hardware_adderss |
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| 142 | * FIXME: get the real address we need |
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| 143 | */ |
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| 144 | if (config->hardware_address == NULL) { |
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[d11ea4eb] | 145 | #if !defined(HAS_UBOOT) |
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[45c8fb6] | 146 | static char hw_addr [TSEC_COUNT][6]; |
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[760ef104] | 147 | volatile tsec_registers *reg_ptr = tsec_cfg.reg_ptr; |
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[d11ea4eb] | 148 | |
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| 149 | /* read MAC address from hardware register */ |
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| 150 | /* we expect it htere from the boot loader */ |
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| 151 | config->hardware_address = hw_addr[unitNumber-1]; |
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[ac7af4a] | 152 | |
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[d11ea4eb] | 153 | hw_addr[unitNumber-1][5] = (reg_ptr->macstnaddr[0] >> 24) & 0xff; |
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| 154 | hw_addr[unitNumber-1][4] = (reg_ptr->macstnaddr[0] >> 16) & 0xff; |
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| 155 | hw_addr[unitNumber-1][3] = (reg_ptr->macstnaddr[0] >> 8) & 0xff; |
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| 156 | hw_addr[unitNumber-1][2] = (reg_ptr->macstnaddr[0] >> 0) & 0xff; |
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| 157 | hw_addr[unitNumber-1][1] = (reg_ptr->macstnaddr[1] >> 24) & 0xff; |
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| 158 | hw_addr[unitNumber-1][0] = (reg_ptr->macstnaddr[1] >> 16) & 0xff; |
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| 159 | #endif |
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[574fb67] | 160 | |
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[d11ea4eb] | 161 | #if defined(HAS_UBOOT) |
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[574fb67] | 162 | switch (unitNumber) { |
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| 163 | case 1: |
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[ac4b164] | 164 | config->hardware_address = bsp_uboot_board_info.bi_enetaddr; |
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[574fb67] | 165 | break; |
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| 166 | |
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| 167 | #ifdef CONFIG_HAS_ETH1 |
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| 168 | case 2: |
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[ac4b164] | 169 | config->hardware_address = bsp_uboot_board_info.bi_enet1addr; |
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[574fb67] | 170 | break; |
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| 171 | #endif /* CONFIG_HAS_ETH1 */ |
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| 172 | |
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| 173 | #ifdef CONFIG_HAS_ETH2 |
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| 174 | case 3: |
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[ac4b164] | 175 | config->hardware_address = bsp_uboot_board_info.bi_enet2addr; |
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[574fb67] | 176 | break; |
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| 177 | #endif /* CONFIG_HAS_ETH2 */ |
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| 178 | |
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| 179 | #ifdef CONFIG_HAS_ETH3 |
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| 180 | case 4: |
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[ac4b164] | 181 | config->hardware_address = bsp_uboot_board_info.bi_enet3addr; |
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[574fb67] | 182 | break; |
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| 183 | #endif /* CONFIG_HAS_ETH3 */ |
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| 184 | |
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| 185 | default: |
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| 186 | return 0; |
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| 187 | } |
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| 188 | |
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| 189 | #endif /* HAS_UBOOT */ |
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| 190 | |
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[f610e83f] | 191 | } |
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| 192 | /* |
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| 193 | * set interrupt number for given interface |
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| 194 | */ |
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[699c2be] | 195 | config->irno = (unsigned) ( |
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| 196 | unitNumber == 1 |
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| 197 | ? BSP_IPIC_IRQ_TSEC1_TX |
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| 198 | : BSP_IPIC_IRQ_TSEC2_TX |
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| 199 | ); |
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[0e1d590c] | 200 | |
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| 201 | if (svr == 0x80b00010 && pvr == 0x80850010) { |
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| 202 | /* |
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| 203 | * This is a special case for MPC8313ERDB with silicon revision 1. Look in |
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| 204 | * "MPC8313ECE Rev. 3, 3/2008" errata for "IPIC 1". |
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| 205 | */ |
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| 206 | if (unitNumber == 1) { |
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| 207 | tsec_cfg.irq_num_tx = 37; |
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| 208 | tsec_cfg.irq_num_rx = 36; |
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| 209 | tsec_cfg.irq_num_err = 35; |
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| 210 | } else if (unitNumber == 2) { |
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| 211 | tsec_cfg.irq_num_tx = 34; |
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| 212 | tsec_cfg.irq_num_rx = 33; |
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| 213 | tsec_cfg.irq_num_err = 32; |
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| 214 | } else { |
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| 215 | return 0; |
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| 216 | } |
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| 217 | } else { |
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| 218 | rtems_irq_number irno = unitNumber == 1 ? |
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| 219 | BSP_IPIC_IRQ_TSEC1_TX : BSP_IPIC_IRQ_TSEC2_TX; |
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| 220 | |
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| 221 | /* get base interrupt number (for Tx irq, Rx=base+1,Err=base+2) */ |
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| 222 | tsec_cfg.irq_num_tx = irno + 0; |
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| 223 | tsec_cfg.irq_num_rx = irno + 1; |
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| 224 | tsec_cfg.irq_num_err = irno + 2; |
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| 225 | } |
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| 226 | |
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| 227 | /* |
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| 228 | * XXX: Although most hardware builders will assign the PHY addresses |
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| 229 | * like this, this should be more configurable |
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| 230 | */ |
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| 231 | #ifdef MPC8313ERDB |
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| 232 | if (unitNumber == 2) { |
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| 233 | tsec_cfg.phy_default = 4; |
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| 234 | } else { |
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| 235 | /* TODO */ |
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| 236 | return 0; |
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| 237 | } |
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| 238 | #else /* MPC8313ERDB */ |
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| 239 | tsec_cfg.phy_default = unitNumber-1; |
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| 240 | #endif /* MPC8313ERDB */ |
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| 241 | |
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| 242 | tsec_cfg.unit_number = unitNumber; |
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| 243 | tsec_cfg.unit_name = unitName; |
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| 244 | |
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[f610e83f] | 245 | /* |
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| 246 | * call attach function of board independent driver |
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| 247 | */ |
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[0e1d590c] | 248 | return tsec_driver_attach_detach(config, attaching); |
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[f610e83f] | 249 | } |
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