1 | /*===============================================================*\ |
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2 | | Project: RTEMS generic MPC83xx BSP | |
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3 | +-----------------------------------------------------------------+ |
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4 | | Copyright (c) 2007 | |
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5 | | Embedded Brains GmbH | |
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6 | | Obere Lagerstr. 30 | |
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7 | | D-82178 Puchheim | |
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8 | | Germany | |
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9 | | rtems@embedded-brains.de | |
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10 | +-----------------------------------------------------------------+ |
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11 | | The license and distribution terms for this file may be | |
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12 | | found in the file LICENSE in this distribution or at | |
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13 | | | |
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14 | | http://www.rtems.com/license/LICENSE. | |
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15 | | | |
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16 | +-----------------------------------------------------------------+ |
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17 | | this file declares constants of the interrupt controller | |
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18 | \*===============================================================*/ |
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19 | #ifndef GEN83xx_IRQ_IRQ_H |
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20 | #define GEN83xx_IRQ_IRQ_H |
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21 | |
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22 | #include <rtems.h> |
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23 | #include <rtems/irq.h> |
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24 | |
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25 | /* |
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26 | * the following definitions specify the indices used |
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27 | * to interface the interrupt handler API |
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28 | */ |
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29 | |
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30 | /* |
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31 | * Peripheral IRQ handlers related definitions |
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32 | */ |
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33 | #define BSP_IPIC_PER_IRQ_NUMBER 128 |
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34 | #define BSP_IPIC_IRQ_LOWEST_OFFSET 0 |
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35 | #define BSP_IPIC_IRQ_MAX_OFFSET (BSP_IPIC_IRQ_LOWEST_OFFSET\ |
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36 | +BSP_IPIC_PER_IRQ_NUMBER-1) |
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37 | |
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38 | #define BSP_IS_IPIC_IRQ(irqnum) \ |
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39 | (((irqnum) >= BSP_IPIC_IRQ_LOWEST_OFFSET) && \ |
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40 | ((irqnum) <= BSP_IPIC_IRQ_MAX_OFFSET)) |
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41 | /* |
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42 | * Processor IRQ handlers related definitions |
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43 | */ |
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44 | #define BSP_PROCESSOR_IRQ_NUMBER 1 |
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45 | #define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_IPIC_IRQ_MAX_OFFSET+1) |
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46 | #define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET\ |
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47 | +BSP_PROCESSOR_IRQ_NUMBER-1) |
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48 | |
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49 | #define BSP_IS_PROCESSOR_IRQ(irqnum) \ |
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50 | (((irqnum) >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET) && \ |
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51 | ((irqnum) <= BSP_PROCESSOR_IRQ_MAX_OFFSET)) |
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52 | /* |
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53 | * Summary |
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54 | */ |
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55 | #define BSP_IRQ_NUMBER (BSP_PROCESSOR_IRQ_MAX_OFFSET+1) |
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56 | #define BSP_LOWEST_OFFSET BSP_IPIC_IRQ_LOWEST_OFFSET |
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57 | #define BSP_MAX_OFFSET BSP_PROCESSOR_IRQ_MAX_OFFSET |
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58 | |
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59 | #define BSP_IS_VALID_IRQ(irqnum) \ |
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60 | (BSP_IS_PROCESSOR_IRQ(irqnum) \ |
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61 | || BSP_IS_IPIC_IRQ(irqnum)) |
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62 | |
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63 | #ifndef ASM |
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64 | #ifdef __cplusplus |
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65 | extern "C" { |
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66 | #endif |
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67 | |
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68 | /* |
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69 | * index table for the module specific handlers, a few entries are only placeholders |
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70 | */ |
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71 | typedef enum { |
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72 | BSP_IPIC_IRQ_FIRST = BSP_IPIC_IRQ_LOWEST_OFFSET, |
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73 | BSP_IPIC_IRQ_ERROR = BSP_IPIC_IRQ_LOWEST_OFFSET + 0, |
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74 | /* reserved irqs 1- 8 */ |
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75 | BSP_IPIC_IRQ_UART1 = BSP_IPIC_IRQ_LOWEST_OFFSET + 9, |
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76 | BSP_IPIC_IRQ_UART2 = BSP_IPIC_IRQ_LOWEST_OFFSET + 10, |
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77 | BSP_IPIC_IRQ_SEC = BSP_IPIC_IRQ_LOWEST_OFFSET + 11, |
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78 | /* reserved irqs 12-13 */ |
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79 | BSP_IPIC_IRQ_I2C1 = BSP_IPIC_IRQ_LOWEST_OFFSET + 14, |
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80 | BSP_IPIC_IRQ_I2C2 = BSP_IPIC_IRQ_LOWEST_OFFSET + 15, |
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81 | BSP_IPIC_IRQ_SPI = BSP_IPIC_IRQ_LOWEST_OFFSET + 16, |
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82 | BSP_IPIC_IRQ_IRQ1 = BSP_IPIC_IRQ_LOWEST_OFFSET + 17, |
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83 | BSP_IPIC_IRQ_IRQ2 = BSP_IPIC_IRQ_LOWEST_OFFSET + 18, |
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84 | BSP_IPIC_IRQ_IRQ3 = BSP_IPIC_IRQ_LOWEST_OFFSET + 19, |
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85 | BSP_IPIC_IRQ_IRQ4 = BSP_IPIC_IRQ_LOWEST_OFFSET + 20, |
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86 | BSP_IPIC_IRQ_IRQ5 = BSP_IPIC_IRQ_LOWEST_OFFSET + 21, |
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87 | BSP_IPIC_IRQ_IRQ6 = BSP_IPIC_IRQ_LOWEST_OFFSET + 22, |
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88 | BSP_IPIC_IRQ_IRQ7 = BSP_IPIC_IRQ_LOWEST_OFFSET + 23, |
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89 | /* reserved irqs 24-31 */ |
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90 | BSP_IPIC_IRQ_TSEC1_TX = BSP_IPIC_IRQ_LOWEST_OFFSET + 32, |
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91 | BSP_IPIC_IRQ_TSEC1_RX = BSP_IPIC_IRQ_LOWEST_OFFSET + 33, |
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92 | BSP_IPIC_IRQ_TSEC1_ERR = BSP_IPIC_IRQ_LOWEST_OFFSET + 34, |
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93 | BSP_IPIC_IRQ_TSEC2_TX = BSP_IPIC_IRQ_LOWEST_OFFSET + 35, |
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94 | BSP_IPIC_IRQ_TSEC2_RX = BSP_IPIC_IRQ_LOWEST_OFFSET + 36, |
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95 | BSP_IPIC_IRQ_TSEC2_ERR = BSP_IPIC_IRQ_LOWEST_OFFSET + 37, |
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96 | BSP_IPIC_IRQ_USB_DR = BSP_IPIC_IRQ_LOWEST_OFFSET + 38, |
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97 | BSP_IPIC_IRQ_USB_MPH = BSP_IPIC_IRQ_LOWEST_OFFSET + 39, |
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98 | /* reserved irqs 40-47 */ |
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99 | BSP_IPIC_IRQ_IRQ0 = BSP_IPIC_IRQ_LOWEST_OFFSET + 48, |
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100 | /* reserved irqs 49-63 */ |
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101 | BSP_IPIC_IRQ_RTC_SEC = BSP_IPIC_IRQ_LOWEST_OFFSET + 64, |
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102 | BSP_IPIC_IRQ_PIT = BSP_IPIC_IRQ_LOWEST_OFFSET + 65, |
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103 | BSP_IPIC_IRQ_PCI1 = BSP_IPIC_IRQ_LOWEST_OFFSET + 66, |
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104 | BSP_IPIC_IRQ_PCI2 = BSP_IPIC_IRQ_LOWEST_OFFSET + 67, |
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105 | BSP_IPIC_IRQ_RTC_ALR = BSP_IPIC_IRQ_LOWEST_OFFSET + 68, |
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106 | BSP_IPIC_IRQ_MU = BSP_IPIC_IRQ_LOWEST_OFFSET + 69, |
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107 | BSP_IPIC_IRQ_SBA = BSP_IPIC_IRQ_LOWEST_OFFSET + 70, |
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108 | BSP_IPIC_IRQ_DMA = BSP_IPIC_IRQ_LOWEST_OFFSET + 71, |
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109 | BSP_IPIC_IRQ_GTM4 = BSP_IPIC_IRQ_LOWEST_OFFSET + 72, |
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110 | BSP_IPIC_IRQ_GTM8 = BSP_IPIC_IRQ_LOWEST_OFFSET + 73, |
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111 | BSP_IPIC_IRQ_GPIO1 = BSP_IPIC_IRQ_LOWEST_OFFSET + 74, |
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112 | BSP_IPIC_IRQ_GPIO2 = BSP_IPIC_IRQ_LOWEST_OFFSET + 75, |
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113 | BSP_IPIC_IRQ_DDR = BSP_IPIC_IRQ_LOWEST_OFFSET + 76, |
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114 | BSP_IPIC_IRQ_LBC = BSP_IPIC_IRQ_LOWEST_OFFSET + 77, |
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115 | BSP_IPIC_IRQ_GTM2 = BSP_IPIC_IRQ_LOWEST_OFFSET + 78, |
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116 | BSP_IPIC_IRQ_GTM6 = BSP_IPIC_IRQ_LOWEST_OFFSET + 79, |
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117 | BSP_IPIC_IRQ_PMC = BSP_IPIC_IRQ_LOWEST_OFFSET + 80, |
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118 | /* reserved irqs 81-83 */ |
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119 | BSP_IPIC_IRQ_GTM3 = BSP_IPIC_IRQ_LOWEST_OFFSET + 84, |
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120 | BSP_IPIC_IRQ_GTM7 = BSP_IPIC_IRQ_LOWEST_OFFSET + 85, |
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121 | /* reserved irqs 86-89 */ |
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122 | BSP_IPIC_IRQ_GTM1 = BSP_IPIC_IRQ_LOWEST_OFFSET + 90, |
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123 | BSP_IPIC_IRQ_GTM5 = BSP_IPIC_IRQ_LOWEST_OFFSET + 91, |
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124 | /* reserved irqs 92-127 */ |
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125 | |
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126 | BSP_IPIC_IRQ_LAST = BSP_IPIC_IRQ_MAX_OFFSET, |
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127 | BSP_DECREMENTER = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 0 |
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128 | } rtems_irq_symbolic_name; |
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129 | |
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130 | extern rtems_irq_connect_data *BSP_rtems_irq_tbl; |
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131 | void BSP_rtems_irq_mng_init(unsigned cpuId); |
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132 | |
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133 | /* ipic.c */ |
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134 | rtems_status_code BSP_irq_handle_at_ipic(uint32_t excNum); |
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135 | void BSP_irq_enable_at_ipic (rtems_irq_number irqnum); |
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136 | void BSP_irq_disable_at_ipic (rtems_irq_number irqnum); |
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137 | |
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138 | #ifdef __cplusplus |
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139 | } |
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140 | #endif |
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141 | #endif /* ASM */ |
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142 | |
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143 | #endif /* GEN83XX_IRQ_IRQ_H */ |
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