source: rtems/c/src/lib/libbsp/powerpc/gen83xx/irq/irq.h @ a045c9d

4.104.114.95
Last change on this file since a045c9d was a045c9d, checked in by Till Straumann <strauman@…>, on 11/30/07 at 20:45:11

2007-11-30 Till Straumann <strauman@…>

  • irq/irq.h, irq/irq_init.c: Removed the definition of ASM_IRQ_VECTOR_BASE; this symbol was only use to initialize the irqBase member of the rtems_irq_global_settings struct. However, irqBase is an rtems_irq_symbolic_name, so using BSP_LOWEST_OFFSET is more appropriate.
  • Property mode set to 100644
File size: 6.2 KB
Line 
1/*===============================================================*\
2| Project: RTEMS generic MPC83xx BSP                              |
3+-----------------------------------------------------------------+
4|                    Copyright (c) 2007                           |
5|                    Embedded Brains GmbH                         |
6|                    Obere Lagerstr. 30                           |
7|                    D-82178 Puchheim                             |
8|                    Germany                                      |
9|                    rtems@embedded-brains.de                     |
10+-----------------------------------------------------------------+
11| The license and distribution terms for this file may be         |
12| found in the file LICENSE in this distribution or at            |
13|                                                                 |
14| http://www.rtems.com/license/LICENSE.                           |
15|                                                                 |
16+-----------------------------------------------------------------+
17| this file declares constants of the interrupt controller        |
18\*===============================================================*/
19#ifndef GEN83xx_IRQ_IRQ_H
20#define GEN83xx_IRQ_IRQ_H
21
22#include <rtems.h>
23#include <rtems/irq.h>
24
25/*
26 * the following definitions specify the indices used
27 * to interface the interrupt handler API
28 */
29
30/*
31 * Peripheral IRQ handlers related definitions
32 */
33#define BSP_IPIC_PER_IRQ_NUMBER         128
34#define BSP_IPIC_IRQ_LOWEST_OFFSET        0
35#define BSP_IPIC_IRQ_MAX_OFFSET      (BSP_IPIC_IRQ_LOWEST_OFFSET\
36                                         +BSP_IPIC_PER_IRQ_NUMBER-1)
37
38#define BSP_IS_IPIC_IRQ(irqnum)                         \
39          (((irqnum) >= BSP_IPIC_IRQ_LOWEST_OFFSET) &&  \
40           ((irqnum) <= BSP_IPIC_IRQ_MAX_OFFSET))
41/*
42 * Processor IRQ handlers related definitions
43 */
44#define BSP_PROCESSOR_IRQ_NUMBER        1
45#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_IPIC_IRQ_MAX_OFFSET+1)
46#define BSP_PROCESSOR_IRQ_MAX_OFFSET    (BSP_PROCESSOR_IRQ_LOWEST_OFFSET\
47                                         +BSP_PROCESSOR_IRQ_NUMBER-1)
48
49#define BSP_IS_PROCESSOR_IRQ(irqnum)                            \
50          (((irqnum) >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET) &&     \
51           ((irqnum) <= BSP_PROCESSOR_IRQ_MAX_OFFSET))
52/*
53 * Summary
54 */
55#define BSP_IRQ_NUMBER                  (BSP_PROCESSOR_IRQ_MAX_OFFSET+1)
56#define BSP_LOWEST_OFFSET               BSP_IPIC_IRQ_LOWEST_OFFSET
57#define BSP_MAX_OFFSET                  BSP_PROCESSOR_IRQ_MAX_OFFSET
58
59#define BSP_IS_VALID_IRQ(irqnum)        \
60          (BSP_IS_PROCESSOR_IRQ(irqnum) \
61           || BSP_IS_IPIC_IRQ(irqnum))
62
63#ifndef ASM
64#ifdef __cplusplus
65extern "C" {
66#endif
67
68/*
69 * index table for the module specific handlers, a few entries are only placeholders
70 */
71  typedef enum {
72    BSP_IPIC_IRQ_FIRST     = BSP_IPIC_IRQ_LOWEST_OFFSET,
73    BSP_IPIC_IRQ_ERROR     = BSP_IPIC_IRQ_LOWEST_OFFSET +  0,
74    /* reserved irqs  1- 8 */
75    BSP_IPIC_IRQ_UART1     = BSP_IPIC_IRQ_LOWEST_OFFSET +  9,
76    BSP_IPIC_IRQ_UART2     = BSP_IPIC_IRQ_LOWEST_OFFSET + 10,
77    BSP_IPIC_IRQ_SEC       = BSP_IPIC_IRQ_LOWEST_OFFSET + 11,
78    /* reserved irqs 12-13 */
79    BSP_IPIC_IRQ_I2C1      = BSP_IPIC_IRQ_LOWEST_OFFSET + 14,
80    BSP_IPIC_IRQ_I2C2      = BSP_IPIC_IRQ_LOWEST_OFFSET + 15,
81    BSP_IPIC_IRQ_SPI       = BSP_IPIC_IRQ_LOWEST_OFFSET + 16,
82    BSP_IPIC_IRQ_IRQ1      = BSP_IPIC_IRQ_LOWEST_OFFSET + 17,
83    BSP_IPIC_IRQ_IRQ2      = BSP_IPIC_IRQ_LOWEST_OFFSET + 18,
84    BSP_IPIC_IRQ_IRQ3      = BSP_IPIC_IRQ_LOWEST_OFFSET + 19,
85    BSP_IPIC_IRQ_IRQ4      = BSP_IPIC_IRQ_LOWEST_OFFSET + 20,
86    BSP_IPIC_IRQ_IRQ5      = BSP_IPIC_IRQ_LOWEST_OFFSET + 21,
87    BSP_IPIC_IRQ_IRQ6      = BSP_IPIC_IRQ_LOWEST_OFFSET + 22,
88    BSP_IPIC_IRQ_IRQ7      = BSP_IPIC_IRQ_LOWEST_OFFSET + 23,
89    /* reserved irqs 24-31 */
90    BSP_IPIC_IRQ_TSEC1_TX  = BSP_IPIC_IRQ_LOWEST_OFFSET + 32,
91    BSP_IPIC_IRQ_TSEC1_RX  = BSP_IPIC_IRQ_LOWEST_OFFSET + 33,
92    BSP_IPIC_IRQ_TSEC1_ERR = BSP_IPIC_IRQ_LOWEST_OFFSET + 34,
93    BSP_IPIC_IRQ_TSEC2_TX  = BSP_IPIC_IRQ_LOWEST_OFFSET + 35,
94    BSP_IPIC_IRQ_TSEC2_RX  = BSP_IPIC_IRQ_LOWEST_OFFSET + 36,
95    BSP_IPIC_IRQ_TSEC2_ERR = BSP_IPIC_IRQ_LOWEST_OFFSET + 37,
96    BSP_IPIC_IRQ_USB_DR    = BSP_IPIC_IRQ_LOWEST_OFFSET + 38,
97    BSP_IPIC_IRQ_USB_MPH   = BSP_IPIC_IRQ_LOWEST_OFFSET + 39,
98    /* reserved irqs 40-47 */
99    BSP_IPIC_IRQ_IRQ0      = BSP_IPIC_IRQ_LOWEST_OFFSET + 48,
100    /* reserved irqs 49-63 */
101    BSP_IPIC_IRQ_RTC_SEC   = BSP_IPIC_IRQ_LOWEST_OFFSET + 64,
102    BSP_IPIC_IRQ_PIT       = BSP_IPIC_IRQ_LOWEST_OFFSET + 65,
103    BSP_IPIC_IRQ_PCI1      = BSP_IPIC_IRQ_LOWEST_OFFSET + 66,
104    BSP_IPIC_IRQ_PCI2      = BSP_IPIC_IRQ_LOWEST_OFFSET + 67,
105    BSP_IPIC_IRQ_RTC_ALR   = BSP_IPIC_IRQ_LOWEST_OFFSET + 68,
106    BSP_IPIC_IRQ_MU        = BSP_IPIC_IRQ_LOWEST_OFFSET + 69,
107    BSP_IPIC_IRQ_SBA       = BSP_IPIC_IRQ_LOWEST_OFFSET + 70,
108    BSP_IPIC_IRQ_DMA       = BSP_IPIC_IRQ_LOWEST_OFFSET + 71,
109    BSP_IPIC_IRQ_GTM4      = BSP_IPIC_IRQ_LOWEST_OFFSET + 72,
110    BSP_IPIC_IRQ_GTM8      = BSP_IPIC_IRQ_LOWEST_OFFSET + 73,
111    BSP_IPIC_IRQ_GPIO1     = BSP_IPIC_IRQ_LOWEST_OFFSET + 74,
112    BSP_IPIC_IRQ_GPIO2     = BSP_IPIC_IRQ_LOWEST_OFFSET + 75,
113    BSP_IPIC_IRQ_DDR       = BSP_IPIC_IRQ_LOWEST_OFFSET + 76,
114    BSP_IPIC_IRQ_LBC       = BSP_IPIC_IRQ_LOWEST_OFFSET + 77,
115    BSP_IPIC_IRQ_GTM2      = BSP_IPIC_IRQ_LOWEST_OFFSET + 78,
116    BSP_IPIC_IRQ_GTM6      = BSP_IPIC_IRQ_LOWEST_OFFSET + 79,
117    BSP_IPIC_IRQ_PMC       = BSP_IPIC_IRQ_LOWEST_OFFSET + 80,
118    /* reserved irqs 81-83 */
119    BSP_IPIC_IRQ_GTM3      = BSP_IPIC_IRQ_LOWEST_OFFSET + 84,
120    BSP_IPIC_IRQ_GTM7      = BSP_IPIC_IRQ_LOWEST_OFFSET + 85,
121    /* reserved irqs 86-89 */
122    BSP_IPIC_IRQ_GTM1      = BSP_IPIC_IRQ_LOWEST_OFFSET + 90,
123    BSP_IPIC_IRQ_GTM5      = BSP_IPIC_IRQ_LOWEST_OFFSET + 91,
124    /* reserved irqs 92-127 */
125
126    BSP_IPIC_IRQ_LAST     = BSP_IPIC_IRQ_MAX_OFFSET,
127    BSP_DECREMENTER       = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 0
128  } rtems_irq_symbolic_name;
129
130  extern rtems_irq_connect_data *BSP_rtems_irq_tbl;
131  void BSP_rtems_irq_mng_init(unsigned cpuId);
132
133  /* ipic.c */
134  rtems_status_code BSP_irq_handle_at_ipic(uint32_t excNum);
135  void BSP_irq_enable_at_ipic (rtems_irq_number irqnum);
136  void BSP_irq_disable_at_ipic (rtems_irq_number irqnum);
137
138#ifdef __cplusplus
139}
140#endif
141#endif /* ASM */
142
143#endif /* GEN83XX_IRQ_IRQ_H */
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