1 | /*===============================================================*\ |
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2 | | Project: RTEMS generic MPC83xx BSP | |
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3 | +-----------------------------------------------------------------+ |
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4 | | Copyright (c) 2007 | |
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5 | | Embedded Brains GmbH | |
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6 | | Obere Lagerstr. 30 | |
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7 | | D-82178 Puchheim | |
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8 | | Germany | |
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9 | | rtems@embedded-brains.de | |
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10 | +-----------------------------------------------------------------+ |
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11 | | The license and distribution terms for this file may be | |
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12 | | found in the file LICENSE in this distribution or at | |
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13 | | | |
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14 | | http://www.rtems.org/license/LICENSE. | |
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15 | | | |
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16 | +-----------------------------------------------------------------+ |
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17 | | this file integrates the IPIC irq controller | |
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18 | \*===============================================================*/ |
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19 | |
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20 | #include <mpc83xx/mpc83xx.h> |
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21 | |
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22 | #include <rtems.h> |
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23 | |
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24 | #include <libcpu/powerpc-utility.h> |
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25 | #include <bsp/vectors.h> |
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26 | |
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27 | #include <bsp.h> |
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28 | #include <bsp/irq.h> |
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29 | #include <bsp/irq-generic.h> |
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30 | |
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31 | #define MPC83XX_IPIC_VECTOR_NUMBER 92 |
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32 | |
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33 | #define MPC83XX_IPIC_IS_VALID_VECTOR( vector) ((vector) >= 0 && (vector) < MPC83XX_IPIC_VECTOR_NUMBER) |
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34 | |
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35 | #define MPC83XX_IPIC_INVALID_MASK_POSITION 255 |
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36 | |
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37 | typedef struct { |
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38 | volatile uint32_t *pend_reg; |
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39 | volatile uint32_t *mask_reg; |
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40 | const uint32_t bit_num; |
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41 | } BSP_isrc_rsc_t; |
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42 | |
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43 | /* |
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44 | * data structure to handle all mask registers in the IPIC |
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45 | * |
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46 | * Mask positions: |
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47 | * simsr [0] : 0 .. 31 |
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48 | * simsr [1] : 32 .. 63 |
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49 | * semsr : 64 .. 95 |
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50 | * sermr : 96 .. 127 |
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51 | */ |
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52 | typedef struct { |
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53 | uint32_t simsr_mask [2]; |
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54 | uint32_t semsr_mask; |
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55 | uint32_t sermr_mask; |
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56 | } mpc83xx_ipic_mask_t; |
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57 | |
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58 | static const BSP_isrc_rsc_t mpc83xx_ipic_isrc_rsc [MPC83XX_IPIC_VECTOR_NUMBER] = { |
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59 | /* vector 0 */ |
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60 | {&mpc83xx.ipic.sersr, &mpc83xx.ipic.sermr, 31}, |
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61 | {NULL, NULL, 0}, |
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62 | {NULL, NULL, 0}, |
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63 | {NULL, NULL, 0}, |
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64 | {NULL, NULL, 0}, |
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65 | {NULL, NULL, 0}, |
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66 | {NULL, NULL, 0}, |
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67 | {NULL, NULL, 0}, |
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68 | /* vector 8 */ |
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69 | {NULL, NULL, 0}, /* reserved vector 8 */ |
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70 | /* vector 9: UART1 SIxxR_H, Bit 24 */ |
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71 | {&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 24}, |
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72 | /* vector 10: UART2 SIxxR_H, Bit 25 */ |
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73 | {&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 25}, |
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74 | /* vector 11: SEC SIxxR_H, Bit 26 */ |
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75 | {&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 26}, |
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76 | {NULL, NULL, 0}, /* reserved vector 12 */ |
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77 | {NULL, NULL, 0}, /* reserved vector 13 */ |
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78 | /* vector 14: I2C1 SIxxR_H, Bit 29 */ |
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79 | {&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 29}, |
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80 | /* vector 15: I2C2 SIxxR_H, Bit 30 */ |
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81 | {&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 30}, |
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82 | /* vector 16: SPI SIxxR_H, Bit 31 */ |
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83 | {&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 31}, |
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84 | /* vector 17: IRQ1 SExxR , Bit 1 */ |
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85 | {&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 1}, |
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86 | /* vector 18: IRQ2 SExxR , Bit 2 */ |
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87 | {&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 2}, |
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88 | /* vector 19: IRQ3 SExxR , Bit 3 */ |
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89 | {&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 3}, |
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90 | /* vector 20: IRQ4 SExxR , Bit 4 */ |
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91 | {&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 4}, |
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92 | /* vector 21: IRQ5 SExxR , Bit 5 */ |
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93 | {&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 5}, |
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94 | /* vector 22: IRQ6 SExxR , Bit 6 */ |
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95 | {&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 6}, |
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96 | /* vector 23: IRQ7 SExxR , Bit 7 */ |
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97 | {&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 7}, |
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98 | {NULL, NULL, 0}, /* reserved vector 24 */ |
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99 | {NULL, NULL, 0}, /* reserved vector 25 */ |
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100 | {NULL, NULL, 0}, /* reserved vector 26 */ |
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101 | {NULL, NULL, 0}, /* reserved vector 27 */ |
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102 | {NULL, NULL, 0}, /* reserved vector 28 */ |
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103 | {NULL, NULL, 0}, /* reserved vector 29 */ |
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104 | {NULL, NULL, 0}, /* reserved vector 30 */ |
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105 | {NULL, NULL, 0}, /* reserved vector 31 */ |
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106 | /* vector 32: TSEC1 Tx SIxxR_H , Bit 0 */ |
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107 | {&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 0}, |
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108 | /* vector 33: TSEC1 Rx SIxxR_H , Bit 1 */ |
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109 | {&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 1}, |
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110 | /* vector 34: TSEC1 Err SIxxR_H , Bit 2 */ |
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111 | {&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 2}, |
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112 | /* vector 35: TSEC2 Tx SIxxR_H , Bit 3 */ |
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113 | {&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 3}, |
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114 | /* vector 36: TSEC2 Rx SIxxR_H , Bit 4 */ |
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115 | {&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 4}, |
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116 | /* vector 37: TSEC2 Err SIxxR_H , Bit 5 */ |
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117 | {&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 5}, |
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118 | /* vector 38: USB DR SIxxR_H , Bit 6 */ |
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119 | {&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 6}, |
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120 | /* vector 39: USB MPH SIxxR_H , Bit 7 */ |
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121 | {&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 7}, |
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122 | {NULL, NULL, 0}, /* reserved vector 40 */ |
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123 | {NULL, NULL, 0}, /* reserved vector 41 */ |
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124 | {NULL, NULL, 0}, /* reserved vector 42 */ |
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125 | {NULL, NULL, 0}, /* reserved vector 43 */ |
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126 | {NULL, NULL, 0}, /* reserved vector 44 */ |
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127 | {NULL, NULL, 0}, /* reserved vector 45 */ |
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128 | {NULL, NULL, 0}, /* reserved vector 46 */ |
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129 | {NULL, NULL, 0}, /* reserved vector 47 */ |
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130 | /* vector 48: IRQ0 SExxR , Bit 0 */ |
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131 | {&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 0}, |
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132 | {NULL, NULL, 0}, /* reserved vector 49 */ |
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133 | {NULL, NULL, 0}, /* reserved vector 50 */ |
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134 | {NULL, NULL, 0}, /* reserved vector 51 */ |
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135 | {NULL, NULL, 0}, /* reserved vector 52 */ |
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136 | {NULL, NULL, 0}, /* reserved vector 53 */ |
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137 | {NULL, NULL, 0}, /* reserved vector 54 */ |
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138 | {NULL, NULL, 0}, /* reserved vector 55 */ |
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139 | {NULL, NULL, 0}, /* reserved vector 56 */ |
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140 | {NULL, NULL, 0}, /* reserved vector 57 */ |
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141 | {NULL, NULL, 0}, /* reserved vector 58 */ |
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142 | {NULL, NULL, 0}, /* reserved vector 59 */ |
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143 | {NULL, NULL, 0}, /* reserved vector 60 */ |
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144 | {NULL, NULL, 0}, /* reserved vector 61 */ |
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145 | {NULL, NULL, 0}, /* reserved vector 62 */ |
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146 | {NULL, NULL, 0}, /* reserved vector 63 */ |
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147 | /* vector 64: RTC SEC SIxxR_L , Bit 0 */ |
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148 | {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 0}, |
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149 | /* vector 65: PIT SIxxR_L , Bit 1 */ |
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150 | {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 1}, |
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151 | /* vector 66: PCI1 SIxxR_L , Bit 2 */ |
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152 | {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 2}, |
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153 | /* vector 67: PCI2 SIxxR_L , Bit 3 */ |
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154 | {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 3}, |
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155 | /* vector 68: RTC ALR SIxxR_L , Bit 4 */ |
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156 | {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 4}, |
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157 | /* vector 69: MU SIxxR_L , Bit 5 */ |
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158 | {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 5}, |
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159 | /* vector 70: SBA SIxxR_L , Bit 6 */ |
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160 | {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 6}, |
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161 | /* vector 71: DMA SIxxR_L , Bit 7 */ |
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162 | {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 7}, |
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163 | /* vector 72: GTM4 SIxxR_L , Bit 8 */ |
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164 | {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 8}, |
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165 | /* vector 73: GTM8 SIxxR_L , Bit 9 */ |
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166 | {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 9}, |
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167 | /* vector 74: GPIO1 SIxxR_L , Bit 10 */ |
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168 | {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 10}, |
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169 | /* vector 75: GPIO2 SIxxR_L , Bit 11 */ |
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170 | {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 11}, |
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171 | /* vector 76: DDR SIxxR_L , Bit 12 */ |
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172 | {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 12}, |
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173 | /* vector 77: LBC SIxxR_L , Bit 13 */ |
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174 | {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 13}, |
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175 | /* vector 78: GTM2 SIxxR_L , Bit 14 */ |
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176 | {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 14}, |
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177 | /* vector 79: GTM6 SIxxR_L , Bit 15 */ |
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178 | {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 15}, |
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179 | /* vector 80: PMC SIxxR_L , Bit 16 */ |
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180 | {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 16}, |
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181 | {NULL, NULL, 0}, /* reserved vector 81 */ |
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182 | {NULL, NULL, 0}, /* reserved vector 82 */ |
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183 | {NULL, NULL, 0}, /* reserved vector 63 */ |
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184 | /* vector 84: GTM3 SIxxR_L , Bit 20 */ |
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185 | {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 20}, |
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186 | /* vector 85: GTM7 SIxxR_L , Bit 21 */ |
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187 | {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 21}, |
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188 | {NULL, NULL, 0}, /* reserved vector 81 */ |
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189 | {NULL, NULL, 0}, /* reserved vector 82 */ |
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190 | {NULL, NULL, 0}, /* reserved vector 63 */ |
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191 | {NULL, NULL, 0}, /* reserved vector 63 */ |
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192 | /* vector 90: GTM1 SIxxR_L , Bit 26 */ |
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193 | {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 26}, |
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194 | /* vector 91: GTM5 SIxxR_L , Bit 27 */ |
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195 | {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 27} |
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196 | }; |
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197 | |
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198 | static const uint8_t |
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199 | mpc83xx_ipic_mask_position_table [MPC83XX_IPIC_VECTOR_NUMBER] = { |
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200 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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201 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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202 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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203 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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204 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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205 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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206 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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207 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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208 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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209 | 7, |
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210 | 6, |
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211 | 5, |
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212 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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213 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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214 | 2, |
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215 | 1, |
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216 | 0, |
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217 | 94, |
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218 | 93, |
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219 | 92, |
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220 | 91, |
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221 | 90, |
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222 | 89, |
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223 | 88, |
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224 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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225 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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226 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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227 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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228 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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229 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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230 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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231 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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232 | 31, |
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233 | 30, |
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234 | 29, |
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235 | 28, |
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236 | 27, |
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237 | 26, |
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238 | 25, |
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239 | 24, |
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240 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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241 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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242 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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243 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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244 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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245 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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246 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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247 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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248 | 95, |
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249 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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250 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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251 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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252 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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253 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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254 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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255 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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256 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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257 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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258 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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259 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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260 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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261 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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262 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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263 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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264 | 63, |
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265 | 62, |
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266 | 61, |
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267 | 60, |
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268 | 59, |
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269 | 58, |
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270 | 57, |
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271 | 56, |
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272 | 55, |
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273 | 54, |
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274 | 53, |
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275 | 52, |
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276 | 51, |
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277 | 50, |
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278 | 49, |
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279 | 48, |
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280 | 47, |
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281 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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282 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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283 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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284 | 43, |
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285 | 42, |
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286 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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287 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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288 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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289 | MPC83XX_IPIC_INVALID_MASK_POSITION, |
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290 | 37, |
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291 | 36 |
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292 | }; |
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293 | |
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294 | /* |
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295 | * this array will be filled with mask values needed |
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296 | * to temporarily disable all IRQ soures with lower or same |
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297 | * priority of the current source (whose vector is the array index) |
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298 | */ |
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299 | static mpc83xx_ipic_mask_t mpc83xx_ipic_prio2mask [MPC83XX_IPIC_VECTOR_NUMBER]; |
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300 | |
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301 | rtems_status_code mpc83xx_ipic_set_mask( |
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302 | rtems_vector_number vector, |
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303 | rtems_vector_number mask_vector, |
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304 | bool mask |
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305 | ) |
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306 | { |
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307 | uint8_t pos = 0; |
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308 | mpc83xx_ipic_mask_t *mask_entry; |
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309 | uint32_t *mask_reg; |
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310 | rtems_interrupt_level level; |
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311 | |
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312 | /* Parameter check */ |
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313 | if (!MPC83XX_IPIC_IS_VALID_VECTOR( vector) || |
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314 | !MPC83XX_IPIC_IS_VALID_VECTOR( mask_vector)) { |
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315 | return RTEMS_INVALID_NUMBER; |
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316 | } else if (vector == mask_vector) { |
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317 | return RTEMS_RESOURCE_IN_USE; |
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318 | } |
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319 | |
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320 | /* Position and mask entry */ |
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321 | pos = mpc83xx_ipic_mask_position_table [mask_vector]; |
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322 | mask_entry = &mpc83xx_ipic_prio2mask [vector]; |
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323 | |
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324 | /* Mask register and position */ |
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325 | if (pos < 32) { |
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326 | mask_reg = &mask_entry->simsr_mask [0]; |
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327 | } else if (pos < 64) { |
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328 | pos -= 32; |
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329 | mask_reg = &mask_entry->simsr_mask [1]; |
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330 | } else if (pos < 96) { |
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331 | pos -= 64; |
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332 | mask_reg = &mask_entry->semsr_mask; |
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333 | } else if (pos < 128) { |
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334 | pos -= 96; |
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335 | mask_reg = &mask_entry->sermr_mask; |
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336 | } else { |
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337 | return RTEMS_NOT_IMPLEMENTED; |
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338 | } |
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339 | |
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340 | /* Mask or unmask */ |
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341 | if (mask) { |
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342 | rtems_interrupt_disable( level); |
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343 | *mask_reg &= ~(1 << pos); |
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344 | rtems_interrupt_enable( level); |
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345 | } else { |
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346 | rtems_interrupt_disable( level); |
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347 | *mask_reg |= 1 << pos; |
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348 | rtems_interrupt_enable( level); |
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349 | } |
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350 | |
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351 | return RTEMS_SUCCESSFUL; |
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352 | } |
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353 | |
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354 | rtems_status_code mpc83xx_ipic_set_highest_priority_interrupt( |
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355 | rtems_vector_number vector, |
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356 | int type |
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357 | ) |
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358 | { |
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359 | rtems_interrupt_level level; |
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360 | uint32_t reg = 0; |
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361 | |
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362 | if (!MPC83XX_IPIC_IS_VALID_VECTOR( vector)) { |
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363 | return RTEMS_INVALID_NUMBER; |
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364 | } else if (type < 0 || type > MPC83XX_IPIC_INTERRUPT_CRITICAL) { |
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365 | return RTEMS_INVALID_NUMBER; |
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366 | } |
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367 | |
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368 | rtems_interrupt_disable( level); |
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369 | reg = mpc83xx.ipic.sicfr; |
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370 | mpc83xx.ipic.sicfr = (reg & ~0x7f000300) | (vector << 24) | (type << 8); |
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371 | rtems_interrupt_enable( level); |
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372 | |
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373 | return RTEMS_SUCCESSFUL; |
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374 | } |
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375 | |
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376 | /* |
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377 | * functions to enable/disable a source at the ipic |
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378 | */ |
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379 | void bsp_interrupt_vector_enable( rtems_vector_number vector) |
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380 | { |
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381 | rtems_vector_number vecnum = vector - BSP_IPIC_IRQ_LOWEST_OFFSET; |
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382 | const BSP_isrc_rsc_t *rsc_ptr; |
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383 | |
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384 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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385 | |
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386 | if (MPC83XX_IPIC_IS_VALID_VECTOR( vecnum)) { |
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387 | rsc_ptr = &mpc83xx_ipic_isrc_rsc [vecnum]; |
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388 | if (rsc_ptr->mask_reg != NULL) { |
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389 | uint32_t bit = 1U << (31 - rsc_ptr->bit_num); |
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390 | rtems_interrupt_level level; |
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391 | |
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392 | rtems_interrupt_disable(level); |
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393 | *(rsc_ptr->mask_reg) |= bit; |
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394 | rtems_interrupt_enable(level); |
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395 | } |
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396 | } |
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397 | } |
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398 | |
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399 | void bsp_interrupt_vector_disable( rtems_vector_number vector) |
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400 | { |
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401 | rtems_vector_number vecnum = vector - BSP_IPIC_IRQ_LOWEST_OFFSET; |
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402 | const BSP_isrc_rsc_t *rsc_ptr; |
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403 | |
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404 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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405 | |
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406 | if (MPC83XX_IPIC_IS_VALID_VECTOR( vecnum)) { |
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407 | rsc_ptr = &mpc83xx_ipic_isrc_rsc [vecnum]; |
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408 | if (rsc_ptr->mask_reg != NULL) { |
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409 | uint32_t bit = 1U << (31 - rsc_ptr->bit_num); |
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410 | rtems_interrupt_level level; |
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411 | |
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412 | rtems_interrupt_disable(level); |
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413 | *(rsc_ptr->mask_reg) &= ~bit; |
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414 | rtems_interrupt_enable(level); |
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415 | } |
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416 | } |
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417 | } |
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418 | |
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419 | /* |
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420 | * IRQ Handler: this is called from the primary exception dispatcher |
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421 | */ |
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422 | static int BSP_irq_handle_at_ipic( unsigned excNum) |
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423 | { |
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424 | int32_t vecnum; |
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425 | #ifdef GEN83XX_ENABLE_INTERRUPT_NESTING |
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426 | mpc83xx_ipic_mask_t mask_save; |
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427 | const mpc83xx_ipic_mask_t *mask_ptr; |
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428 | uint32_t msr = 0; |
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429 | rtems_interrupt_level level; |
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430 | #endif |
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431 | |
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432 | /* Get vector number */ |
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433 | switch (excNum) { |
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434 | case ASM_EXT_VECTOR: |
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435 | vecnum = MPC83xx_VCR_TO_VEC( mpc83xx.ipic.sivcr); |
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436 | break; |
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437 | case ASM_E300_SYSMGMT_VECTOR: |
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438 | vecnum = MPC83xx_VCR_TO_VEC( mpc83xx.ipic.smvcr); |
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439 | break; |
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440 | case ASM_E300_CRIT_VECTOR: |
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441 | vecnum = MPC83xx_VCR_TO_VEC( mpc83xx.ipic.scvcr); |
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442 | break; |
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443 | default: |
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444 | return 1; |
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445 | } |
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446 | |
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447 | /* |
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448 | * Check the vector number, mask lower priority interrupts, enable |
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449 | * exceptions and dispatch the handler. |
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450 | */ |
---|
451 | if (MPC83XX_IPIC_IS_VALID_VECTOR( vecnum)) { |
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452 | #ifdef GEN83XX_ENABLE_INTERRUPT_NESTING |
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453 | mask_ptr = &mpc83xx_ipic_prio2mask [vecnum]; |
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454 | |
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455 | rtems_interrupt_disable( level); |
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456 | |
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457 | /* Save current mask registers */ |
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458 | mask_save.simsr_mask [0] = mpc83xx.ipic.simsr [0]; |
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459 | mask_save.simsr_mask [1] = mpc83xx.ipic.simsr [1]; |
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460 | mask_save.semsr_mask = mpc83xx.ipic.semsr; |
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461 | mask_save.sermr_mask = mpc83xx.ipic.sermr; |
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462 | |
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463 | /* Mask all lower priority interrupts */ |
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464 | mpc83xx.ipic.simsr [0] &= mask_ptr->simsr_mask [0]; |
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465 | mpc83xx.ipic.simsr [1] &= mask_ptr->simsr_mask [1]; |
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466 | mpc83xx.ipic.semsr &= mask_ptr->semsr_mask; |
---|
467 | mpc83xx.ipic.sermr &= mask_ptr->sermr_mask; |
---|
468 | |
---|
469 | rtems_interrupt_enable( level); |
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470 | |
---|
471 | /* Enable all interrupts */ |
---|
472 | if (excNum != ASM_E300_CRIT_VECTOR) { |
---|
473 | msr = ppc_external_exceptions_enable(); |
---|
474 | } |
---|
475 | #endif /* GEN83XX_ENABLE_INTERRUPT_NESTING */ |
---|
476 | |
---|
477 | /* Dispatch interrupt handlers */ |
---|
478 | bsp_interrupt_handler_dispatch( vecnum + BSP_IPIC_IRQ_LOWEST_OFFSET); |
---|
479 | |
---|
480 | #ifdef GEN83XX_ENABLE_INTERRUPT_NESTING |
---|
481 | /* Restore machine state */ |
---|
482 | if (excNum != ASM_E300_CRIT_VECTOR) { |
---|
483 | ppc_external_exceptions_disable( msr); |
---|
484 | } |
---|
485 | |
---|
486 | /* Restore initial masks */ |
---|
487 | rtems_interrupt_disable( level); |
---|
488 | mpc83xx.ipic.simsr [0] = mask_save.simsr_mask [0]; |
---|
489 | mpc83xx.ipic.simsr [1] = mask_save.simsr_mask [1]; |
---|
490 | mpc83xx.ipic.semsr = mask_save.semsr_mask; |
---|
491 | mpc83xx.ipic.sermr = mask_save.sermr_mask; |
---|
492 | rtems_interrupt_enable( level); |
---|
493 | #endif /* GEN83XX_ENABLE_INTERRUPT_NESTING */ |
---|
494 | } else { |
---|
495 | bsp_interrupt_handler_default( vecnum); |
---|
496 | } |
---|
497 | |
---|
498 | return 0; |
---|
499 | } |
---|
500 | |
---|
501 | /* |
---|
502 | * Fill the array mpc83xx_ipic_prio2mask to allow masking of lower prio sources |
---|
503 | * to implement nested interrupts. |
---|
504 | */ |
---|
505 | static rtems_status_code mpc83xx_ipic_calc_prio2mask(void) |
---|
506 | { |
---|
507 | rtems_status_code rc = RTEMS_SUCCESSFUL; |
---|
508 | |
---|
509 | /* |
---|
510 | * FIXME: fill the array |
---|
511 | */ |
---|
512 | return rc; |
---|
513 | } |
---|
514 | |
---|
515 | /* |
---|
516 | * Activate the interrupt controller |
---|
517 | */ |
---|
518 | static rtems_status_code mpc83xx_ipic_initialize(void) |
---|
519 | { |
---|
520 | /* |
---|
521 | * mask off all interrupts |
---|
522 | */ |
---|
523 | mpc83xx.ipic.simsr [0] = 0; |
---|
524 | mpc83xx.ipic.simsr [1] = 0; |
---|
525 | mpc83xx.ipic.semsr = 0; |
---|
526 | mpc83xx.ipic.sermr = 0; |
---|
527 | /* |
---|
528 | * set desired configuration as defined in bspopts.h |
---|
529 | * normally, the default values should be fine |
---|
530 | */ |
---|
531 | #if defined( BSP_SICFR_VAL) /* defined in bspopts.h ? */ |
---|
532 | mpc83xx.ipic.sicfr = BSP_SICFR_VAL; |
---|
533 | #endif |
---|
534 | |
---|
535 | /* |
---|
536 | * set desired priorities as defined in bspopts.h |
---|
537 | * normally, the default values should be fine |
---|
538 | */ |
---|
539 | #if defined( BSP_SIPRR0_VAL) /* defined in bspopts.h ? */ |
---|
540 | mpc83xx.ipic.siprr [0] = BSP_SIPRR0_VAL; |
---|
541 | #endif |
---|
542 | |
---|
543 | #if defined( BSP_SIPRR1_VAL) /* defined in bspopts.h ? */ |
---|
544 | mpc83xx.ipic.siprr [1] = BSP_SIPRR1_VAL; |
---|
545 | #endif |
---|
546 | |
---|
547 | #if defined( BSP_SIPRR2_VAL) /* defined in bspopts.h ? */ |
---|
548 | mpc83xx.ipic.siprr [2] = BSP_SIPRR2_VAL; |
---|
549 | #endif |
---|
550 | |
---|
551 | #if defined( BSP_SIPRR3_VAL) /* defined in bspopts.h ? */ |
---|
552 | mpc83xx.ipic.siprr [3] = BSP_SIPRR3_VAL; |
---|
553 | #endif |
---|
554 | |
---|
555 | #if defined( BSP_SMPRR0_VAL) /* defined in bspopts.h ? */ |
---|
556 | mpc83xx.ipic.smprr [0] = BSP_SMPRR0_VAL; |
---|
557 | #endif |
---|
558 | |
---|
559 | #if defined( BSP_SMPRR1_VAL) /* defined in bspopts.h ? */ |
---|
560 | mpc83xx.ipic.smprr [1] = BSP_SMPRR1_VAL; |
---|
561 | #endif |
---|
562 | |
---|
563 | #if defined( BSP_SECNR_VAL) /* defined in bspopts.h ? */ |
---|
564 | mpc83xx.ipic.secnr = BSP_SECNR_VAL; |
---|
565 | #endif |
---|
566 | |
---|
567 | /* |
---|
568 | * calculate priority masks |
---|
569 | */ |
---|
570 | return mpc83xx_ipic_calc_prio2mask(); |
---|
571 | } |
---|
572 | |
---|
573 | static int mpc83xx_exception_handler( |
---|
574 | BSP_Exception_frame *frame, |
---|
575 | unsigned exception_number |
---|
576 | ) |
---|
577 | { |
---|
578 | return BSP_irq_handle_at_ipic( exception_number); |
---|
579 | } |
---|
580 | |
---|
581 | rtems_status_code bsp_interrupt_facility_initialize() |
---|
582 | { |
---|
583 | /* Install exception handler */ |
---|
584 | if (ppc_exc_set_handler( ASM_EXT_VECTOR, mpc83xx_exception_handler)) { |
---|
585 | return RTEMS_IO_ERROR; |
---|
586 | } |
---|
587 | if (ppc_exc_set_handler( ASM_E300_SYSMGMT_VECTOR, mpc83xx_exception_handler)) { |
---|
588 | return RTEMS_IO_ERROR; |
---|
589 | } |
---|
590 | if (ppc_exc_set_handler( ASM_E300_CRIT_VECTOR, mpc83xx_exception_handler)) { |
---|
591 | return RTEMS_IO_ERROR; |
---|
592 | } |
---|
593 | |
---|
594 | /* Initialize the interrupt controller */ |
---|
595 | return mpc83xx_ipic_initialize(); |
---|
596 | } |
---|