source: rtems/c/src/lib/libbsp/powerpc/gen83xx/irq/irq.c @ 2d2de4eb

4.104.115
Last change on this file since 2d2de4eb was 2d2de4eb, checked in by Thomas Doerfler <Thomas.Doerfler@…>, on 10/23/09 at 07:32:46

Update for exception support changes.
  • Property mode set to 100644
File size: 17.4 KB
Line 
1/*===============================================================*\
2| Project: RTEMS generic MPC83xx BSP                              |
3+-----------------------------------------------------------------+
4|                    Copyright (c) 2007                           |
5|                    Embedded Brains GmbH                         |
6|                    Obere Lagerstr. 30                           |
7|                    D-82178 Puchheim                             |
8|                    Germany                                      |
9|                    rtems@embedded-brains.de                     |
10+-----------------------------------------------------------------+
11| The license and distribution terms for this file may be         |
12| found in the file LICENSE in this distribution or at            |
13|                                                                 |
14| http://www.rtems.com/license/LICENSE.                           |
15|                                                                 |
16+-----------------------------------------------------------------+
17| this file integrates the IPIC irq controller                    |
18\*===============================================================*/
19
20#include <mpc83xx/mpc83xx.h>
21
22#include <rtems.h>
23
24#include <libcpu/powerpc-utility.h>
25#include <bsp/vectors.h>
26
27#include <bsp.h>
28#include <bsp/irq.h>
29#include <bsp/irq-generic.h>
30
31#define MPC83XX_IPIC_VECTOR_NUMBER 92
32
33#define MPC83XX_IPIC_IS_VALID_VECTOR( vector) ((vector) >= 0 && (vector) < MPC83XX_IPIC_VECTOR_NUMBER)
34
35#define MPC83XX_IPIC_INVALID_MASK_POSITION 255
36
37typedef struct {
38        volatile uint32_t *pend_reg;
39        volatile uint32_t *mask_reg;
40        const uint32_t bit_num;
41} BSP_isrc_rsc_t;
42
43/*
44 * data structure to handle all mask registers in the IPIC
45 *
46 * Mask positions:
47 *   simsr [0] :  0 .. 31
48 *   simsr [1] : 32 .. 63
49 *   semsr     : 64 .. 95
50 *   sermr     : 96 .. 127
51 */
52typedef struct {
53        uint32_t simsr_mask [2];
54        uint32_t semsr_mask;
55        uint32_t sermr_mask;
56} mpc83xx_ipic_mask_t;
57
58static const BSP_isrc_rsc_t mpc83xx_ipic_isrc_rsc [MPC83XX_IPIC_VECTOR_NUMBER] = {
59        /* vector 0 */
60        {&mpc83xx.ipic.sersr, &mpc83xx.ipic.sermr, 31},
61        {NULL, NULL, 0},
62        {NULL, NULL, 0},
63        {NULL, NULL, 0},
64        {NULL, NULL, 0},
65        {NULL, NULL, 0},
66        {NULL, NULL, 0},
67        {NULL, NULL, 0},
68        /* vector  8 */
69        {NULL, NULL, 0},        /* reserved vector  8 */
70        /* vector  9: UART1 SIxxR_H, Bit 24 */
71        {&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 24},
72        /* vector 10: UART2 SIxxR_H, Bit 25 */
73        {&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 25},
74        /* vector 11: SEC   SIxxR_H, Bit 26 */
75        {&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 26},
76        {NULL, NULL, 0},        /* reserved vector 12 */
77        {NULL, NULL, 0},        /* reserved vector 13 */
78        /* vector 14: I2C1 SIxxR_H, Bit 29 */
79        {&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 29},
80        /* vector 15: I2C2 SIxxR_H, Bit 30 */
81        {&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 30},
82        /* vector 16: SPI  SIxxR_H, Bit 31 */
83        {&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 31},
84        /* vector 17: IRQ1 SExxR  , Bit  1 */
85        {&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 1},
86        /* vector 18: IRQ2 SExxR  , Bit  2 */
87        {&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 2},
88        /* vector 19: IRQ3 SExxR  , Bit  3 */
89        {&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 3},
90        /* vector 20: IRQ4 SExxR  , Bit  4 */
91        {&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 4},
92        /* vector 21: IRQ5 SExxR  , Bit  5 */
93        {&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 5},
94        /* vector 22: IRQ6 SExxR  , Bit  6 */
95        {&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 6},
96        /* vector 23: IRQ7 SExxR  , Bit  7 */
97        {&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 7},
98        {NULL, NULL, 0},        /* reserved vector 24 */
99        {NULL, NULL, 0},        /* reserved vector 25 */
100        {NULL, NULL, 0},        /* reserved vector 26 */
101        {NULL, NULL, 0},        /* reserved vector 27 */
102        {NULL, NULL, 0},        /* reserved vector 28 */
103        {NULL, NULL, 0},        /* reserved vector 29 */
104        {NULL, NULL, 0},        /* reserved vector 30 */
105        {NULL, NULL, 0},        /* reserved vector 31 */
106        /* vector 32: TSEC1 Tx  SIxxR_H  , Bit  0 */
107        {&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 0},
108        /* vector 33: TSEC1 Rx  SIxxR_H  , Bit  1 */
109        {&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 1},
110        /* vector 34: TSEC1 Err SIxxR_H  , Bit  2 */
111        {&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 2},
112        /* vector 35: TSEC2 Tx  SIxxR_H  , Bit  3 */
113        {&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 3},
114        /* vector 36: TSEC2 Rx  SIxxR_H  , Bit  4 */
115        {&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 4},
116        /* vector 37: TSEC2 Err SIxxR_H  , Bit  5 */
117        {&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 5},
118        /* vector 38: USB DR    SIxxR_H  , Bit  6 */
119        {&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 6},
120        /* vector 39: USB MPH   SIxxR_H  , Bit  7 */
121        {&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 7},
122        {NULL, NULL, 0},        /* reserved vector 40 */
123        {NULL, NULL, 0},        /* reserved vector 41 */
124        {NULL, NULL, 0},        /* reserved vector 42 */
125        {NULL, NULL, 0},        /* reserved vector 43 */
126        {NULL, NULL, 0},        /* reserved vector 44 */
127        {NULL, NULL, 0},        /* reserved vector 45 */
128        {NULL, NULL, 0},        /* reserved vector 46 */
129        {NULL, NULL, 0},        /* reserved vector 47 */
130        /* vector 48: IRQ0 SExxR  , Bit  0 */
131        {&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 0},
132        {NULL, NULL, 0},        /* reserved vector 49 */
133        {NULL, NULL, 0},        /* reserved vector 50 */
134        {NULL, NULL, 0},        /* reserved vector 51 */
135        {NULL, NULL, 0},        /* reserved vector 52 */
136        {NULL, NULL, 0},        /* reserved vector 53 */
137        {NULL, NULL, 0},        /* reserved vector 54 */
138        {NULL, NULL, 0},        /* reserved vector 55 */
139        {NULL, NULL, 0},        /* reserved vector 56 */
140        {NULL, NULL, 0},        /* reserved vector 57 */
141        {NULL, NULL, 0},        /* reserved vector 58 */
142        {NULL, NULL, 0},        /* reserved vector 59 */
143        {NULL, NULL, 0},        /* reserved vector 60 */
144        {NULL, NULL, 0},        /* reserved vector 61 */
145        {NULL, NULL, 0},        /* reserved vector 62 */
146        {NULL, NULL, 0},        /* reserved vector 63 */
147        /* vector 64: RTC SEC   SIxxR_L  , Bit  0 */
148        {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 0},
149        /* vector 65: PIT       SIxxR_L  , Bit  1 */
150        {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 1},
151        /* vector 66: PCI1      SIxxR_L  , Bit  2 */
152        {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 2},
153        /* vector 67: PCI2      SIxxR_L  , Bit  3 */
154        {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 3},
155        /* vector 68: RTC ALR   SIxxR_L  , Bit  4 */
156        {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 4},
157        /* vector 69: MU        SIxxR_L  , Bit  5 */
158        {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 5},
159        /* vector 70: SBA       SIxxR_L  , Bit  6 */
160        {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 6},
161        /* vector 71: DMA       SIxxR_L  , Bit  7 */
162        {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 7},
163        /* vector 72: GTM4      SIxxR_L  , Bit  8 */
164        {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 8},
165        /* vector 73: GTM8      SIxxR_L  , Bit  9 */
166        {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 9},
167        /* vector 74: GPIO1     SIxxR_L  , Bit 10 */
168        {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 10},
169        /* vector 75: GPIO2     SIxxR_L  , Bit 11 */
170        {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 11},
171        /* vector 76: DDR       SIxxR_L  , Bit 12 */
172        {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 12},
173        /* vector 77: LBC       SIxxR_L  , Bit 13 */
174        {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 13},
175        /* vector 78: GTM2      SIxxR_L  , Bit 14 */
176        {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 14},
177        /* vector 79: GTM6      SIxxR_L  , Bit 15 */
178        {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 15},
179        /* vector 80: PMC       SIxxR_L  , Bit 16 */
180        {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 16},
181        {NULL, NULL, 0},        /* reserved vector 81 */
182        {NULL, NULL, 0},        /* reserved vector 82 */
183        {NULL, NULL, 0},        /* reserved vector 63 */
184        /* vector 84: GTM3      SIxxR_L  , Bit 20 */
185        {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 20},
186        /* vector 85: GTM7      SIxxR_L  , Bit 21 */
187        {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 21},
188        {NULL, NULL, 0},        /* reserved vector 81 */
189        {NULL, NULL, 0},        /* reserved vector 82 */
190        {NULL, NULL, 0},        /* reserved vector 63 */
191        {NULL, NULL, 0},        /* reserved vector 63 */
192        /* vector 90: GTM1      SIxxR_L  , Bit 26 */
193        {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 26},
194        /* vector 91: GTM5      SIxxR_L  , Bit 27 */
195        {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 27}
196};
197
198static const uint8_t mpc83xx_ipic_mask_position_table [MPC83XX_IPIC_VECTOR_NUMBER] = {
199        MPC83XX_IPIC_INVALID_MASK_POSITION,
200        MPC83XX_IPIC_INVALID_MASK_POSITION,
201        MPC83XX_IPIC_INVALID_MASK_POSITION,
202        MPC83XX_IPIC_INVALID_MASK_POSITION,
203        MPC83XX_IPIC_INVALID_MASK_POSITION,
204        MPC83XX_IPIC_INVALID_MASK_POSITION,
205        MPC83XX_IPIC_INVALID_MASK_POSITION,
206        MPC83XX_IPIC_INVALID_MASK_POSITION,
207        MPC83XX_IPIC_INVALID_MASK_POSITION,
208        7,
209        6,
210        5,
211        MPC83XX_IPIC_INVALID_MASK_POSITION,
212        MPC83XX_IPIC_INVALID_MASK_POSITION,
213        2,
214        1,
215        0,
216        94,
217        93,
218        92,
219        91,
220        90,
221        89,
222        88,
223        MPC83XX_IPIC_INVALID_MASK_POSITION,
224        MPC83XX_IPIC_INVALID_MASK_POSITION,
225        MPC83XX_IPIC_INVALID_MASK_POSITION,
226        MPC83XX_IPIC_INVALID_MASK_POSITION,
227        MPC83XX_IPIC_INVALID_MASK_POSITION,
228        MPC83XX_IPIC_INVALID_MASK_POSITION,
229        MPC83XX_IPIC_INVALID_MASK_POSITION,
230        MPC83XX_IPIC_INVALID_MASK_POSITION,
231        31,
232        30,
233        29,
234        28,
235        27,
236        26,
237        25,
238        24,
239        MPC83XX_IPIC_INVALID_MASK_POSITION,
240        MPC83XX_IPIC_INVALID_MASK_POSITION,
241        MPC83XX_IPIC_INVALID_MASK_POSITION,
242        MPC83XX_IPIC_INVALID_MASK_POSITION,
243        MPC83XX_IPIC_INVALID_MASK_POSITION,
244        MPC83XX_IPIC_INVALID_MASK_POSITION,
245        MPC83XX_IPIC_INVALID_MASK_POSITION,
246        MPC83XX_IPIC_INVALID_MASK_POSITION,
247        95,
248        MPC83XX_IPIC_INVALID_MASK_POSITION,
249        MPC83XX_IPIC_INVALID_MASK_POSITION,
250        MPC83XX_IPIC_INVALID_MASK_POSITION,
251        MPC83XX_IPIC_INVALID_MASK_POSITION,
252        MPC83XX_IPIC_INVALID_MASK_POSITION,
253        MPC83XX_IPIC_INVALID_MASK_POSITION,
254        MPC83XX_IPIC_INVALID_MASK_POSITION,
255        MPC83XX_IPIC_INVALID_MASK_POSITION,
256        MPC83XX_IPIC_INVALID_MASK_POSITION,
257        MPC83XX_IPIC_INVALID_MASK_POSITION,
258        MPC83XX_IPIC_INVALID_MASK_POSITION,
259        MPC83XX_IPIC_INVALID_MASK_POSITION,
260        MPC83XX_IPIC_INVALID_MASK_POSITION,
261        MPC83XX_IPIC_INVALID_MASK_POSITION,
262        MPC83XX_IPIC_INVALID_MASK_POSITION,
263        63,
264        62,
265        61,
266        60,
267        59,
268        58,
269        57,
270        56,
271        55,
272        54,
273        53,
274        52,
275        51,
276        50,
277        49,
278        48,
279        47,
280        MPC83XX_IPIC_INVALID_MASK_POSITION,
281        MPC83XX_IPIC_INVALID_MASK_POSITION,
282        MPC83XX_IPIC_INVALID_MASK_POSITION,
283        43,
284        42,
285        MPC83XX_IPIC_INVALID_MASK_POSITION,
286        MPC83XX_IPIC_INVALID_MASK_POSITION,
287        MPC83XX_IPIC_INVALID_MASK_POSITION,
288        MPC83XX_IPIC_INVALID_MASK_POSITION,
289        37,
290        36
291};
292
293/*
294 * this array will be filled with mask values needed
295 * to temporarily disable all IRQ soures with lower or same
296 * priority of the current source (whose vector is the array index)
297 */
298static mpc83xx_ipic_mask_t mpc83xx_ipic_prio2mask [MPC83XX_IPIC_VECTOR_NUMBER];
299
300rtems_status_code mpc83xx_ipic_set_mask( rtems_vector_number vector, rtems_vector_number mask_vector, bool mask)
301{
302        uint8_t pos = 0;
303        mpc83xx_ipic_mask_t *mask_entry;
304        uint32_t *mask_reg;
305        rtems_interrupt_level level;
306
307        /* Parameter check */
308        if (!MPC83XX_IPIC_IS_VALID_VECTOR( vector) || !MPC83XX_IPIC_IS_VALID_VECTOR( mask_vector)) {
309                return RTEMS_INVALID_NUMBER;
310        } else if (vector == mask_vector) {
311                return RTEMS_RESOURCE_IN_USE;
312        }
313
314        /* Position and mask entry */
315        pos = mpc83xx_ipic_mask_position_table [mask_vector];
316        mask_entry = &mpc83xx_ipic_prio2mask [vector];
317
318        /* Mask register and position */
319        if (pos < 32) {
320                mask_reg = &mask_entry->simsr_mask [0];
321        } else if (pos < 64) {
322                pos -= 32;
323                mask_reg = &mask_entry->simsr_mask [1];
324        } else if (pos < 96) {
325                pos -= 64;
326                mask_reg = &mask_entry->semsr_mask;
327        } else if (pos < 128) {
328                pos -= 96;
329                mask_reg = &mask_entry->sermr_mask;
330        } else {
331                return RTEMS_NOT_IMPLEMENTED;
332        }
333
334        /* Mask or unmask */
335        if (mask) {
336                rtems_interrupt_disable( level);
337                *mask_reg &= ~(1 << pos);
338                rtems_interrupt_enable( level);
339        } else {
340                rtems_interrupt_disable( level);
341                *mask_reg |= 1 << pos;
342                rtems_interrupt_enable( level);
343        }
344
345        return RTEMS_SUCCESSFUL;
346}
347
348rtems_status_code mpc83xx_ipic_set_highest_priority_interrupt( rtems_vector_number vector, int type)
349{
350        rtems_interrupt_level level;
351        uint32_t reg = 0;
352
353        if (!MPC83XX_IPIC_IS_VALID_VECTOR( vector)) {
354                return RTEMS_INVALID_NUMBER;
355        } else if (type < 0 || type > MPC83XX_IPIC_INTERRUPT_CRITICAL) {
356                return RTEMS_INVALID_NUMBER;
357        }
358
359        rtems_interrupt_disable( level);
360        reg = mpc83xx.ipic.sicfr;
361        mpc83xx.ipic.sicfr = (reg & ~0x7f000300) | (vector << 24) | (type << 8);
362        rtems_interrupt_enable( level);
363
364        return RTEMS_SUCCESSFUL;
365}
366
367/*
368 * functions to enable/disable a source at the ipic
369 */
370rtems_status_code bsp_interrupt_vector_enable( rtems_vector_number irqnum)
371{
372        rtems_vector_number vecnum = irqnum - BSP_IPIC_IRQ_LOWEST_OFFSET;
373        const BSP_isrc_rsc_t *rsc_ptr;
374
375        if (MPC83XX_IPIC_IS_VALID_VECTOR( vecnum)) {
376                rsc_ptr = &mpc83xx_ipic_isrc_rsc [vecnum];
377                if (rsc_ptr->mask_reg != NULL) {
378                        *(rsc_ptr->mask_reg) |= 1 << (31 - rsc_ptr->bit_num);
379                }
380        }
381
382        return RTEMS_SUCCESSFUL;
383}
384
385rtems_status_code bsp_interrupt_vector_disable( rtems_vector_number irqnum)
386{
387        rtems_vector_number vecnum = irqnum - BSP_IPIC_IRQ_LOWEST_OFFSET;
388        const BSP_isrc_rsc_t *rsc_ptr;
389
390        if (MPC83XX_IPIC_IS_VALID_VECTOR( vecnum)) {
391                rsc_ptr = &mpc83xx_ipic_isrc_rsc [vecnum];
392                if (rsc_ptr->mask_reg != NULL) {
393                        *(rsc_ptr->mask_reg) &= ~(1 << (31 - rsc_ptr->bit_num));
394                }
395        }
396
397        return RTEMS_SUCCESSFUL;
398}
399
400
401/*
402 *  IRQ Handler: this is called from the primary exception dispatcher
403 */
404static int BSP_irq_handle_at_ipic( unsigned excNum)
405{
406        int32_t vecnum;
407        mpc83xx_ipic_mask_t mask_save;
408        const mpc83xx_ipic_mask_t *mask_ptr;
409        uint32_t msr;
410        rtems_interrupt_level level;
411
412        /* Get vector number */
413        switch (excNum) {
414                case ASM_EXT_VECTOR:
415                        vecnum = MPC83xx_VCR_TO_VEC( mpc83xx.ipic.sivcr);
416                        break;
417                case ASM_E300_SYSMGMT_VECTOR:
418                        vecnum = MPC83xx_VCR_TO_VEC( mpc83xx.ipic.smvcr);
419                        break;
420                case ASM_E300_CRIT_VECTOR:
421                        vecnum = MPC83xx_VCR_TO_VEC( mpc83xx.ipic.scvcr);
422                        break;
423                default:
424                        return 1;
425        }
426
427        /*
428         * Check the vector number, mask lower priority interrupts, enable
429         * exceptions and dispatch the handler.
430         */
431        if (MPC83XX_IPIC_IS_VALID_VECTOR( vecnum)) {
432                mask_ptr = &mpc83xx_ipic_prio2mask [vecnum];
433
434                rtems_interrupt_disable( level);
435
436                /* Save current mask registers */
437                mask_save.simsr_mask [0] = mpc83xx.ipic.simsr [0];
438                mask_save.simsr_mask [1] = mpc83xx.ipic.simsr [1];
439                mask_save.semsr_mask = mpc83xx.ipic.semsr;
440                mask_save.sermr_mask = mpc83xx.ipic.sermr;
441
442                /* Mask all lower priority interrupts */
443                mpc83xx.ipic.simsr [0] &= mask_ptr->simsr_mask [0];
444                mpc83xx.ipic.simsr [1] &= mask_ptr->simsr_mask [1];
445                mpc83xx.ipic.semsr &= mask_ptr->semsr_mask;
446                mpc83xx.ipic.sermr &= mask_ptr->sermr_mask;
447
448                rtems_interrupt_enable( level);
449
450                /* Enable all interrupts */
451                if (excNum != ASM_E300_CRIT_VECTOR) {
452                        msr = ppc_external_exceptions_enable();
453                }
454
455                /* Dispatch interrupt handlers */
456                bsp_interrupt_handler_dispatch( vecnum + BSP_IPIC_IRQ_LOWEST_OFFSET);
457
458                /* Restore machine state */
459                if (excNum != ASM_E300_CRIT_VECTOR) {
460                        ppc_external_exceptions_disable( msr);
461                }
462
463                /* Restore initial masks */
464                rtems_interrupt_disable( level);
465                mpc83xx.ipic.simsr [0] = mask_save.simsr_mask [0];
466                mpc83xx.ipic.simsr [1] = mask_save.simsr_mask [1];
467                mpc83xx.ipic.semsr = mask_save.semsr_mask;
468                mpc83xx.ipic.sermr = mask_save.sermr_mask;
469                rtems_interrupt_enable( level);
470        } else {
471                bsp_interrupt_handler_default( vecnum);
472        }
473
474        return 0;
475}
476
477/*
478 * Fill the array mpc83xx_ipic_prio2mask to allow masking of lower prio sources
479 * to implement nested interrupts.
480 */
481rtems_status_code mpc83xx_ipic_calc_prio2mask( void)
482{
483        rtems_status_code rc = RTEMS_SUCCESSFUL;
484
485        /*
486         * FIXME: fill the array
487         */
488        return rc;
489}
490
491/*
492 * Activate the interrupt controller
493 */
494rtems_status_code mpc83xx_ipic_initialize( void)
495{
496        /*
497         * mask off all interrupts
498         */
499        mpc83xx.ipic.simsr [0] = 0;
500        mpc83xx.ipic.simsr [1] = 0;
501        mpc83xx.ipic.semsr = 0;
502        mpc83xx.ipic.sermr = 0;
503        /*
504         * set desired configuration as defined in bspopts.h
505         * normally, the default values should be fine
506         */
507#if defined( BSP_SICFR_VAL)     /* defined in bspopts.h ? */
508        mpc83xx.ipic.sicfr = BSP_SICFR_VAL;
509#endif
510
511        /*
512         * set desired priorities as defined in bspopts.h
513         * normally, the default values should be fine
514         */
515#if defined( BSP_SIPRR0_VAL)    /* defined in bspopts.h ? */
516        mpc83xx.ipic.siprr [0] = BSP_SIPRR0_VAL;
517#endif
518
519#if defined( BSP_SIPRR1_VAL)    /* defined in bspopts.h ? */
520        mpc83xx.ipic.siprr [1] = BSP_SIPRR1_VAL;
521#endif
522
523#if defined( BSP_SIPRR2_VAL)    /* defined in bspopts.h ? */
524        mpc83xx.ipic.siprr [2] = BSP_SIPRR2_VAL;
525#endif
526
527#if defined( BSP_SIPRR3_VAL)    /* defined in bspopts.h ? */
528        mpc83xx.ipic.siprr [3] = BSP_SIPRR3_VAL;
529#endif
530
531#if defined( BSP_SMPRR0_VAL)    /* defined in bspopts.h ? */
532        mpc83xx.ipic.smprr [0] = BSP_SMPRR0_VAL;
533#endif
534
535#if defined( BSP_SMPRR1_VAL)    /* defined in bspopts.h ? */
536        mpc83xx.ipic.smprr [1] = BSP_SMPRR1_VAL;
537#endif
538
539#if defined( BSP_SECNR_VAL)     /* defined in bspopts.h ? */
540        mpc83xx.ipic.secnr = BSP_SECNR_VAL;
541#endif
542
543        /*
544         * calculate priority masks
545         */
546        return mpc83xx_ipic_calc_prio2mask();
547}
548
549int mpc83xx_exception_handler( BSP_Exception_frame *frame, unsigned exception_number)
550{
551        return BSP_irq_handle_at_ipic( exception_number);
552}
553
554rtems_status_code bsp_interrupt_facility_initialize()
555{
556        /* Install exception handler */
557        if (ppc_exc_set_handler( ASM_EXT_VECTOR, mpc83xx_exception_handler)) {
558                return RTEMS_IO_ERROR;
559        }
560        if (ppc_exc_set_handler( ASM_E300_SYSMGMT_VECTOR, mpc83xx_exception_handler)) {
561                return RTEMS_IO_ERROR;
562        }
563        if (ppc_exc_set_handler( ASM_E300_CRIT_VECTOR, mpc83xx_exception_handler)) {
564                return RTEMS_IO_ERROR;
565        }
566
567        /* Initialize the interrupt controller */
568        return mpc83xx_ipic_initialize();
569}
570
571void bsp_interrupt_handler_default( rtems_vector_number vector)
572{
573        printk( "Spurious interrupt: 0x%08x\n", vector);
574}
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