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source: rtems/c/src/lib/libbsp/powerpc/gen83xx/irq/irq.c @ e570c313

4.115

Last change on this file since e570c313 was e570c313, checked in by Joel Sherrill <joel.sherrill@…>, on 01/24/11 at 15:32:04

2011-01-24 Joel Sherrill <joel.sherrill@…>

configure.ac, console/console-config.c, i2c/i2c_init.c, include/bsp.h, include/hwreg_vals.h, include/irq.h, include/tm27.h, include/tsec-config.h, irq/irq.c, network/network.c, spi/spi_init.c, startup/bspstart.c: Address some of the issues spotted by the check_bsp script.

Property mode set to 100644

File size: 17.4 KB

Rev	Line
[574fb67]	1	/===============================================================\
	2	\| Project: RTEMS generic MPC83xx BSP \|
	3	+-----------------------------------------------------------------+
	4	\| Copyright (c) 2007 \|
	5	\| Embedded Brains GmbH \|
	6	\| Obere Lagerstr. 30 \|
	7	\| D-82178 Puchheim \|
	8	\| Germany \|
	9	\| rtems@embedded-brains.de \|
	10	+-----------------------------------------------------------------+
	11	\| The license and distribution terms for this file may be \|
	12	\| found in the file LICENSE in this distribution or at \|
	13	\| \|
	14	\| http://www.rtems.com/license/LICENSE. \|
	15	\| \|
	16	+-----------------------------------------------------------------+
	17	\| this file integrates the IPIC irq controller \|
	18	\===============================================================/
	19
[e570c313]	20	/*
	21	* $Id$
	22	*/
	23
[574fb67]	24	#include <mpc83xx/mpc83xx.h>
	25
	26	#include <rtems.h>
	27
	28	#include <libcpu/powerpc-utility.h>
[2d2de4eb]	29	#include <bsp/vectors.h>
[574fb67]	30
	31	#include <bsp.h>
	32	#include <bsp/irq.h>
	33	#include <bsp/irq-generic.h>
	34
	35	#define MPC83XX_IPIC_VECTOR_NUMBER 92
	36
	37	#define MPC83XX_IPIC_IS_VALID_VECTOR( vector) ((vector) >= 0 && (vector) < MPC83XX_IPIC_VECTOR_NUMBER)
	38
	39	#define MPC83XX_IPIC_INVALID_MASK_POSITION 255
	40
	41	typedef struct {
	42	volatile uint32_t *pend_reg;
	43	volatile uint32_t *mask_reg;
	44	const uint32_t bit_num;
	45	} BSP_isrc_rsc_t;
	46
	47	/*
	48	* data structure to handle all mask registers in the IPIC
	49	*
	50	* Mask positions:
	51	* simsr [0] : 0 .. 31
	52	* simsr [1] : 32 .. 63
	53	* semsr : 64 .. 95
	54	* sermr : 96 .. 127
	55	*/
	56	typedef struct {
	57	uint32_t simsr_mask [2];
	58	uint32_t semsr_mask;
	59	uint32_t sermr_mask;
	60	} mpc83xx_ipic_mask_t;
	61
	62	static const BSP_isrc_rsc_t mpc83xx_ipic_isrc_rsc [MPC83XX_IPIC_VECTOR_NUMBER] = {
	63	/* vector 0 */
	64	{&mpc83xx.ipic.sersr, &mpc83xx.ipic.sermr, 31},
	65	{NULL, NULL, 0},
	66	{NULL, NULL, 0},
	67	{NULL, NULL, 0},
	68	{NULL, NULL, 0},
	69	{NULL, NULL, 0},
	70	{NULL, NULL, 0},
	71	{NULL, NULL, 0},
	72	/* vector 8 */
	73	{NULL, NULL, 0}, /* reserved vector 8 */
	74	/* vector 9: UART1 SIxxR_H, Bit 24 */
	75	{&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 24},
	76	/* vector 10: UART2 SIxxR_H, Bit 25 */
	77	{&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 25},
	78	/* vector 11: SEC SIxxR_H, Bit 26 */
	79	{&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 26},
	80	{NULL, NULL, 0}, /* reserved vector 12 */
	81	{NULL, NULL, 0}, /* reserved vector 13 */
	82	/* vector 14: I2C1 SIxxR_H, Bit 29 */
	83	{&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 29},
	84	/* vector 15: I2C2 SIxxR_H, Bit 30 */
	85	{&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 30},
	86	/* vector 16: SPI SIxxR_H, Bit 31 */
	87	{&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 31},
	88	/* vector 17: IRQ1 SExxR , Bit 1 */
	89	{&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 1},
	90	/* vector 18: IRQ2 SExxR , Bit 2 */
	91	{&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 2},
	92	/* vector 19: IRQ3 SExxR , Bit 3 */
	93	{&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 3},
	94	/* vector 20: IRQ4 SExxR , Bit 4 */
	95	{&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 4},
	96	/* vector 21: IRQ5 SExxR , Bit 5 */
	97	{&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 5},
	98	/* vector 22: IRQ6 SExxR , Bit 6 */
	99	{&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 6},
	100	/* vector 23: IRQ7 SExxR , Bit 7 */
	101	{&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 7},
	102	{NULL, NULL, 0}, /* reserved vector 24 */
	103	{NULL, NULL, 0}, /* reserved vector 25 */
	104	{NULL, NULL, 0}, /* reserved vector 26 */
	105	{NULL, NULL, 0}, /* reserved vector 27 */
	106	{NULL, NULL, 0}, /* reserved vector 28 */
	107	{NULL, NULL, 0}, /* reserved vector 29 */
	108	{NULL, NULL, 0}, /* reserved vector 30 */
	109	{NULL, NULL, 0}, /* reserved vector 31 */
	110	/* vector 32: TSEC1 Tx SIxxR_H , Bit 0 */
	111	{&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 0},
	112	/* vector 33: TSEC1 Rx SIxxR_H , Bit 1 */
	113	{&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 1},
	114	/* vector 34: TSEC1 Err SIxxR_H , Bit 2 */
	115	{&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 2},
	116	/* vector 35: TSEC2 Tx SIxxR_H , Bit 3 */
	117	{&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 3},
	118	/* vector 36: TSEC2 Rx SIxxR_H , Bit 4 */
	119	{&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 4},
	120	/* vector 37: TSEC2 Err SIxxR_H , Bit 5 */
	121	{&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 5},
	122	/* vector 38: USB DR SIxxR_H , Bit 6 */
	123	{&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 6},
	124	/* vector 39: USB MPH SIxxR_H , Bit 7 */
	125	{&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 7},
	126	{NULL, NULL, 0}, /* reserved vector 40 */
	127	{NULL, NULL, 0}, /* reserved vector 41 */
	128	{NULL, NULL, 0}, /* reserved vector 42 */
	129	{NULL, NULL, 0}, /* reserved vector 43 */
	130	{NULL, NULL, 0}, /* reserved vector 44 */
	131	{NULL, NULL, 0}, /* reserved vector 45 */
	132	{NULL, NULL, 0}, /* reserved vector 46 */
	133	{NULL, NULL, 0}, /* reserved vector 47 */
	134	/* vector 48: IRQ0 SExxR , Bit 0 */
	135	{&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 0},
	136	{NULL, NULL, 0}, /* reserved vector 49 */
	137	{NULL, NULL, 0}, /* reserved vector 50 */
	138	{NULL, NULL, 0}, /* reserved vector 51 */
	139	{NULL, NULL, 0}, /* reserved vector 52 */
	140	{NULL, NULL, 0}, /* reserved vector 53 */
	141	{NULL, NULL, 0}, /* reserved vector 54 */
	142	{NULL, NULL, 0}, /* reserved vector 55 */
	143	{NULL, NULL, 0}, /* reserved vector 56 */
	144	{NULL, NULL, 0}, /* reserved vector 57 */
	145	{NULL, NULL, 0}, /* reserved vector 58 */
	146	{NULL, NULL, 0}, /* reserved vector 59 */
	147	{NULL, NULL, 0}, /* reserved vector 60 */
	148	{NULL, NULL, 0}, /* reserved vector 61 */
	149	{NULL, NULL, 0}, /* reserved vector 62 */
	150	{NULL, NULL, 0}, /* reserved vector 63 */
	151	/* vector 64: RTC SEC SIxxR_L , Bit 0 */
	152	{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 0},
	153	/* vector 65: PIT SIxxR_L , Bit 1 */
	154	{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 1},
	155	/* vector 66: PCI1 SIxxR_L , Bit 2 */
	156	{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 2},
	157	/* vector 67: PCI2 SIxxR_L , Bit 3 */
	158	{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 3},
	159	/* vector 68: RTC ALR SIxxR_L , Bit 4 */
	160	{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 4},
	161	/* vector 69: MU SIxxR_L , Bit 5 */
	162	{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 5},
	163	/* vector 70: SBA SIxxR_L , Bit 6 */
	164	{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 6},
	165	/* vector 71: DMA SIxxR_L , Bit 7 */
	166	{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 7},
	167	/* vector 72: GTM4 SIxxR_L , Bit 8 */
	168	{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 8},
	169	/* vector 73: GTM8 SIxxR_L , Bit 9 */
	170	{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 9},
	171	/* vector 74: GPIO1 SIxxR_L , Bit 10 */
	172	{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 10},
	173	/* vector 75: GPIO2 SIxxR_L , Bit 11 */
	174	{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 11},
	175	/* vector 76: DDR SIxxR_L , Bit 12 */
	176	{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 12},
	177	/* vector 77: LBC SIxxR_L , Bit 13 */
	178	{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 13},
	179	/* vector 78: GTM2 SIxxR_L , Bit 14 */
	180	{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 14},
	181	/* vector 79: GTM6 SIxxR_L , Bit 15 */
	182	{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 15},
	183	/* vector 80: PMC SIxxR_L , Bit 16 */
	184	{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 16},
	185	{NULL, NULL, 0}, /* reserved vector 81 */
	186	{NULL, NULL, 0}, /* reserved vector 82 */
	187	{NULL, NULL, 0}, /* reserved vector 63 */
	188	/* vector 84: GTM3 SIxxR_L , Bit 20 */
	189	{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 20},
	190	/* vector 85: GTM7 SIxxR_L , Bit 21 */
	191	{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 21},
	192	{NULL, NULL, 0}, /* reserved vector 81 */
	193	{NULL, NULL, 0}, /* reserved vector 82 */
	194	{NULL, NULL, 0}, /* reserved vector 63 */
	195	{NULL, NULL, 0}, /* reserved vector 63 */
	196	/* vector 90: GTM1 SIxxR_L , Bit 26 */
	197	{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 26},
	198	/* vector 91: GTM5 SIxxR_L , Bit 27 */
	199	{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 27}
	200	};
	201
	202	static const uint8_t mpc83xx_ipic_mask_position_table [MPC83XX_IPIC_VECTOR_NUMBER] = {
	203	MPC83XX_IPIC_INVALID_MASK_POSITION,
	204	MPC83XX_IPIC_INVALID_MASK_POSITION,
	205	MPC83XX_IPIC_INVALID_MASK_POSITION,
	206	MPC83XX_IPIC_INVALID_MASK_POSITION,
	207	MPC83XX_IPIC_INVALID_MASK_POSITION,
	208	MPC83XX_IPIC_INVALID_MASK_POSITION,
	209	MPC83XX_IPIC_INVALID_MASK_POSITION,
	210	MPC83XX_IPIC_INVALID_MASK_POSITION,
	211	MPC83XX_IPIC_INVALID_MASK_POSITION,
	212	7,
	213	6,
	214	5,
	215	MPC83XX_IPIC_INVALID_MASK_POSITION,
	216	MPC83XX_IPIC_INVALID_MASK_POSITION,
	217	2,
	218	1,
	219	0,
	220	94,
	221	93,
	222	92,
	223	91,
	224	90,
	225	89,
	226	88,
	227	MPC83XX_IPIC_INVALID_MASK_POSITION,
	228	MPC83XX_IPIC_INVALID_MASK_POSITION,
	229	MPC83XX_IPIC_INVALID_MASK_POSITION,
	230	MPC83XX_IPIC_INVALID_MASK_POSITION,
	231	MPC83XX_IPIC_INVALID_MASK_POSITION,
	232	MPC83XX_IPIC_INVALID_MASK_POSITION,
	233	MPC83XX_IPIC_INVALID_MASK_POSITION,
	234	MPC83XX_IPIC_INVALID_MASK_POSITION,
	235	31,
	236	30,
	237	29,
	238	28,
	239	27,
	240	26,
	241	25,
	242	24,
	243	MPC83XX_IPIC_INVALID_MASK_POSITION,
	244	MPC83XX_IPIC_INVALID_MASK_POSITION,
	245	MPC83XX_IPIC_INVALID_MASK_POSITION,
	246	MPC83XX_IPIC_INVALID_MASK_POSITION,
	247	MPC83XX_IPIC_INVALID_MASK_POSITION,
	248	MPC83XX_IPIC_INVALID_MASK_POSITION,
	249	MPC83XX_IPIC_INVALID_MASK_POSITION,
	250	MPC83XX_IPIC_INVALID_MASK_POSITION,
	251	95,
	252	MPC83XX_IPIC_INVALID_MASK_POSITION,
	253	MPC83XX_IPIC_INVALID_MASK_POSITION,
	254	MPC83XX_IPIC_INVALID_MASK_POSITION,
	255	MPC83XX_IPIC_INVALID_MASK_POSITION,
	256	MPC83XX_IPIC_INVALID_MASK_POSITION,
	257	MPC83XX_IPIC_INVALID_MASK_POSITION,
	258	MPC83XX_IPIC_INVALID_MASK_POSITION,
	259	MPC83XX_IPIC_INVALID_MASK_POSITION,
	260	MPC83XX_IPIC_INVALID_MASK_POSITION,
	261	MPC83XX_IPIC_INVALID_MASK_POSITION,
	262	MPC83XX_IPIC_INVALID_MASK_POSITION,
	263	MPC83XX_IPIC_INVALID_MASK_POSITION,
	264	MPC83XX_IPIC_INVALID_MASK_POSITION,
	265	MPC83XX_IPIC_INVALID_MASK_POSITION,
	266	MPC83XX_IPIC_INVALID_MASK_POSITION,
	267	63,
	268	62,
	269	61,
	270	60,
	271	59,
	272	58,
	273	57,
	274	56,
	275	55,
	276	54,
	277	53,
	278	52,
	279	51,
	280	50,
	281	49,
	282	48,
	283	47,
	284	MPC83XX_IPIC_INVALID_MASK_POSITION,
	285	MPC83XX_IPIC_INVALID_MASK_POSITION,
	286	MPC83XX_IPIC_INVALID_MASK_POSITION,
	287	43,
	288	42,
	289	MPC83XX_IPIC_INVALID_MASK_POSITION,
	290	MPC83XX_IPIC_INVALID_MASK_POSITION,
	291	MPC83XX_IPIC_INVALID_MASK_POSITION,
	292	MPC83XX_IPIC_INVALID_MASK_POSITION,
	293	37,
	294	36
	295	};
	296
	297	/*
[ac7af4a]	298	* this array will be filled with mask values needed
[574fb67]	299	* to temporarily disable all IRQ soures with lower or same
	300	* priority of the current source (whose vector is the array index)
	301	*/
	302	static mpc83xx_ipic_mask_t mpc83xx_ipic_prio2mask [MPC83XX_IPIC_VECTOR_NUMBER];
	303
	304	rtems_status_code mpc83xx_ipic_set_mask( rtems_vector_number vector, rtems_vector_number mask_vector, bool mask)
	305	{
	306	uint8_t pos = 0;
	307	mpc83xx_ipic_mask_t *mask_entry;
	308	uint32_t *mask_reg;
	309	rtems_interrupt_level level;
	310
	311	/* Parameter check */
	312	if (!MPC83XX_IPIC_IS_VALID_VECTOR( vector) \|\| !MPC83XX_IPIC_IS_VALID_VECTOR( mask_vector)) {
	313	return RTEMS_INVALID_NUMBER;
	314	} else if (vector == mask_vector) {
	315	return RTEMS_RESOURCE_IN_USE;
	316	}
	317
	318	/* Position and mask entry */
	319	pos = mpc83xx_ipic_mask_position_table [mask_vector];
	320	mask_entry = &mpc83xx_ipic_prio2mask [vector];
	321
	322	/* Mask register and position */
	323	if (pos < 32) {
	324	mask_reg = &mask_entry->simsr_mask [0];
	325	} else if (pos < 64) {
	326	pos -= 32;
	327	mask_reg = &mask_entry->simsr_mask [1];
	328	} else if (pos < 96) {
	329	pos -= 64;
	330	mask_reg = &mask_entry->semsr_mask;
	331	} else if (pos < 128) {
	332	pos -= 96;
	333	mask_reg = &mask_entry->sermr_mask;
	334	} else {
	335	return RTEMS_NOT_IMPLEMENTED;
	336	}
	337
	338	/* Mask or unmask */
	339	if (mask) {
	340	rtems_interrupt_disable( level);
	341	*mask_reg &= ~(1 << pos);
	342	rtems_interrupt_enable( level);
	343	} else {
	344	rtems_interrupt_disable( level);
	345	*mask_reg \|= 1 << pos;
	346	rtems_interrupt_enable( level);
	347	}
	348
	349	return RTEMS_SUCCESSFUL;
	350	}
	351
	352	rtems_status_code mpc83xx_ipic_set_highest_priority_interrupt( rtems_vector_number vector, int type)
	353	{
	354	rtems_interrupt_level level;
	355	uint32_t reg = 0;
	356
	357	if (!MPC83XX_IPIC_IS_VALID_VECTOR( vector)) {
	358	return RTEMS_INVALID_NUMBER;
	359	} else if (type < 0 \|\| type > MPC83XX_IPIC_INTERRUPT_CRITICAL) {
	360	return RTEMS_INVALID_NUMBER;
	361	}
	362
	363	rtems_interrupt_disable( level);
	364	reg = mpc83xx.ipic.sicfr;
	365	mpc83xx.ipic.sicfr = (reg & ~0x7f000300) \| (vector << 24) \| (type << 8);
	366	rtems_interrupt_enable( level);
	367
	368	return RTEMS_SUCCESSFUL;
	369	}
	370
	371	/*
	372	* functions to enable/disable a source at the ipic
	373	*/
	374	rtems_status_code bsp_interrupt_vector_enable( rtems_vector_number irqnum)
	375	{
	376	rtems_vector_number vecnum = irqnum - BSP_IPIC_IRQ_LOWEST_OFFSET;
	377	const BSP_isrc_rsc_t *rsc_ptr;
	378
	379	if (MPC83XX_IPIC_IS_VALID_VECTOR( vecnum)) {
	380	rsc_ptr = &mpc83xx_ipic_isrc_rsc [vecnum];
	381	if (rsc_ptr->mask_reg != NULL) {
	382	*(rsc_ptr->mask_reg) \|= 1 << (31 - rsc_ptr->bit_num);
	383	}
	384	}
	385
	386	return RTEMS_SUCCESSFUL;
	387	}
	388
	389	rtems_status_code bsp_interrupt_vector_disable( rtems_vector_number irqnum)
	390	{
	391	rtems_vector_number vecnum = irqnum - BSP_IPIC_IRQ_LOWEST_OFFSET;
	392	const BSP_isrc_rsc_t *rsc_ptr;
	393
	394	if (MPC83XX_IPIC_IS_VALID_VECTOR( vecnum)) {
	395	rsc_ptr = &mpc83xx_ipic_isrc_rsc [vecnum];
	396	if (rsc_ptr->mask_reg != NULL) {
	397	*(rsc_ptr->mask_reg) &= ~(1 << (31 - rsc_ptr->bit_num));
	398	}
	399	}
	400
	401	return RTEMS_SUCCESSFUL;
	402	}
	403
	404
	405	/*
	406	* IRQ Handler: this is called from the primary exception dispatcher
	407	*/
	408	static int BSP_irq_handle_at_ipic( unsigned excNum)
	409	{
	410	int32_t vecnum;
	411	mpc83xx_ipic_mask_t mask_save;
	412	const mpc83xx_ipic_mask_t *mask_ptr;
[0cc8672]	413	uint32_t msr = 0;
[574fb67]	414	rtems_interrupt_level level;
	415
	416	/* Get vector number */
	417	switch (excNum) {
	418	case ASM_EXT_VECTOR:
	419	vecnum = MPC83xx_VCR_TO_VEC( mpc83xx.ipic.sivcr);
	420	break;
	421	case ASM_E300_SYSMGMT_VECTOR:
	422	vecnum = MPC83xx_VCR_TO_VEC( mpc83xx.ipic.smvcr);
	423	break;
	424	case ASM_E300_CRIT_VECTOR:
	425	vecnum = MPC83xx_VCR_TO_VEC( mpc83xx.ipic.scvcr);
	426	break;
	427	default:
	428	return 1;
	429	}
	430
	431	/*
	432	* Check the vector number, mask lower priority interrupts, enable
	433	* exceptions and dispatch the handler.
	434	*/
	435	if (MPC83XX_IPIC_IS_VALID_VECTOR( vecnum)) {
	436	mask_ptr = &mpc83xx_ipic_prio2mask [vecnum];
	437
	438	rtems_interrupt_disable( level);
	439
	440	/* Save current mask registers */
	441	mask_save.simsr_mask [0] = mpc83xx.ipic.simsr [0];
	442	mask_save.simsr_mask [1] = mpc83xx.ipic.simsr [1];
	443	mask_save.semsr_mask = mpc83xx.ipic.semsr;
	444	mask_save.sermr_mask = mpc83xx.ipic.sermr;
	445
	446	/* Mask all lower priority interrupts */
	447	mpc83xx.ipic.simsr [0] &= mask_ptr->simsr_mask [0];
	448	mpc83xx.ipic.simsr [1] &= mask_ptr->simsr_mask [1];
	449	mpc83xx.ipic.semsr &= mask_ptr->semsr_mask;
	450	mpc83xx.ipic.sermr &= mask_ptr->sermr_mask;
	451
	452	rtems_interrupt_enable( level);
	453
	454	/* Enable all interrupts */
	455	if (excNum != ASM_E300_CRIT_VECTOR) {
	456	msr = ppc_external_exceptions_enable();
	457	}
	458
	459	/* Dispatch interrupt handlers */
	460	bsp_interrupt_handler_dispatch( vecnum + BSP_IPIC_IRQ_LOWEST_OFFSET);
	461
	462	/* Restore machine state */
	463	if (excNum != ASM_E300_CRIT_VECTOR) {
	464	ppc_external_exceptions_disable( msr);
	465	}
	466
	467	/* Restore initial masks */
	468	rtems_interrupt_disable( level);
	469	mpc83xx.ipic.simsr [0] = mask_save.simsr_mask [0];
	470	mpc83xx.ipic.simsr [1] = mask_save.simsr_mask [1];
	471	mpc83xx.ipic.semsr = mask_save.semsr_mask;
	472	mpc83xx.ipic.sermr = mask_save.sermr_mask;
	473	rtems_interrupt_enable( level);
	474	} else {
	475	bsp_interrupt_handler_default( vecnum);
	476	}
	477
	478	return 0;
	479	}
	480
	481	/*
	482	* Fill the array mpc83xx_ipic_prio2mask to allow masking of lower prio sources
	483	* to implement nested interrupts.
	484	*/
	485	rtems_status_code mpc83xx_ipic_calc_prio2mask( void)
	486	{
	487	rtems_status_code rc = RTEMS_SUCCESSFUL;
	488
	489	/*
	490	* FIXME: fill the array
	491	*/
	492	return rc;
	493	}
	494
	495	/*
	496	* Activate the interrupt controller
	497	*/
	498	rtems_status_code mpc83xx_ipic_initialize( void)
	499	{
[ac7af4a]	500	/*
	501	* mask off all interrupts
[574fb67]	502	*/
	503	mpc83xx.ipic.simsr [0] = 0;
	504	mpc83xx.ipic.simsr [1] = 0;
	505	mpc83xx.ipic.semsr = 0;
	506	mpc83xx.ipic.sermr = 0;
	507	/*
	508	* set desired configuration as defined in bspopts.h
	509	* normally, the default values should be fine
	510	*/
	511	#if defined( BSP_SICFR_VAL) /* defined in bspopts.h ? */
	512	mpc83xx.ipic.sicfr = BSP_SICFR_VAL;
	513	#endif
	514
	515	/*
	516	* set desired priorities as defined in bspopts.h
	517	* normally, the default values should be fine
	518	*/
	519	#if defined( BSP_SIPRR0_VAL) /* defined in bspopts.h ? */
	520	mpc83xx.ipic.siprr [0] = BSP_SIPRR0_VAL;
	521	#endif
	522
	523	#if defined( BSP_SIPRR1_VAL) /* defined in bspopts.h ? */
	524	mpc83xx.ipic.siprr [1] = BSP_SIPRR1_VAL;
	525	#endif
	526
	527	#if defined( BSP_SIPRR2_VAL) /* defined in bspopts.h ? */
	528	mpc83xx.ipic.siprr [2] = BSP_SIPRR2_VAL;
	529	#endif
	530
	531	#if defined( BSP_SIPRR3_VAL) /* defined in bspopts.h ? */
	532	mpc83xx.ipic.siprr [3] = BSP_SIPRR3_VAL;
	533	#endif
	534
	535	#if defined( BSP_SMPRR0_VAL) /* defined in bspopts.h ? */
	536	mpc83xx.ipic.smprr [0] = BSP_SMPRR0_VAL;
	537	#endif
	538
	539	#if defined( BSP_SMPRR1_VAL) /* defined in bspopts.h ? */
	540	mpc83xx.ipic.smprr [1] = BSP_SMPRR1_VAL;
	541	#endif
	542
	543	#if defined( BSP_SECNR_VAL) /* defined in bspopts.h ? */
	544	mpc83xx.ipic.secnr = BSP_SECNR_VAL;
	545	#endif
	546
	547	/*
	548	* calculate priority masks
	549	*/
	550	return mpc83xx_ipic_calc_prio2mask();
	551	}
	552
	553	int mpc83xx_exception_handler( BSP_Exception_frame *frame, unsigned exception_number)
	554	{
	555	return BSP_irq_handle_at_ipic( exception_number);
	556	}
	557
	558	rtems_status_code bsp_interrupt_facility_initialize()
	559	{
	560	/* Install exception handler */
	561	if (ppc_exc_set_handler( ASM_EXT_VECTOR, mpc83xx_exception_handler)) {
	562	return RTEMS_IO_ERROR;
	563	}
	564	if (ppc_exc_set_handler( ASM_E300_SYSMGMT_VECTOR, mpc83xx_exception_handler)) {
	565	return RTEMS_IO_ERROR;
	566	}
	567	if (ppc_exc_set_handler( ASM_E300_CRIT_VECTOR, mpc83xx_exception_handler)) {
	568	return RTEMS_IO_ERROR;
	569	}
	570
	571	/* Initialize the interrupt controller */
	572	return mpc83xx_ipic_initialize();
	573	}
	574
	575	void bsp_interrupt_handler_default( rtems_vector_number vector)
	576	{
	577	printk( "Spurious interrupt: 0x%08x\n", vector);
	578	}

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