source: rtems/c/src/lib/libbsp/powerpc/gen83xx/include/irq.h @ e570c313

4.11
Last change on this file since e570c313 was e570c313, checked in by Joel Sherrill <joel.sherrill@…>, on Jan 24, 2011 at 3:32:04 PM

2011-01-24 Joel Sherrill <joel.sherrill@…>

  • configure.ac, console/console-config.c, i2c/i2c_init.c, include/bsp.h, include/hwreg_vals.h, include/irq.h, include/tm27.h, include/tsec-config.h, irq/irq.c, network/network.c, spi/spi_init.c, startup/bspstart.c: Address some of the issues spotted by the check_bsp script.
  • Property mode set to 100644
File size: 6.3 KB
Line 
1/*===============================================================*\
2| Project: RTEMS generic MPC83xx BSP                              |
3+-----------------------------------------------------------------+
4|                    Copyright (c) 2007, 2010                     |
5|                    Embedded Brains GmbH                         |
6|                    Obere Lagerstr. 30                           |
7|                    D-82178 Puchheim                             |
8|                    Germany                                      |
9|                    rtems@embedded-brains.de                     |
10+-----------------------------------------------------------------+
11| The license and distribution terms for this file may be         |
12| found in the file LICENSE in this distribution or at            |
13|                                                                 |
14| http://www.rtems.com/license/LICENSE.                           |
15|                                                                 |
16+-----------------------------------------------------------------+
17| this file declares constants of the interrupt controller        |
18\*===============================================================*/
19
20/*
21 *  $Id$
22 */
23
24#ifndef GEN83xx_IRQ_IRQ_H
25#define GEN83xx_IRQ_IRQ_H
26
27#include <stdbool.h>
28
29#include <rtems.h>
30#include <rtems/irq.h>
31#include <rtems/irq-extension.h>
32
33/*
34 * the following definitions specify the indices used
35 * to interface the interrupt handler API
36 */
37
38/*
39 * Peripheral IRQ handlers related definitions
40 */
41#define BSP_IPIC_PER_IRQ_NUMBER         128
42#define BSP_IPIC_IRQ_LOWEST_OFFSET        0
43#define BSP_IPIC_IRQ_MAX_OFFSET      (BSP_IPIC_IRQ_LOWEST_OFFSET\
44                                         +BSP_IPIC_PER_IRQ_NUMBER-1)
45
46#define BSP_IS_IPIC_IRQ(irqnum)                         \
47          (((irqnum) >= BSP_IPIC_IRQ_LOWEST_OFFSET) &&  \
48           ((irqnum) <= BSP_IPIC_IRQ_MAX_OFFSET))
49/*
50 * Processor IRQ handlers related definitions
51 */
52#define BSP_PROCESSOR_IRQ_NUMBER        1
53#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_IPIC_IRQ_MAX_OFFSET+1)
54#define BSP_PROCESSOR_IRQ_MAX_OFFSET    (BSP_PROCESSOR_IRQ_LOWEST_OFFSET\
55                                         +BSP_PROCESSOR_IRQ_NUMBER-1)
56
57#define BSP_IS_PROCESSOR_IRQ(irqnum)                            \
58          (((irqnum) >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET) &&     \
59           ((irqnum) <= BSP_PROCESSOR_IRQ_MAX_OFFSET))
60/*
61 * Summary
62 */
63#define BSP_IRQ_NUMBER                  (BSP_PROCESSOR_IRQ_MAX_OFFSET+1)
64#define BSP_LOWEST_OFFSET               BSP_IPIC_IRQ_LOWEST_OFFSET
65#define BSP_MAX_OFFSET                  BSP_PROCESSOR_IRQ_MAX_OFFSET
66
67#define BSP_IS_VALID_IRQ(irqnum)        \
68          (BSP_IS_PROCESSOR_IRQ(irqnum) \
69           || BSP_IS_IPIC_IRQ(irqnum))
70
71#ifndef ASM
72#ifdef __cplusplus
73extern "C" {
74#endif
75
76/*
77 * index table for the module specific handlers, a few entries are only placeholders
78 */
79  typedef enum {
80    BSP_IPIC_IRQ_FIRST     = BSP_IPIC_IRQ_LOWEST_OFFSET,
81    BSP_IPIC_IRQ_ERROR     = BSP_IPIC_IRQ_LOWEST_OFFSET +  0,
82    /* reserved irqs  1- 8 */
83    BSP_IPIC_IRQ_UART1     = BSP_IPIC_IRQ_LOWEST_OFFSET +  9,
84    BSP_IPIC_IRQ_UART2     = BSP_IPIC_IRQ_LOWEST_OFFSET + 10,
85    BSP_IPIC_IRQ_SEC       = BSP_IPIC_IRQ_LOWEST_OFFSET + 11,
86    /* reserved irqs 12-13 */
87    BSP_IPIC_IRQ_I2C1      = BSP_IPIC_IRQ_LOWEST_OFFSET + 14,
88    BSP_IPIC_IRQ_I2C2      = BSP_IPIC_IRQ_LOWEST_OFFSET + 15,
89    BSP_IPIC_IRQ_SPI       = BSP_IPIC_IRQ_LOWEST_OFFSET + 16,
90    BSP_IPIC_IRQ_IRQ1      = BSP_IPIC_IRQ_LOWEST_OFFSET + 17,
91    BSP_IPIC_IRQ_IRQ2      = BSP_IPIC_IRQ_LOWEST_OFFSET + 18,
92    BSP_IPIC_IRQ_IRQ3      = BSP_IPIC_IRQ_LOWEST_OFFSET + 19,
93    BSP_IPIC_IRQ_IRQ4      = BSP_IPIC_IRQ_LOWEST_OFFSET + 20,
94    BSP_IPIC_IRQ_IRQ5      = BSP_IPIC_IRQ_LOWEST_OFFSET + 21,
95    BSP_IPIC_IRQ_IRQ6      = BSP_IPIC_IRQ_LOWEST_OFFSET + 22,
96    BSP_IPIC_IRQ_IRQ7      = BSP_IPIC_IRQ_LOWEST_OFFSET + 23,
97    /* reserved irqs 24-31 */
98    BSP_IPIC_IRQ_TSEC1_TX  = BSP_IPIC_IRQ_LOWEST_OFFSET + 32,
99    BSP_IPIC_IRQ_TSEC1_RX  = BSP_IPIC_IRQ_LOWEST_OFFSET + 33,
100    BSP_IPIC_IRQ_TSEC1_ERR = BSP_IPIC_IRQ_LOWEST_OFFSET + 34,
101    BSP_IPIC_IRQ_TSEC2_TX  = BSP_IPIC_IRQ_LOWEST_OFFSET + 35,
102    BSP_IPIC_IRQ_TSEC2_RX  = BSP_IPIC_IRQ_LOWEST_OFFSET + 36,
103    BSP_IPIC_IRQ_TSEC2_ERR = BSP_IPIC_IRQ_LOWEST_OFFSET + 37,
104    BSP_IPIC_IRQ_USB_DR    = BSP_IPIC_IRQ_LOWEST_OFFSET + 38,
105    BSP_IPIC_IRQ_USB_MPH   = BSP_IPIC_IRQ_LOWEST_OFFSET + 39,
106    /* reserved irqs 40-47 */
107    BSP_IPIC_IRQ_IRQ0      = BSP_IPIC_IRQ_LOWEST_OFFSET + 48,
108    /* reserved irqs 49-63 */
109    BSP_IPIC_IRQ_RTC_SEC   = BSP_IPIC_IRQ_LOWEST_OFFSET + 64,
110    BSP_IPIC_IRQ_PIT       = BSP_IPIC_IRQ_LOWEST_OFFSET + 65,
111    BSP_IPIC_IRQ_PCI1      = BSP_IPIC_IRQ_LOWEST_OFFSET + 66,
112    BSP_IPIC_IRQ_PCI2      = BSP_IPIC_IRQ_LOWEST_OFFSET + 67,
113    BSP_IPIC_IRQ_RTC_ALR   = BSP_IPIC_IRQ_LOWEST_OFFSET + 68,
114    BSP_IPIC_IRQ_MU        = BSP_IPIC_IRQ_LOWEST_OFFSET + 69,
115    BSP_IPIC_IRQ_SBA       = BSP_IPIC_IRQ_LOWEST_OFFSET + 70,
116    BSP_IPIC_IRQ_DMA       = BSP_IPIC_IRQ_LOWEST_OFFSET + 71,
117    BSP_IPIC_IRQ_GTM4      = BSP_IPIC_IRQ_LOWEST_OFFSET + 72,
118    BSP_IPIC_IRQ_GTM8      = BSP_IPIC_IRQ_LOWEST_OFFSET + 73,
119    BSP_IPIC_IRQ_GPIO1     = BSP_IPIC_IRQ_LOWEST_OFFSET + 74,
120    BSP_IPIC_IRQ_GPIO2     = BSP_IPIC_IRQ_LOWEST_OFFSET + 75,
121    BSP_IPIC_IRQ_DDR       = BSP_IPIC_IRQ_LOWEST_OFFSET + 76,
122    BSP_IPIC_IRQ_LBC       = BSP_IPIC_IRQ_LOWEST_OFFSET + 77,
123    BSP_IPIC_IRQ_GTM2      = BSP_IPIC_IRQ_LOWEST_OFFSET + 78,
124    BSP_IPIC_IRQ_GTM6      = BSP_IPIC_IRQ_LOWEST_OFFSET + 79,
125    BSP_IPIC_IRQ_PMC       = BSP_IPIC_IRQ_LOWEST_OFFSET + 80,
126    /* reserved irqs 81-83 */
127    BSP_IPIC_IRQ_GTM3      = BSP_IPIC_IRQ_LOWEST_OFFSET + 84,
128    BSP_IPIC_IRQ_GTM7      = BSP_IPIC_IRQ_LOWEST_OFFSET + 85,
129    /* reserved irqs 86-89 */
130    BSP_IPIC_IRQ_GTM1      = BSP_IPIC_IRQ_LOWEST_OFFSET + 90,
131    BSP_IPIC_IRQ_GTM5      = BSP_IPIC_IRQ_LOWEST_OFFSET + 91,
132    /* reserved irqs 92-127 */
133
134    BSP_IPIC_IRQ_LAST     = BSP_IPIC_IRQ_MAX_OFFSET,
135  } rtems_irq_symbolic_name;
136
137#define BSP_INTERRUPT_VECTOR_MIN BSP_LOWEST_OFFSET
138
139#define BSP_INTERRUPT_VECTOR_MAX BSP_MAX_OFFSET
140
141rtems_status_code mpc83xx_ipic_set_mask( rtems_vector_number vector, rtems_vector_number mask_vector, bool mask);
142
143#define MPC83XX_IPIC_INTERRUPT_NORMAL 0
144
145#define MPC83XX_IPIC_INTERRUPT_SYSTEM 1
146
147#define MPC83XX_IPIC_INTERRUPT_CRITICAL 2
148
149rtems_status_code mpc83xx_ipic_set_highest_priority_interrupt( rtems_vector_number vector, int type);
150
151#ifdef __cplusplus
152}
153#endif
154#endif /* ASM */
155
156#endif /* GEN83XX_IRQ_IRQ_H */
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