source: rtems/c/src/lib/libbsp/powerpc/gen83xx/include/irq.h @ 1202742

4.104.115
Last change on this file since 1202742 was ac7af4a, checked in by Ralf Corsepius <ralf.corsepius@…>, on 11/30/09 at 04:37:44

Whitespace removal.
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File size: 6.2 KB
Line 
1/*===============================================================*\
2| Project: RTEMS generic MPC83xx BSP                              |
3+-----------------------------------------------------------------+
4|                    Copyright (c) 2007                           |
5|                    Embedded Brains GmbH                         |
6|                    Obere Lagerstr. 30                           |
7|                    D-82178 Puchheim                             |
8|                    Germany                                      |
9|                    rtems@embedded-brains.de                     |
10+-----------------------------------------------------------------+
11| The license and distribution terms for this file may be         |
12| found in the file LICENSE in this distribution or at            |
13|                                                                 |
14| http://www.rtems.com/license/LICENSE.                           |
15|                                                                 |
16+-----------------------------------------------------------------+
17| this file declares constants of the interrupt controller        |
18\*===============================================================*/
19#ifndef GEN83xx_IRQ_IRQ_H
20#define GEN83xx_IRQ_IRQ_H
21
22#include <stdbool.h>
23
24#include <rtems.h>
25#include <rtems/irq.h>
26#include <rtems/irq-extension.h>
27
28/*
29 * the following definitions specify the indices used
30 * to interface the interrupt handler API
31 */
32
33/*
34 * Peripheral IRQ handlers related definitions
35 */
36#define BSP_IPIC_PER_IRQ_NUMBER         128
37#define BSP_IPIC_IRQ_LOWEST_OFFSET        0
38#define BSP_IPIC_IRQ_MAX_OFFSET      (BSP_IPIC_IRQ_LOWEST_OFFSET\
39                                         +BSP_IPIC_PER_IRQ_NUMBER-1)
40
41#define BSP_IS_IPIC_IRQ(irqnum)                         \
42          (((irqnum) >= BSP_IPIC_IRQ_LOWEST_OFFSET) &&  \
43           ((irqnum) <= BSP_IPIC_IRQ_MAX_OFFSET))
44/*
45 * Processor IRQ handlers related definitions
46 */
47#define BSP_PROCESSOR_IRQ_NUMBER        1
48#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_IPIC_IRQ_MAX_OFFSET+1)
49#define BSP_PROCESSOR_IRQ_MAX_OFFSET    (BSP_PROCESSOR_IRQ_LOWEST_OFFSET\
50                                         +BSP_PROCESSOR_IRQ_NUMBER-1)
51
52#define BSP_IS_PROCESSOR_IRQ(irqnum)                            \
53          (((irqnum) >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET) &&     \
54           ((irqnum) <= BSP_PROCESSOR_IRQ_MAX_OFFSET))
55/*
56 * Summary
57 */
58#define BSP_IRQ_NUMBER                  (BSP_PROCESSOR_IRQ_MAX_OFFSET+1)
59#define BSP_LOWEST_OFFSET               BSP_IPIC_IRQ_LOWEST_OFFSET
60#define BSP_MAX_OFFSET                  BSP_PROCESSOR_IRQ_MAX_OFFSET
61
62#define BSP_IS_VALID_IRQ(irqnum)        \
63          (BSP_IS_PROCESSOR_IRQ(irqnum) \
64           || BSP_IS_IPIC_IRQ(irqnum))
65
66#ifndef ASM
67#ifdef __cplusplus
68extern "C" {
69#endif
70
71/*
72 * index table for the module specific handlers, a few entries are only placeholders
73 */
74  typedef enum {
75    BSP_IPIC_IRQ_FIRST     = BSP_IPIC_IRQ_LOWEST_OFFSET,
76    BSP_IPIC_IRQ_ERROR     = BSP_IPIC_IRQ_LOWEST_OFFSET +  0,
77    /* reserved irqs  1- 8 */
78    BSP_IPIC_IRQ_UART1     = BSP_IPIC_IRQ_LOWEST_OFFSET +  9,
79    BSP_IPIC_IRQ_UART2     = BSP_IPIC_IRQ_LOWEST_OFFSET + 10,
80    BSP_IPIC_IRQ_SEC       = BSP_IPIC_IRQ_LOWEST_OFFSET + 11,
81    /* reserved irqs 12-13 */
82    BSP_IPIC_IRQ_I2C1      = BSP_IPIC_IRQ_LOWEST_OFFSET + 14,
83    BSP_IPIC_IRQ_I2C2      = BSP_IPIC_IRQ_LOWEST_OFFSET + 15,
84    BSP_IPIC_IRQ_SPI       = BSP_IPIC_IRQ_LOWEST_OFFSET + 16,
85    BSP_IPIC_IRQ_IRQ1      = BSP_IPIC_IRQ_LOWEST_OFFSET + 17,
86    BSP_IPIC_IRQ_IRQ2      = BSP_IPIC_IRQ_LOWEST_OFFSET + 18,
87    BSP_IPIC_IRQ_IRQ3      = BSP_IPIC_IRQ_LOWEST_OFFSET + 19,
88    BSP_IPIC_IRQ_IRQ4      = BSP_IPIC_IRQ_LOWEST_OFFSET + 20,
89    BSP_IPIC_IRQ_IRQ5      = BSP_IPIC_IRQ_LOWEST_OFFSET + 21,
90    BSP_IPIC_IRQ_IRQ6      = BSP_IPIC_IRQ_LOWEST_OFFSET + 22,
91    BSP_IPIC_IRQ_IRQ7      = BSP_IPIC_IRQ_LOWEST_OFFSET + 23,
92    /* reserved irqs 24-31 */
93    BSP_IPIC_IRQ_TSEC1_TX  = BSP_IPIC_IRQ_LOWEST_OFFSET + 32,
94    BSP_IPIC_IRQ_TSEC1_RX  = BSP_IPIC_IRQ_LOWEST_OFFSET + 33,
95    BSP_IPIC_IRQ_TSEC1_ERR = BSP_IPIC_IRQ_LOWEST_OFFSET + 34,
96    BSP_IPIC_IRQ_TSEC2_TX  = BSP_IPIC_IRQ_LOWEST_OFFSET + 35,
97    BSP_IPIC_IRQ_TSEC2_RX  = BSP_IPIC_IRQ_LOWEST_OFFSET + 36,
98    BSP_IPIC_IRQ_TSEC2_ERR = BSP_IPIC_IRQ_LOWEST_OFFSET + 37,
99    BSP_IPIC_IRQ_USB_DR    = BSP_IPIC_IRQ_LOWEST_OFFSET + 38,
100    BSP_IPIC_IRQ_USB_MPH   = BSP_IPIC_IRQ_LOWEST_OFFSET + 39,
101    /* reserved irqs 40-47 */
102    BSP_IPIC_IRQ_IRQ0      = BSP_IPIC_IRQ_LOWEST_OFFSET + 48,
103    /* reserved irqs 49-63 */
104    BSP_IPIC_IRQ_RTC_SEC   = BSP_IPIC_IRQ_LOWEST_OFFSET + 64,
105    BSP_IPIC_IRQ_PIT       = BSP_IPIC_IRQ_LOWEST_OFFSET + 65,
106    BSP_IPIC_IRQ_PCI1      = BSP_IPIC_IRQ_LOWEST_OFFSET + 66,
107    BSP_IPIC_IRQ_PCI2      = BSP_IPIC_IRQ_LOWEST_OFFSET + 67,
108    BSP_IPIC_IRQ_RTC_ALR   = BSP_IPIC_IRQ_LOWEST_OFFSET + 68,
109    BSP_IPIC_IRQ_MU        = BSP_IPIC_IRQ_LOWEST_OFFSET + 69,
110    BSP_IPIC_IRQ_SBA       = BSP_IPIC_IRQ_LOWEST_OFFSET + 70,
111    BSP_IPIC_IRQ_DMA       = BSP_IPIC_IRQ_LOWEST_OFFSET + 71,
112    BSP_IPIC_IRQ_GTM4      = BSP_IPIC_IRQ_LOWEST_OFFSET + 72,
113    BSP_IPIC_IRQ_GTM8      = BSP_IPIC_IRQ_LOWEST_OFFSET + 73,
114    BSP_IPIC_IRQ_GPIO1     = BSP_IPIC_IRQ_LOWEST_OFFSET + 74,
115    BSP_IPIC_IRQ_GPIO2     = BSP_IPIC_IRQ_LOWEST_OFFSET + 75,
116    BSP_IPIC_IRQ_DDR       = BSP_IPIC_IRQ_LOWEST_OFFSET + 76,
117    BSP_IPIC_IRQ_LBC       = BSP_IPIC_IRQ_LOWEST_OFFSET + 77,
118    BSP_IPIC_IRQ_GTM2      = BSP_IPIC_IRQ_LOWEST_OFFSET + 78,
119    BSP_IPIC_IRQ_GTM6      = BSP_IPIC_IRQ_LOWEST_OFFSET + 79,
120    BSP_IPIC_IRQ_PMC       = BSP_IPIC_IRQ_LOWEST_OFFSET + 80,
121    /* reserved irqs 81-83 */
122    BSP_IPIC_IRQ_GTM3      = BSP_IPIC_IRQ_LOWEST_OFFSET + 84,
123    BSP_IPIC_IRQ_GTM7      = BSP_IPIC_IRQ_LOWEST_OFFSET + 85,
124    /* reserved irqs 86-89 */
125    BSP_IPIC_IRQ_GTM1      = BSP_IPIC_IRQ_LOWEST_OFFSET + 90,
126    BSP_IPIC_IRQ_GTM5      = BSP_IPIC_IRQ_LOWEST_OFFSET + 91,
127    /* reserved irqs 92-127 */
128
129    BSP_IPIC_IRQ_LAST     = BSP_IPIC_IRQ_MAX_OFFSET,
130  } rtems_irq_symbolic_name;
131
132rtems_status_code mpc83xx_ipic_set_mask( rtems_vector_number vector, rtems_vector_number mask_vector, bool mask);
133
134#define MPC83XX_IPIC_INTERRUPT_NORMAL 0
135
136#define MPC83XX_IPIC_INTERRUPT_SYSTEM 1
137
138#define MPC83XX_IPIC_INTERRUPT_CRITICAL 2
139
140rtems_status_code mpc83xx_ipic_set_highest_priority_interrupt( rtems_vector_number vector, int type);
141
142#ifdef __cplusplus
143}
144#endif
145#endif /* ASM */
146
147#endif /* GEN83XX_IRQ_IRQ_H */
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