source: rtems/c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h @ e570c313

4.11
Last change on this file since e570c313 was e570c313, checked in by Joel Sherrill <joel.sherrill@…>, on Jan 24, 2011 at 3:32:04 PM

2011-01-24 Joel Sherrill <joel.sherrill@…>

  • configure.ac, console/console-config.c, i2c/i2c_init.c, include/bsp.h, include/hwreg_vals.h, include/irq.h, include/tm27.h, include/tsec-config.h, irq/irq.c, network/network.c, spi/spi_init.c, startup/bspstart.c: Address some of the issues spotted by the check_bsp script.
  • Property mode set to 100644
File size: 7.6 KB
Line 
1/*===============================================================*\
2| Project: RTEMS generic MPC83xx BSP                              |
3+-----------------------------------------------------------------+
4|                    Copyright (c) 2007                           |
5|                    Embedded Brains GmbH                         |
6|                    Obere Lagerstr. 30                           |
7|                    D-82178 Puchheim                             |
8|                    Germany                                      |
9|                    rtems@embedded-brains.de                     |
10+-----------------------------------------------------------------+
11| The license and distribution terms for this file may be         |
12| found in the file LICENSE in this distribution or at            |
13|                                                                 |
14| http://www.rtems.com/license/LICENSE.                           |
15|                                                                 |
16+-----------------------------------------------------------------+
17| this file contains board specific definitions                   |
18\*===============================================================*/
19
20/*
21 *  $Id$
22 */
23
24#ifndef __GEN83xx_HWREG_VALS_h
25#define __GEN83xx_HWREG_VALS_h
26
27#include <mpc83xx/mpc83xx.h>
28#include <bsp.h>
29/*
30 * distinguish board characteristics
31 */
32#if defined(MPC8349EAMDS)
33/*
34 * for Freescale MPC8349 EAMDS
35 */
36/*
37 * two DUART channels supported
38 */
39#define GEN83xx_DUART_AVAIL_MASK 0x03
40
41/* we need the low level initialization in start.S*/
42#define NEED_LOW_LEVEL_INIT
43/*
44 * clocking infos
45 */
46#define BSP_CLKIN_FRQ 66000000L
47#define RCFG_SYSPLL_MF 4
48#define RCFG_COREPLL_MF 4
49
50/*
51 * Reset configuration words
52 */
53#define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 |    \
54                          RCWLR_DDRCM_1_1  |    \
55                          RCWLR_SPMF(RCFG_SYSPLL_MF)    |       \
56                          RCWLR_COREPLL(RCFG_COREPLL_MF))
57
58#define RESET_CONF_WRD_H (RCWHR_PCI_HOST     |  \
59                          RCWHR_PCI_32       |  \
60                          RCWHR_PCI1ARB_EN   |  \
61                          RCWHR_PCI2ARB_EN   |  \
62                          RCWHR_CORE_EN      |  \
63                          RCWHR_BMS_LOW      |  \
64                          RCWHR_BOOTSEQ_NONE |  \
65                          RCWHR_SW_DIS       |  \
66                          RCWHR_ROMLOC_LB16  |  \
67                          RCWHR_TSEC1M_GMII  |  \
68                          RCWHR_TSEC2M_GMII  |  \
69                          RCWHR_ENDIAN_BIG   |  \
70                          RCWHR_LALE_NORM    |  \
71                          RCWHR_LDP_PAR)
72#elif defined(HSC_CM01)
73/*
74 * for JPK HSC_CM01
75 */
76/*
77 * one DUART channel (UART1) supported
78 */
79#define GEN83xx_DUART_AVAIL_MASK 0x01
80
81/* we need the low level initialization in start.S*/
82#define NEED_LOW_LEVEL_INIT
83/*
84 * clocking infos
85 */
86#define BSP_CLKIN_FRQ 30000000L
87#define RCFG_SYSPLL_MF 11
88#define RCFG_COREPLL_MF 4
89/*
90 * Reset configuration words
91 */
92#define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 |    \
93                          RCWLR_DDRCM_1_1  |    \
94                          RCWLR_SPMF(RCFG_SYSPLL_MF)    |       \
95                          RCWLR_COREPLL(RCFG_COREPLL_MF))
96
97#define RESET_CONF_WRD_H (RCWHR_PCI_HOST     |  \
98                          RCWHR_PCI_32       |  \
99                          RCWHR_PCI1ARB_DIS  |  \
100                          RCWHR_PCI2ARB_DIS  |  \
101                          RCWHR_CORE_EN      |  \
102                          RCWHR_BMS_LOW      |  \
103                          RCWHR_BOOTSEQ_NONE |  \
104                          RCWHR_SW_DIS       |  \
105                          RCWHR_ROMLOC_LB16  |  \
106                          RCWHR_TSEC1M_RGMII |  \
107                          RCWHR_TSEC2M_GMII  |  \
108                          RCWHR_ENDIAN_BIG   |  \
109                          RCWHR_LALE_EARLY   |  \
110                          RCWHR_LDP_SPC)
111
112#elif defined( HAS_UBOOT)
113
114/* TODO */
115
116#else
117
118#error "board type not defined"
119
120#endif
121
122#if defined(MPC8349EAMDS)
123/**************************
124 * for Freescale MPC8349EAMDS
125 */
126
127/*
128 * working values for various registers, used in start/start.S
129 */
130
131/*
132 * Local Access Windows
133 * FIXME: decode bit settings
134 */
135#define LBLAWBAR0_VAL  0xFE000000
136#define LBLAWAR0_VAL   0x80000016
137#define LBLAWBAR1_VAL  0xF8000000
138#define LBLAWAR1_VAL   0x8000000E
139#define LBLAWBAR2_VAL  0xF0000000
140#define LBLAWAR2_VAL   0x80000019
141#define DDRLAWBAR0_VAL 0x00000000
142#define DDRLAWAR0_VAL  0x8000001B
143/*
144 * Local Bus (Memory) Controller
145 * FIXME: decode bit settings
146 */
147#define BR0_VAL 0xFE001001
148#define OR0_VAL 0xFF806FF7
149#define BR1_VAL 0xF8000801
150#define OR1_VAL 0xFFFFE8F0
151#define BR2_VAL 0xF0001861
152#define OR2_VAL 0xFC006901
153/*
154 * SDRAM registers
155 * FIXME: decode bit settings
156 */
157#define MRPTR_VAL 0x20000000
158#define LSRT_VAL  0x32000000
159#define LSDMR_VAL 0x4062D733
160#define LCRR_VAL  0x80000004
161
162/*
163 * DDR-SDRAM registers
164 * FIXME: decode bit settings
165 */
166#define CS2_BNDS_VAL                 0x00000007
167#define CS3_BNDS_VAL                 0x0008000F
168#define CS2_CONFIG_VAL               0x80000101
169#define CS3_CONFIG_VAL               0x80000101
170#define TIMING_CFG_1_VAL             0x36333321
171#define TIMING_CFG_2_VAL             0x00000800
172#define DDR_SDRAM_CFG_VAL            0xC2000000
173#define DDR_SDRAM_MODE_VAL           0x00000022
174#define DDR_SDRAM_INTTVL_VAL         0x045B0100
175#define DDR_SDRAM_CLK_CNTL_VAL       0x00000000
176
177#elif defined(HSC_CM01)
178/**************************
179 * for JPK HSC_CM01
180 */
181
182/* fpga BCSR register */
183#define FPGA_START 0xF8000000
184#define FPGA_SIZE  0x8000
185#define FPGA_END   (FPGA_START+FPGA_SIZE-1)
186
187/*
188 * working values for various registers, used in start/start.S
189 */
190
191/* fpga config 16 MB size */
192#define FPGA_CONFIG_START       0xF8000000
193#define FPGA_CONFIG_SIZE        0x01000000
194/* fpga register 8 MB size */
195#define FPGA_REGISTER_START     0xF9000000
196#define FPGA_REGISTER_SIZE      0x00800000
197/* fpga fifo 8 MB size */
198#define FPGA_FIFO_START         0xF9800000
199#define FPGA_FIFO_SIZE          0x00800000
200
201#define FPGA_START (FPGA_CONFIG_START)
202// fpga window size 32 MByte
203#define FPGA_SIZE  (0x02000000)
204#define FPGA_END   (FPGA_START+FPGA_SIZE-1)
205
206/*
207 * Local Access Windows
208 * FIXME: decode bit settings
209 */
210
211#define LBLAWBAR0_VAL  bsp_rom_start
212#define LBLAWAR0_VAL   0x80000018
213#define LBLAWBAR1_VAL  (FPGA_CONFIG_START)
214#define LBLAWAR1_VAL   0x80000018
215#define DDRLAWBAR0_VAL bsp_ram_start
216#define DDRLAWAR0_VAL  0x8000001B
217/*
218 * Local Bus (Memory) Controller
219 * FIXME: decode bit settings
220 */
221#define BR0_VAL (0xFE000000 | 0x01001)
222#define OR0_VAL 0xFE000E54
223// fpga config access range (UPM_A) (32 kByte)
224#define BR2_VAL (FPGA_CONFIG_START | 0x01881)
225#define OR2_VAL 0xFFFF9100
226
227// fpga register access range (UPM_B) (8 MByte)
228#define BR3_VAL (FPGA_REGISTER_START | 0x018A1)
229#define OR3_VAL 0xFF801100
230
231// fpga fifo access range (UPM_C) (8 MByte)
232#define BR4_VAL (FPGA_FIFO_START | 0x018C1)
233#define OR4_VAL 0xFF801100
234
235/*
236 * SDRAM registers
237 */
238#define MRPTR_VAL 0x20000000
239#define LSRT_VAL  0x32000000
240#define LSDMR_VAL 0x4062D733
241#define LCRR_VAL  0x80010004
242
243/*
244 * DDR-SDRAM registers
245 * FIXME: decode bit settings
246 */
247#define DDRCDR_VAL                   0x00000001
248#define CS0_BNDS_VAL                 0x0000000F
249#define CS0_CONFIG_VAL               0x80810102
250#define TIMING_CFG_0_VAL             0x00420802
251#define TIMING_CFG_1_VAL             0x3735A322
252#define TIMING_CFG_2_VAL             0x2F9044C7
253#define DDR_SDRAM_CFG_2_VAL          0x00401000
254#define DDR_SDRAM_MODE_VAL           0x44521632
255#define DDR_SDRAM_CLK_CNTL_VAL       0x01800000
256#define DDR_SDRAM_CFG_VAL            0x63000008
257
258#define DDR_ERR_DISABLE_VAL          0x0000008D
259#define DDR_ERR_DISABLE_VAL2         0x00000089
260#define DDR_SDRAM_DATA_INIT_VAL      0xC01DCAFE
261#define DDR_SDRAM_INIT_ADDR_VAL      0
262#define DDR_SDRAM_INTERVAL_VAL       0x05080000
263
264#elif defined( HAS_UBOOT)
265
266/* TODO */
267
268#else
269
270#error "board type not defined"
271
272#endif
273
274/**************************
275 * derived values for all boards
276 */
277/* value of input clock divider (derived from pll mode reg) */
278#define BSP_SYSPLL_CKID (((mpc83xx.clk.spmr>>(31-8))&0x01)+1)
279/* value of system pll (derived from pll mode reg) */
280#define BSP_SYSPLL_MF    ((mpc83xx.clk.spmr>>(31-7))&0x0f)
281/* value of system pll (derived from pll mode reg) */
282#define BSP_COREPLL_MF   ((mpc83xx.clk.spmr>>(31-15))&0x7f)
283
284#endif /* __GEN83xx_HWREG_VALS_h */
Note: See TracBrowser for help on using the repository browser.