source: rtems/c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h @ 9b4422a2

4.115
Last change on this file since 9b4422a2 was 9b4422a2, checked in by Joel Sherrill <joel.sherrill@…>, on 05/03/12 at 15:09:24

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1/*===============================================================*\
2| Project: RTEMS generic MPC83xx BSP                              |
3+-----------------------------------------------------------------+
4|                    Copyright (c) 2007                           |
5|                    Embedded Brains GmbH                         |
6|                    Obere Lagerstr. 30                           |
7|                    D-82178 Puchheim                             |
8|                    Germany                                      |
9|                    rtems@embedded-brains.de                     |
10+-----------------------------------------------------------------+
11| The license and distribution terms for this file may be         |
12| found in the file LICENSE in this distribution or at            |
13|                                                                 |
14| http://www.rtems.com/license/LICENSE.                           |
15|                                                                 |
16+-----------------------------------------------------------------+
17| this file contains board specific definitions                   |
18\*===============================================================*/
19
20
21#ifndef __GEN83xx_HWREG_VALS_h
22#define __GEN83xx_HWREG_VALS_h
23
24#include <mpc83xx/mpc83xx.h>
25#include <bsp.h>
26/*
27 * distinguish board characteristics
28 */
29#if defined(MPC83XX_BOARD_MPC8349EAMDS)
30/*
31 * for Freescale MPC8349 EAMDS
32 */
33/*
34 * two DUART channels supported
35 */
36#define GEN83xx_DUART_AVAIL_MASK 0x03
37
38/* we need the low level initialization in start.S*/
39#define NEED_LOW_LEVEL_INIT
40/*
41 * clocking infos
42 */
43#define BSP_CLKIN_FRQ 66000000L
44#define RCFG_SYSPLL_MF 4
45#define RCFG_COREPLL_MF 4
46
47/*
48 * Reset configuration words
49 */
50#define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 |    \
51                          RCWLR_DDRCM_1_1  |    \
52                          RCWLR_SPMF(RCFG_SYSPLL_MF)    |       \
53                          RCWLR_COREPLL(RCFG_COREPLL_MF))
54
55#define RESET_CONF_WRD_H (RCWHR_PCI_HOST     |  \
56                          RCWHR_PCI_32       |  \
57                          RCWHR_PCI1ARB_EN   |  \
58                          RCWHR_PCI2ARB_EN   |  \
59                          RCWHR_CORE_EN      |  \
60                          RCWHR_BMS_LOW      |  \
61                          RCWHR_BOOTSEQ_NONE |  \
62                          RCWHR_SW_DIS       |  \
63                          RCWHR_ROMLOC_LB16  |  \
64                          RCWHR_TSEC1M_GMII  |  \
65                          RCWHR_TSEC2M_GMII  |  \
66                          RCWHR_ENDIAN_BIG   |  \
67                          RCWHR_LALE_NORM    |  \
68                          RCWHR_LDP_PAR)
69#elif defined(MPC83XX_BOARD_HSC_CM01)
70/*
71 * for JPK HSC_CM01
72 */
73/*
74 * one DUART channel (UART1) supported
75 */
76#define GEN83xx_DUART_AVAIL_MASK 0x01
77
78/* we need the low level initialization in start.S*/
79#define NEED_LOW_LEVEL_INIT
80/*
81 * clocking infos
82 */
83#define BSP_CLKIN_FRQ 30000000L
84#define RCFG_SYSPLL_MF 11
85#define RCFG_COREPLL_MF 4
86/*
87 * Reset configuration words
88 */
89#define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 |    \
90                          RCWLR_DDRCM_1_1  |    \
91                          RCWLR_SPMF(RCFG_SYSPLL_MF)    |       \
92                          RCWLR_COREPLL(RCFG_COREPLL_MF))
93
94#define RESET_CONF_WRD_H (RCWHR_PCI_HOST     |  \
95                          RCWHR_PCI_32       |  \
96                          RCWHR_PCI1ARB_DIS  |  \
97                          RCWHR_PCI2ARB_DIS  |  \
98                          RCWHR_CORE_EN      |  \
99                          RCWHR_BMS_LOW      |  \
100                          RCWHR_BOOTSEQ_NONE |  \
101                          RCWHR_SW_DIS       |  \
102                          RCWHR_ROMLOC_LB16  |  \
103                          RCWHR_TSEC1M_RGMII |  \
104                          RCWHR_TSEC2M_GMII  |  \
105                          RCWHR_ENDIAN_BIG   |  \
106                          RCWHR_LALE_EARLY   |  \
107                          RCWHR_LDP_SPC)
108
109#elif defined( HAS_UBOOT)
110
111/* TODO */
112
113#else
114
115#error "board type not defined"
116
117#endif
118
119#if defined(MPC83XX_BOARD_MPC8349EAMDS)
120/**************************
121 * for Freescale MPC83XX_BOARD_MPC8349EAMDS
122 */
123
124/*
125 * working values for various registers, used in start/start.S
126 */
127
128/*
129 * Local Access Windows
130 * FIXME: decode bit settings
131 */
132#define LBLAWBAR0_VAL  0xFE000000
133#define LBLAWAR0_VAL   0x80000016
134#define LBLAWBAR1_VAL  0xF8000000
135#define LBLAWAR1_VAL   0x8000000E
136#define LBLAWBAR2_VAL  0xF0000000
137#define LBLAWAR2_VAL   0x80000019
138#define DDRLAWBAR0_VAL 0x00000000
139#define DDRLAWAR0_VAL  0x8000001B
140/*
141 * Local Bus (Memory) Controller
142 * FIXME: decode bit settings
143 */
144#define BR0_VAL 0xFE001001
145#define OR0_VAL 0xFF806FF7
146#define BR1_VAL 0xF8000801
147#define OR1_VAL 0xFFFFE8F0
148#define BR2_VAL 0xF0001861
149#define OR2_VAL 0xFC006901
150/*
151 * SDRAM registers
152 * FIXME: decode bit settings
153 */
154#define MRPTR_VAL 0x20000000
155#define LSRT_VAL  0x32000000
156#define LSDMR_VAL 0x4062D733
157#define LCRR_VAL  0x80000004
158
159/*
160 * DDR-SDRAM registers
161 * FIXME: decode bit settings
162 */
163#define CS2_BNDS_VAL                 0x00000007
164#define CS3_BNDS_VAL                 0x0008000F
165#define CS2_CONFIG_VAL               0x80000101
166#define CS3_CONFIG_VAL               0x80000101
167#define TIMING_CFG_1_VAL             0x36333321
168#define TIMING_CFG_2_VAL             0x00000800
169#define DDR_SDRAM_CFG_VAL            0xC2000000
170#define DDR_SDRAM_MODE_VAL           0x00000022
171#define DDR_SDRAM_INTTVL_VAL         0x045B0100
172#define DDR_SDRAM_CLK_CNTL_VAL       0x00000000
173
174#elif defined(MPC83XX_BOARD_HSC_CM01)
175/**************************
176 * for JPK HSC_CM01
177 */
178
179/* fpga BCSR register */
180#define FPGA_START 0xF8000000
181#define FPGA_SIZE  0x8000
182#define FPGA_END   (FPGA_START+FPGA_SIZE-1)
183
184/*
185 * working values for various registers, used in start/start.S
186 */
187
188/* fpga config 16 MB size */
189#define FPGA_CONFIG_START       0xF8000000
190#define FPGA_CONFIG_SIZE        0x01000000
191/* fpga register 8 MB size */
192#define FPGA_REGISTER_START     0xF9000000
193#define FPGA_REGISTER_SIZE      0x00800000
194/* fpga fifo 8 MB size */
195#define FPGA_FIFO_START         0xF9800000
196#define FPGA_FIFO_SIZE          0x00800000
197
198#define FPGA_START (FPGA_CONFIG_START)
199// fpga window size 32 MByte
200#define FPGA_SIZE  (0x02000000)
201#define FPGA_END   (FPGA_START+FPGA_SIZE-1)
202
203/*
204 * Local Access Windows
205 * FIXME: decode bit settings
206 */
207
208#define LBLAWBAR0_VAL  bsp_rom_start
209#define LBLAWAR0_VAL   0x80000018
210#define LBLAWBAR1_VAL  (FPGA_CONFIG_START)
211#define LBLAWAR1_VAL   0x80000018
212#define DDRLAWBAR0_VAL bsp_ram_start
213#define DDRLAWAR0_VAL  0x8000001B
214/*
215 * Local Bus (Memory) Controller
216 * FIXME: decode bit settings
217 */
218#define BR0_VAL (0xFE000000 | 0x01001)
219#define OR0_VAL 0xFE000E54
220// fpga config access range (UPM_A) (32 kByte)
221#define BR2_VAL (FPGA_CONFIG_START | 0x01881)
222#define OR2_VAL 0xFFFF9100
223
224// fpga register access range (UPM_B) (8 MByte)
225#define BR3_VAL (FPGA_REGISTER_START | 0x018A1)
226#define OR3_VAL 0xFF801100
227
228// fpga fifo access range (UPM_C) (8 MByte)
229#define BR4_VAL (FPGA_FIFO_START | 0x018C1)
230#define OR4_VAL 0xFF801100
231
232/*
233 * SDRAM registers
234 */
235#define MRPTR_VAL 0x20000000
236#define LSRT_VAL  0x32000000
237#define LSDMR_VAL 0x4062D733
238#define LCRR_VAL  0x80010004
239
240/*
241 * DDR-SDRAM registers
242 * FIXME: decode bit settings
243 */
244#define DDRCDR_VAL                   0x00000001
245#define CS0_BNDS_VAL                 0x0000000F
246#define CS0_CONFIG_VAL               0x80810102
247#define TIMING_CFG_0_VAL             0x00420802
248#define TIMING_CFG_1_VAL             0x3735A322
249#define TIMING_CFG_2_VAL             0x2F9044C7
250#define DDR_SDRAM_CFG_2_VAL          0x00401000
251#define DDR_SDRAM_MODE_VAL           0x44521632
252#define DDR_SDRAM_CLK_CNTL_VAL       0x01800000
253#define DDR_SDRAM_CFG_VAL            0x63000008
254
255#define DDR_ERR_DISABLE_VAL          0x0000008D
256#define DDR_ERR_DISABLE_VAL2         0x00000089
257#define DDR_SDRAM_DATA_INIT_VAL      0xC01DCAFE
258#define DDR_SDRAM_INIT_ADDR_VAL      0
259#define DDR_SDRAM_INTERVAL_VAL       0x05080000
260
261#elif defined( HAS_UBOOT)
262
263/* TODO */
264
265#else
266
267#error "board type not defined"
268
269#endif
270
271/**************************
272 * derived values for all boards
273 */
274/* value of input clock divider (derived from pll mode reg) */
275#define BSP_SYSPLL_CKID (((mpc83xx.clk.spmr>>(31-8))&0x01)+1)
276/* value of system pll (derived from pll mode reg) */
277#define BSP_SYSPLL_MF    ((mpc83xx.clk.spmr>>(31-7))&0x0f)
278/* value of system pll (derived from pll mode reg) */
279#define BSP_COREPLL_MF   ((mpc83xx.clk.spmr>>(31-15))&0x7f)
280
281#endif /* __GEN83xx_HWREG_VALS_h */
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