source: rtems/c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h @ 4b23c94

4.104.114.95
Last change on this file since 4b23c94 was 4b23c94, checked in by Thomas Doerfler <Thomas.Doerfler@…>, on 08/26/08 at 11:55:31

various changes to gen83xx BSP and others
  • Property mode set to 100644
File size: 7.6 KB
Line 
1/*===============================================================*\
2| Project: RTEMS generic MPC83xx BSP                              |
3+-----------------------------------------------------------------+
4|                    Copyright (c) 2007                           |
5|                    Embedded Brains GmbH                         |
6|                    Obere Lagerstr. 30                           |
7|                    D-82178 Puchheim                             |
8|                    Germany                                      |
9|                    rtems@embedded-brains.de                     |
10+-----------------------------------------------------------------+
11| The license and distribution terms for this file may be         |
12| found in the file LICENSE in this distribution or at            |
13|                                                                 |
14| http://www.rtems.com/license/LICENSE.                           |
15|                                                                 |
16+-----------------------------------------------------------------+
17| this file contains board specific definitions                   |
18\*===============================================================*/
19
20#ifndef __GEN83xx_HWREG_VALS_h
21#define __GEN83xx_HWREG_VALS_h
22
23#include <mpc83xx/mpc83xx.h>
24#include <bsp.h>
25/*
26 * distinguish board characteristics
27 */
28#if defined(MPC8349EAMDS)
29/*
30 * for Freescale MPC8349 EAMDS
31 */
32/*
33 * two DUART channels supported
34 */
35#define GEN83xx_DUART_AVAIL_MASK 0x03
36
37/* we need the low level initialization in start.S*/
38#define NEED_LOW_LEVEL_INIT
39/*
40 * clocking infos
41 */
42#define BSP_CLKIN_FRQ 66000000L
43#define RCFG_SYSPLL_MF 4
44#define RCFG_COREPLL_MF 4
45
46/*
47 * Reset configuration words
48 */
49#define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 |    \
50                          RCWLR_DDRCM_1_1  |    \
51                          RCWLR_SPMF(RCFG_SYSPLL_MF)    |       \
52                          RCWLR_COREPLL(RCFG_COREPLL_MF))
53
54#define RESET_CONF_WRD_H (RCWHR_PCI_HOST     |  \
55                          RCWHR_PCI_32       |  \
56                          RCWHR_PCI1ARB_EN   |  \
57                          RCWHR_PCI2ARB_EN   |  \
58                          RCWHR_CORE_EN      |  \
59                          RCWHR_BMS_LOW      |  \
60                          RCWHR_BOOTSEQ_NONE |  \
61                          RCWHR_SW_DIS       |  \
62                          RCWHR_ROMLOC_LB16  |  \
63                          RCWHR_TSEC1M_GMII  |  \
64                          RCWHR_TSEC2M_GMII  |  \
65                          RCWHR_ENDIAN_BIG   |  \
66                          RCWHR_LALE_NORM    |  \
67                          RCWHR_LDP_PAR)
68#elif defined(HSC_CM01)
69/*
70 * for JPK HSC_CM01
71 */
72/*
73 * one DUART channel (UART1) supported
74 */
75#define GEN83xx_DUART_AVAIL_MASK 0x01
76
77/* we need the low level initialization in start.S*/
78#define NEED_LOW_LEVEL_INIT
79/*
80 * clocking infos
81 */
82#define BSP_CLKIN_FRQ 30000000L
83#define RCFG_SYSPLL_MF 11
84#define RCFG_COREPLL_MF 4
85/*
86 * Reset configuration words
87 */
88#define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 |    \
89                          RCWLR_DDRCM_1_1  |    \
90                          RCWLR_SPMF(RCFG_SYSPLL_MF)    |       \
91                          RCWLR_COREPLL(RCFG_COREPLL_MF))
92
93#define RESET_CONF_WRD_H (RCWHR_PCI_HOST     |  \
94                          RCWHR_PCI_32       |  \
95                          RCWHR_PCI1ARB_DIS  |  \
96                          RCWHR_PCI2ARB_DIS  |  \
97                          RCWHR_CORE_EN      |  \
98                          RCWHR_BMS_LOW      |  \
99                          RCWHR_BOOTSEQ_NONE |  \
100                          RCWHR_SW_DIS       |  \
101                          RCWHR_ROMLOC_LB16  |  \
102                          RCWHR_TSEC1M_RGMII |  \
103                          RCWHR_TSEC2M_GMII  |  \
104                          RCWHR_ENDIAN_BIG   |  \
105                          RCWHR_LALE_EARLY   |  \
106                          RCWHR_LDP_SPC)
107
108#elif defined( HAS_UBOOT)
109
110/* TODO */
111
112#else
113
114#error "board type not defined"
115
116#endif
117
118#if defined(MPC8349EAMDS)
119/**************************
120 * for Freescale MPC8349EAMDS
121 */
122
123/*
124 * working values for various registers, used in start/start.S
125 */
126
127/*
128 * Local Access Windows
129 * FIXME: decode bit settings
130 */
131#define LBLAWBAR0_VAL  0xFE000000
132#define LBLAWAR0_VAL   0x80000016
133#define LBLAWBAR1_VAL  0xF8000000
134#define LBLAWAR1_VAL   0x8000000E
135#define LBLAWBAR2_VAL  0xF0000000
136#define LBLAWAR2_VAL   0x80000019
137#define DDRLAWBAR0_VAL 0x00000000
138#define DDRLAWAR0_VAL  0x8000001B
139/*
140 * Local Bus (Memory) Controller
141 * FIXME: decode bit settings
142 */
143#define BR0_VAL 0xFE001001
144#define OR0_VAL 0xFF806FF7
145#define BR1_VAL 0xF8000801
146#define OR1_VAL 0xFFFFE8F0
147#define BR2_VAL 0xF0001861
148#define OR2_VAL 0xFC006901
149/*
150 * SDRAM registers
151 * FIXME: decode bit settings
152 */
153#define MRPTR_VAL 0x20000000
154#define LSRT_VAL  0x32000000
155#define LSDMR_VAL 0x4062D733
156#define LCRR_VAL  0x80000004
157
158/*
159 * DDR-SDRAM registers
160 * FIXME: decode bit settings
161 */
162#define CS2_BNDS_VAL                 0x00000007
163#define CS3_BNDS_VAL                 0x0008000F
164#define CS2_CONFIG_VAL               0x80000101
165#define CS3_CONFIG_VAL               0x80000101
166#define TIMING_CFG_1_VAL             0x36333321
167#define TIMING_CFG_2_VAL             0x00000800
168#define DDR_SDRAM_CFG_VAL            0xC2000000
169#define DDR_SDRAM_MODE_VAL           0x00000022
170#define DDR_SDRAM_INTTVL_VAL         0x045B0100
171#define DDR_SDRAM_CLK_CNTL_VAL       0x00000000
172
173#elif defined(HSC_CM01)
174/**************************
175 * for JPK HSC_CM01
176 */
177
178/* fpga BCSR register */
179#define FPGA_START 0xF8000000
180#define FPGA_SIZE  0x8000
181#define FPGA_END   (FPGA_START+FPGA_SIZE-1)
182
183/*
184 * working values for various registers, used in start/start.S
185 */
186
187/* fpga config 16 MB size */
188#define FPGA_CONFIG_START       0xF8000000
189#define FPGA_CONFIG_SIZE        0x01000000
190/* fpga register 8 MB size */
191#define FPGA_REGISTER_START     0xF9000000
192#define FPGA_REGISTER_SIZE      0x00800000
193/* fpga fifo 8 MB size */
194#define FPGA_FIFO_START         0xF9800000
195#define FPGA_FIFO_SIZE          0x00800000
196
197#define FPGA_START (FPGA_CONFIG_START)
198// fpga window size 32 MByte
199#define FPGA_SIZE  (0x02000000)
200#define FPGA_END   (FPGA_START+FPGA_SIZE-1)
201
202/*
203 * Local Access Windows
204 * FIXME: decode bit settings
205 */
206
207#define LBLAWBAR0_VAL  bsp_rom_start
208#define LBLAWAR0_VAL   0x80000018
209#define LBLAWBAR1_VAL  (FPGA_CONFIG_START)
210#define LBLAWAR1_VAL   0x80000015
211#define DDRLAWBAR0_VAL bsp_ram_start
212#define DDRLAWAR0_VAL  0x8000001B
213/*
214 * Local Bus (Memory) Controller
215 * FIXME: decode bit settings
216 */
217#define BR0_VAL 0xFE001001
218#define OR0_VAL 0xFE000E54
219// fpga config access range (UPM_A) (32 kByte)
220#define BR2_VAL (FPGA_CONFIG_START | 0x01881)
221#define OR2_VAL 0xFFF80100
222
223// fpga register access range (UPM_B) (8 MByte)
224#define BR3_VAL (FPGA_REGISTER_START | 0x018A1)
225#define OR3_VAL 0xFF800100
226
227// fpga fifo access range (UPM_B) (8 MByte)
228#define BR4_VAL (FPGA_FIFO_START | 0x018A1)
229#define OR4_VAL 0xFF800100
230
231/*
232 * SDRAM registers
233 */
234#define MRPTR_VAL 0x20000000
235#define LSRT_VAL  0x32000000
236#define LSDMR_VAL 0x4062D733
237#define LCRR_VAL  0x80010004
238
239/*
240 * DDR-SDRAM registers
241 * FIXME: decode bit settings
242 */
243#define DDRCDR_VAL                   0x00000001
244#define CS0_BNDS_VAL                 0x0000000F
245#define CS0_CONFIG_VAL               0x80810102
246#define TIMING_CFG_0_VAL             0x00420802
247#define TIMING_CFG_1_VAL             0x3735A322
248#define TIMING_CFG_2_VAL             0x2F9044C7
249#define DDR_SDRAM_CFG_2_VAL          0x00401000
250#define DDR_SDRAM_MODE_VAL           0x44521632
251#define DDR_SDRAM_CLK_CNTL_VAL       0x01800000
252#define DDR_SDRAM_CFG_VAL            0x43000008
253
254#define DDR_ERR_DISABLE_VAL          0x0000008D
255#define DDR_ERR_DISABLE_VAL2         0x00000089
256#define DDR_SDRAM_DATA_INIT_VAL      0xC01DCAFE
257#define DDR_SDRAM_INIT_ADDR_VAL      0
258#define DDR_SDRAM_INTERVAL_VAL       0x05080000
259
260#elif defined( HAS_UBOOT)
261
262/* TODO */
263
264#else
265
266#error "board type not defined"
267
268#endif
269
270/**************************
271 * derived values for all boards
272 */
273/* value of input clock divider (derived from pll mode reg) */
274#define BSP_SYSPLL_CKID (((mpc83xx.clk.spmr>>(31-8))&0x01)+1)
275/* value of system pll (derived from pll mode reg) */
276#define BSP_SYSPLL_MF    ((mpc83xx.clk.spmr>>(31-7))&0x0f)
277/* value of system pll (derived from pll mode reg) */
278#define BSP_COREPLL_MF   ((mpc83xx.clk.spmr>>(31-15))&0x7f)
279
280#endif /* __GEN83xx_HWREG_VALS_h */
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