[42bf1b9] | 1 | /*===============================================================*\ |
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| 2 | | Project: RTEMS generic MPC83xx BSP | |
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| 3 | +-----------------------------------------------------------------+ |
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| 4 | | Copyright (c) 2007 | |
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| 5 | | Embedded Brains GmbH | |
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| 6 | | Obere Lagerstr. 30 | |
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| 7 | | D-82178 Puchheim | |
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| 8 | | Germany | |
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| 9 | | rtems@embedded-brains.de | |
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| 10 | +-----------------------------------------------------------------+ |
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| 11 | | The license and distribution terms for this file may be | |
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| 12 | | found in the file LICENSE in this distribution or at | |
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| 13 | | | |
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| 14 | | http://www.rtems.com/license/LICENSE. | |
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| 15 | | | |
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| 16 | +-----------------------------------------------------------------+ |
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| 17 | | this file contains board specific definitions | |
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| 18 | \*===============================================================*/ |
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| 19 | |
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| 20 | #ifndef __GEN83xx_HWREG_VALS_h |
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| 21 | #define __GEN83xx_HWREG_VALS_h |
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| 22 | |
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| 23 | #include <mpc83xx/mpc83xx.h> |
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[4b23c94] | 24 | #include <bsp.h> |
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[42bf1b9] | 25 | /* |
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| 26 | * distinguish board characteristics |
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| 27 | */ |
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| 28 | #if defined(MPC8349EAMDS) |
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| 29 | /* |
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| 30 | * for Freescale MPC8349 EAMDS |
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| 31 | */ |
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| 32 | /* |
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| 33 | * two DUART channels supported |
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| 34 | */ |
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| 35 | #define GEN83xx_DUART_AVAIL_MASK 0x03 |
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| 36 | |
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| 37 | /* we need the low level initialization in start.S*/ |
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| 38 | #define NEED_LOW_LEVEL_INIT |
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| 39 | /* |
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| 40 | * clocking infos |
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| 41 | */ |
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| 42 | #define BSP_CLKIN_FRQ 66000000L |
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| 43 | #define RCFG_SYSPLL_MF 4 |
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| 44 | #define RCFG_COREPLL_MF 4 |
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| 45 | |
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| 46 | /* |
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| 47 | * Reset configuration words |
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| 48 | */ |
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| 49 | #define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 | \ |
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| 50 | RCWLR_DDRCM_1_1 | \ |
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| 51 | RCWLR_SPMF(RCFG_SYSPLL_MF) | \ |
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| 52 | RCWLR_COREPLL(RCFG_COREPLL_MF)) |
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| 53 | |
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| 54 | #define RESET_CONF_WRD_H (RCWHR_PCI_HOST | \ |
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| 55 | RCWHR_PCI_32 | \ |
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| 56 | RCWHR_PCI1ARB_EN | \ |
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| 57 | RCWHR_PCI2ARB_EN | \ |
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| 58 | RCWHR_CORE_EN | \ |
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| 59 | RCWHR_BMS_LOW | \ |
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| 60 | RCWHR_BOOTSEQ_NONE | \ |
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| 61 | RCWHR_SW_DIS | \ |
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| 62 | RCWHR_ROMLOC_LB16 | \ |
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| 63 | RCWHR_TSEC1M_GMII | \ |
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| 64 | RCWHR_TSEC2M_GMII | \ |
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| 65 | RCWHR_ENDIAN_BIG | \ |
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| 66 | RCWHR_LALE_NORM | \ |
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| 67 | RCWHR_LDP_PAR) |
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| 68 | #elif defined(HSC_CM01) |
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| 69 | /* |
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| 70 | * for JPK HSC_CM01 |
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| 71 | */ |
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| 72 | /* |
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| 73 | * one DUART channel (UART1) supported |
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| 74 | */ |
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| 75 | #define GEN83xx_DUART_AVAIL_MASK 0x01 |
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| 76 | |
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| 77 | /* we need the low level initialization in start.S*/ |
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| 78 | #define NEED_LOW_LEVEL_INIT |
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| 79 | /* |
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| 80 | * clocking infos |
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| 81 | */ |
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| 82 | #define BSP_CLKIN_FRQ 30000000L |
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| 83 | #define RCFG_SYSPLL_MF 11 |
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| 84 | #define RCFG_COREPLL_MF 4 |
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| 85 | /* |
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| 86 | * Reset configuration words |
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| 87 | */ |
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| 88 | #define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 | \ |
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| 89 | RCWLR_DDRCM_1_1 | \ |
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| 90 | RCWLR_SPMF(RCFG_SYSPLL_MF) | \ |
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| 91 | RCWLR_COREPLL(RCFG_COREPLL_MF)) |
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| 92 | |
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| 93 | #define RESET_CONF_WRD_H (RCWHR_PCI_HOST | \ |
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| 94 | RCWHR_PCI_32 | \ |
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[4b23c94] | 95 | RCWHR_PCI1ARB_DIS | \ |
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| 96 | RCWHR_PCI2ARB_DIS | \ |
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[42bf1b9] | 97 | RCWHR_CORE_EN | \ |
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| 98 | RCWHR_BMS_LOW | \ |
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| 99 | RCWHR_BOOTSEQ_NONE | \ |
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| 100 | RCWHR_SW_DIS | \ |
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| 101 | RCWHR_ROMLOC_LB16 | \ |
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| 102 | RCWHR_TSEC1M_RGMII | \ |
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| 103 | RCWHR_TSEC2M_GMII | \ |
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| 104 | RCWHR_ENDIAN_BIG | \ |
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[4b23c94] | 105 | RCWHR_LALE_EARLY | \ |
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| 106 | RCWHR_LDP_SPC) |
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[574fb67] | 107 | |
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| 108 | #elif defined( HAS_UBOOT) |
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| 109 | |
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| 110 | /* TODO */ |
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| 111 | |
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[42bf1b9] | 112 | #else |
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[574fb67] | 113 | |
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[42bf1b9] | 114 | #error "board type not defined" |
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[574fb67] | 115 | |
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[42bf1b9] | 116 | #endif |
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| 117 | |
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| 118 | #if defined(MPC8349EAMDS) |
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| 119 | /************************** |
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| 120 | * for Freescale MPC8349EAMDS |
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| 121 | */ |
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| 122 | |
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| 123 | /* |
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| 124 | * working values for various registers, used in start/start.S |
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| 125 | */ |
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[574fb67] | 126 | |
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[42bf1b9] | 127 | /* |
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| 128 | * Local Access Windows |
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| 129 | * FIXME: decode bit settings |
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| 130 | */ |
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| 131 | #define LBLAWBAR0_VAL 0xFE000000 |
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| 132 | #define LBLAWAR0_VAL 0x80000016 |
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| 133 | #define LBLAWBAR1_VAL 0xF8000000 |
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| 134 | #define LBLAWAR1_VAL 0x8000000E |
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| 135 | #define LBLAWBAR2_VAL 0xF0000000 |
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| 136 | #define LBLAWAR2_VAL 0x80000019 |
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| 137 | #define DDRLAWBAR0_VAL 0x00000000 |
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| 138 | #define DDRLAWAR0_VAL 0x8000001B |
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| 139 | /* |
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| 140 | * Local Bus (Memory) Controller |
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| 141 | * FIXME: decode bit settings |
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| 142 | */ |
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| 143 | #define BR0_VAL 0xFE001001 |
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| 144 | #define OR0_VAL 0xFF806FF7 |
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| 145 | #define BR1_VAL 0xF8000801 |
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| 146 | #define OR1_VAL 0xFFFFE8F0 |
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| 147 | #define BR2_VAL 0xF0001861 |
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| 148 | #define OR2_VAL 0xFC006901 |
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| 149 | /* |
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| 150 | * SDRAM registers |
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| 151 | * FIXME: decode bit settings |
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| 152 | */ |
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| 153 | #define MRPTR_VAL 0x20000000 |
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| 154 | #define LSRT_VAL 0x32000000 |
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| 155 | #define LSDMR_VAL 0x4062D733 |
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| 156 | #define LCRR_VAL 0x80000004 |
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| 157 | |
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| 158 | /* |
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| 159 | * DDR-SDRAM registers |
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| 160 | * FIXME: decode bit settings |
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| 161 | */ |
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| 162 | #define CS2_BNDS_VAL 0x00000007 |
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| 163 | #define CS3_BNDS_VAL 0x0008000F |
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| 164 | #define CS2_CONFIG_VAL 0x80000101 |
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| 165 | #define CS3_CONFIG_VAL 0x80000101 |
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| 166 | #define TIMING_CFG_1_VAL 0x36333321 |
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| 167 | #define TIMING_CFG_2_VAL 0x00000800 |
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| 168 | #define DDR_SDRAM_CFG_VAL 0xC2000000 |
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| 169 | #define DDR_SDRAM_MODE_VAL 0x00000022 |
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| 170 | #define DDR_SDRAM_INTTVL_VAL 0x045B0100 |
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| 171 | #define DDR_SDRAM_CLK_CNTL_VAL 0x00000000 |
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| 172 | |
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| 173 | #elif defined(HSC_CM01) |
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| 174 | /************************** |
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| 175 | * for JPK HSC_CM01 |
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| 176 | */ |
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| 177 | |
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[4b23c94] | 178 | /* fpga BCSR register */ |
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| 179 | #define FPGA_START 0xF8000000 |
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| 180 | #define FPGA_SIZE 0x8000 |
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| 181 | #define FPGA_END (FPGA_START+FPGA_SIZE-1) |
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| 182 | |
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[42bf1b9] | 183 | /* |
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| 184 | * working values for various registers, used in start/start.S |
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| 185 | */ |
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[574fb67] | 186 | |
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[4b23c94] | 187 | /* fpga config 16 MB size */ |
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| 188 | #define FPGA_CONFIG_START 0xF8000000 |
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| 189 | #define FPGA_CONFIG_SIZE 0x01000000 |
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| 190 | /* fpga register 8 MB size */ |
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| 191 | #define FPGA_REGISTER_START 0xF9000000 |
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| 192 | #define FPGA_REGISTER_SIZE 0x00800000 |
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| 193 | /* fpga fifo 8 MB size */ |
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| 194 | #define FPGA_FIFO_START 0xF9800000 |
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| 195 | #define FPGA_FIFO_SIZE 0x00800000 |
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| 196 | |
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| 197 | #define FPGA_START (FPGA_CONFIG_START) |
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| 198 | // fpga window size 32 MByte |
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| 199 | #define FPGA_SIZE (0x02000000) |
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| 200 | #define FPGA_END (FPGA_START+FPGA_SIZE-1) |
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| 201 | |
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[42bf1b9] | 202 | /* |
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| 203 | * Local Access Windows |
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| 204 | * FIXME: decode bit settings |
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| 205 | */ |
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| 206 | |
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[574fb67] | 207 | #define LBLAWBAR0_VAL bsp_rom_start |
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[42bf1b9] | 208 | #define LBLAWAR0_VAL 0x80000018 |
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[4b23c94] | 209 | #define LBLAWBAR1_VAL (FPGA_CONFIG_START) |
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[42bf1b9] | 210 | #define LBLAWAR1_VAL 0x80000015 |
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[574fb67] | 211 | #define DDRLAWBAR0_VAL bsp_ram_start |
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[42bf1b9] | 212 | #define DDRLAWAR0_VAL 0x8000001B |
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| 213 | /* |
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| 214 | * Local Bus (Memory) Controller |
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| 215 | * FIXME: decode bit settings |
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| 216 | */ |
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| 217 | #define BR0_VAL 0xFE001001 |
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| 218 | #define OR0_VAL 0xFE000E54 |
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[4b23c94] | 219 | // fpga config access range (UPM_A) (32 kByte) |
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| 220 | #define BR2_VAL (FPGA_CONFIG_START | 0x01881) |
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| 221 | #define OR2_VAL 0xFFF80100 |
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| 222 | |
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| 223 | // fpga register access range (UPM_B) (8 MByte) |
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| 224 | #define BR3_VAL (FPGA_REGISTER_START | 0x018A1) |
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| 225 | #define OR3_VAL 0xFF800100 |
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| 226 | |
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| 227 | // fpga fifo access range (UPM_B) (8 MByte) |
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| 228 | #define BR4_VAL (FPGA_FIFO_START | 0x018A1) |
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| 229 | #define OR4_VAL 0xFF800100 |
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| 230 | |
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[42bf1b9] | 231 | /* |
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[4b23c94] | 232 | * SDRAM registers |
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[42bf1b9] | 233 | */ |
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[4b23c94] | 234 | #define MRPTR_VAL 0x20000000 |
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| 235 | #define LSRT_VAL 0x32000000 |
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| 236 | #define LSDMR_VAL 0x4062D733 |
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| 237 | #define LCRR_VAL 0x80010004 |
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[42bf1b9] | 238 | |
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| 239 | /* |
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| 240 | * DDR-SDRAM registers |
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| 241 | * FIXME: decode bit settings |
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| 242 | */ |
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| 243 | #define DDRCDR_VAL 0x00000001 |
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| 244 | #define CS0_BNDS_VAL 0x0000000F |
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| 245 | #define CS0_CONFIG_VAL 0x80810102 |
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| 246 | #define TIMING_CFG_0_VAL 0x00420802 |
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| 247 | #define TIMING_CFG_1_VAL 0x3735A322 |
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| 248 | #define TIMING_CFG_2_VAL 0x2F9044C7 |
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| 249 | #define DDR_SDRAM_CFG_2_VAL 0x00401000 |
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| 250 | #define DDR_SDRAM_MODE_VAL 0x44521632 |
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| 251 | #define DDR_SDRAM_CLK_CNTL_VAL 0x01800000 |
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[eb32e3a] | 252 | #define DDR_SDRAM_CFG_VAL 0x63000008 |
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[42bf1b9] | 253 | |
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| 254 | #define DDR_ERR_DISABLE_VAL 0x0000008D |
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| 255 | #define DDR_ERR_DISABLE_VAL2 0x00000089 |
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| 256 | #define DDR_SDRAM_DATA_INIT_VAL 0xC01DCAFE |
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| 257 | #define DDR_SDRAM_INIT_ADDR_VAL 0 |
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| 258 | #define DDR_SDRAM_INTERVAL_VAL 0x05080000 |
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[574fb67] | 259 | |
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| 260 | #elif defined( HAS_UBOOT) |
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| 261 | |
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| 262 | /* TODO */ |
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| 263 | |
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[42bf1b9] | 264 | #else |
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[574fb67] | 265 | |
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[42bf1b9] | 266 | #error "board type not defined" |
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| 267 | |
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[574fb67] | 268 | #endif |
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[42bf1b9] | 269 | |
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| 270 | /************************** |
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| 271 | * derived values for all boards |
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| 272 | */ |
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| 273 | /* value of input clock divider (derived from pll mode reg) */ |
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| 274 | #define BSP_SYSPLL_CKID (((mpc83xx.clk.spmr>>(31-8))&0x01)+1) |
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| 275 | /* value of system pll (derived from pll mode reg) */ |
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| 276 | #define BSP_SYSPLL_MF ((mpc83xx.clk.spmr>>(31-7))&0x0f) |
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| 277 | /* value of system pll (derived from pll mode reg) */ |
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| 278 | #define BSP_COREPLL_MF ((mpc83xx.clk.spmr>>(31-15))&0x7f) |
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| 279 | |
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| 280 | #endif /* __GEN83xx_HWREG_VALS_h */ |
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