[42bf1b9] | 1 | /*===============================================================*\ |
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| 2 | | Project: RTEMS generic MPC83xx BSP | |
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| 3 | +-----------------------------------------------------------------+ |
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| 4 | | Copyright (c) 2007 | |
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| 5 | | Embedded Brains GmbH | |
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| 6 | | Obere Lagerstr. 30 | |
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| 7 | | D-82178 Puchheim | |
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| 8 | | Germany | |
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| 9 | | rtems@embedded-brains.de | |
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| 10 | +-----------------------------------------------------------------+ |
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| 11 | | The license and distribution terms for this file may be | |
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| 12 | | found in the file LICENSE in this distribution or at | |
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| 13 | | | |
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| 14 | | http://www.rtems.com/license/LICENSE. | |
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| 15 | | | |
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| 16 | +-----------------------------------------------------------------+ |
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| 17 | | this file contains board specific definitions | |
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| 18 | \*===============================================================*/ |
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| 19 | |
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[e570c313] | 20 | /* |
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| 21 | * $Id$ |
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| 22 | */ |
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| 23 | |
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[42bf1b9] | 24 | #ifndef __GEN83xx_HWREG_VALS_h |
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| 25 | #define __GEN83xx_HWREG_VALS_h |
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| 26 | |
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| 27 | #include <mpc83xx/mpc83xx.h> |
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[4b23c94] | 28 | #include <bsp.h> |
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[42bf1b9] | 29 | /* |
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| 30 | * distinguish board characteristics |
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| 31 | */ |
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[7a752161] | 32 | #if defined(MPC83XX_BOARD_MPC8349EAMDS) |
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[42bf1b9] | 33 | /* |
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| 34 | * for Freescale MPC8349 EAMDS |
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| 35 | */ |
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| 36 | /* |
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| 37 | * two DUART channels supported |
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| 38 | */ |
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| 39 | #define GEN83xx_DUART_AVAIL_MASK 0x03 |
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| 40 | |
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| 41 | /* we need the low level initialization in start.S*/ |
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| 42 | #define NEED_LOW_LEVEL_INIT |
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| 43 | /* |
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| 44 | * clocking infos |
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| 45 | */ |
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| 46 | #define BSP_CLKIN_FRQ 66000000L |
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[ac7af4a] | 47 | #define RCFG_SYSPLL_MF 4 |
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[42bf1b9] | 48 | #define RCFG_COREPLL_MF 4 |
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| 49 | |
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| 50 | /* |
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| 51 | * Reset configuration words |
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| 52 | */ |
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| 53 | #define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 | \ |
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| 54 | RCWLR_DDRCM_1_1 | \ |
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| 55 | RCWLR_SPMF(RCFG_SYSPLL_MF) | \ |
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| 56 | RCWLR_COREPLL(RCFG_COREPLL_MF)) |
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| 57 | |
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| 58 | #define RESET_CONF_WRD_H (RCWHR_PCI_HOST | \ |
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| 59 | RCWHR_PCI_32 | \ |
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| 60 | RCWHR_PCI1ARB_EN | \ |
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| 61 | RCWHR_PCI2ARB_EN | \ |
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| 62 | RCWHR_CORE_EN | \ |
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| 63 | RCWHR_BMS_LOW | \ |
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| 64 | RCWHR_BOOTSEQ_NONE | \ |
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| 65 | RCWHR_SW_DIS | \ |
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| 66 | RCWHR_ROMLOC_LB16 | \ |
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| 67 | RCWHR_TSEC1M_GMII | \ |
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| 68 | RCWHR_TSEC2M_GMII | \ |
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| 69 | RCWHR_ENDIAN_BIG | \ |
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| 70 | RCWHR_LALE_NORM | \ |
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| 71 | RCWHR_LDP_PAR) |
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[7a752161] | 72 | #elif defined(MPC83XX_BOARD_HSC_CM01) |
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[42bf1b9] | 73 | /* |
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| 74 | * for JPK HSC_CM01 |
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| 75 | */ |
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| 76 | /* |
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| 77 | * one DUART channel (UART1) supported |
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| 78 | */ |
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| 79 | #define GEN83xx_DUART_AVAIL_MASK 0x01 |
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| 80 | |
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| 81 | /* we need the low level initialization in start.S*/ |
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| 82 | #define NEED_LOW_LEVEL_INIT |
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| 83 | /* |
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| 84 | * clocking infos |
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| 85 | */ |
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| 86 | #define BSP_CLKIN_FRQ 30000000L |
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[ac7af4a] | 87 | #define RCFG_SYSPLL_MF 11 |
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[42bf1b9] | 88 | #define RCFG_COREPLL_MF 4 |
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| 89 | /* |
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| 90 | * Reset configuration words |
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| 91 | */ |
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| 92 | #define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 | \ |
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| 93 | RCWLR_DDRCM_1_1 | \ |
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| 94 | RCWLR_SPMF(RCFG_SYSPLL_MF) | \ |
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| 95 | RCWLR_COREPLL(RCFG_COREPLL_MF)) |
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| 96 | |
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| 97 | #define RESET_CONF_WRD_H (RCWHR_PCI_HOST | \ |
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| 98 | RCWHR_PCI_32 | \ |
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[4b23c94] | 99 | RCWHR_PCI1ARB_DIS | \ |
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| 100 | RCWHR_PCI2ARB_DIS | \ |
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[42bf1b9] | 101 | RCWHR_CORE_EN | \ |
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| 102 | RCWHR_BMS_LOW | \ |
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| 103 | RCWHR_BOOTSEQ_NONE | \ |
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| 104 | RCWHR_SW_DIS | \ |
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| 105 | RCWHR_ROMLOC_LB16 | \ |
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| 106 | RCWHR_TSEC1M_RGMII | \ |
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| 107 | RCWHR_TSEC2M_GMII | \ |
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| 108 | RCWHR_ENDIAN_BIG | \ |
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[4b23c94] | 109 | RCWHR_LALE_EARLY | \ |
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| 110 | RCWHR_LDP_SPC) |
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[574fb67] | 111 | |
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| 112 | #elif defined( HAS_UBOOT) |
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| 113 | |
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| 114 | /* TODO */ |
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| 115 | |
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[42bf1b9] | 116 | #else |
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[574fb67] | 117 | |
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[42bf1b9] | 118 | #error "board type not defined" |
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[574fb67] | 119 | |
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[42bf1b9] | 120 | #endif |
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| 121 | |
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[7a752161] | 122 | #if defined(MPC83XX_BOARD_MPC8349EAMDS) |
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[42bf1b9] | 123 | /************************** |
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[7a752161] | 124 | * for Freescale MPC83XX_BOARD_MPC8349EAMDS |
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[42bf1b9] | 125 | */ |
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| 126 | |
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| 127 | /* |
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| 128 | * working values for various registers, used in start/start.S |
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| 129 | */ |
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[574fb67] | 130 | |
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[42bf1b9] | 131 | /* |
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| 132 | * Local Access Windows |
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[ac7af4a] | 133 | * FIXME: decode bit settings |
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[42bf1b9] | 134 | */ |
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| 135 | #define LBLAWBAR0_VAL 0xFE000000 |
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| 136 | #define LBLAWAR0_VAL 0x80000016 |
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| 137 | #define LBLAWBAR1_VAL 0xF8000000 |
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| 138 | #define LBLAWAR1_VAL 0x8000000E |
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| 139 | #define LBLAWBAR2_VAL 0xF0000000 |
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| 140 | #define LBLAWAR2_VAL 0x80000019 |
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| 141 | #define DDRLAWBAR0_VAL 0x00000000 |
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| 142 | #define DDRLAWAR0_VAL 0x8000001B |
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| 143 | /* |
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| 144 | * Local Bus (Memory) Controller |
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[ac7af4a] | 145 | * FIXME: decode bit settings |
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[42bf1b9] | 146 | */ |
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| 147 | #define BR0_VAL 0xFE001001 |
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| 148 | #define OR0_VAL 0xFF806FF7 |
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| 149 | #define BR1_VAL 0xF8000801 |
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| 150 | #define OR1_VAL 0xFFFFE8F0 |
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| 151 | #define BR2_VAL 0xF0001861 |
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| 152 | #define OR2_VAL 0xFC006901 |
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| 153 | /* |
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| 154 | * SDRAM registers |
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[ac7af4a] | 155 | * FIXME: decode bit settings |
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[42bf1b9] | 156 | */ |
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| 157 | #define MRPTR_VAL 0x20000000 |
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| 158 | #define LSRT_VAL 0x32000000 |
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| 159 | #define LSDMR_VAL 0x4062D733 |
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| 160 | #define LCRR_VAL 0x80000004 |
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| 161 | |
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| 162 | /* |
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| 163 | * DDR-SDRAM registers |
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[ac7af4a] | 164 | * FIXME: decode bit settings |
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[42bf1b9] | 165 | */ |
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| 166 | #define CS2_BNDS_VAL 0x00000007 |
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| 167 | #define CS3_BNDS_VAL 0x0008000F |
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| 168 | #define CS2_CONFIG_VAL 0x80000101 |
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| 169 | #define CS3_CONFIG_VAL 0x80000101 |
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| 170 | #define TIMING_CFG_1_VAL 0x36333321 |
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| 171 | #define TIMING_CFG_2_VAL 0x00000800 |
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| 172 | #define DDR_SDRAM_CFG_VAL 0xC2000000 |
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| 173 | #define DDR_SDRAM_MODE_VAL 0x00000022 |
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| 174 | #define DDR_SDRAM_INTTVL_VAL 0x045B0100 |
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| 175 | #define DDR_SDRAM_CLK_CNTL_VAL 0x00000000 |
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| 176 | |
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[7a752161] | 177 | #elif defined(MPC83XX_BOARD_HSC_CM01) |
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[42bf1b9] | 178 | /************************** |
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| 179 | * for JPK HSC_CM01 |
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| 180 | */ |
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| 181 | |
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[4b23c94] | 182 | /* fpga BCSR register */ |
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| 183 | #define FPGA_START 0xF8000000 |
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| 184 | #define FPGA_SIZE 0x8000 |
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| 185 | #define FPGA_END (FPGA_START+FPGA_SIZE-1) |
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| 186 | |
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[42bf1b9] | 187 | /* |
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| 188 | * working values for various registers, used in start/start.S |
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| 189 | */ |
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[574fb67] | 190 | |
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[4b23c94] | 191 | /* fpga config 16 MB size */ |
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| 192 | #define FPGA_CONFIG_START 0xF8000000 |
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| 193 | #define FPGA_CONFIG_SIZE 0x01000000 |
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| 194 | /* fpga register 8 MB size */ |
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| 195 | #define FPGA_REGISTER_START 0xF9000000 |
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| 196 | #define FPGA_REGISTER_SIZE 0x00800000 |
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| 197 | /* fpga fifo 8 MB size */ |
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| 198 | #define FPGA_FIFO_START 0xF9800000 |
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| 199 | #define FPGA_FIFO_SIZE 0x00800000 |
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| 200 | |
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| 201 | #define FPGA_START (FPGA_CONFIG_START) |
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| 202 | // fpga window size 32 MByte |
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| 203 | #define FPGA_SIZE (0x02000000) |
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| 204 | #define FPGA_END (FPGA_START+FPGA_SIZE-1) |
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| 205 | |
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[42bf1b9] | 206 | /* |
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| 207 | * Local Access Windows |
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[ac7af4a] | 208 | * FIXME: decode bit settings |
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[42bf1b9] | 209 | */ |
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| 210 | |
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[574fb67] | 211 | #define LBLAWBAR0_VAL bsp_rom_start |
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[42bf1b9] | 212 | #define LBLAWAR0_VAL 0x80000018 |
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[4b23c94] | 213 | #define LBLAWBAR1_VAL (FPGA_CONFIG_START) |
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[ce7d6e62] | 214 | #define LBLAWAR1_VAL 0x80000018 |
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[574fb67] | 215 | #define DDRLAWBAR0_VAL bsp_ram_start |
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[42bf1b9] | 216 | #define DDRLAWAR0_VAL 0x8000001B |
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| 217 | /* |
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| 218 | * Local Bus (Memory) Controller |
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[ac7af4a] | 219 | * FIXME: decode bit settings |
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[42bf1b9] | 220 | */ |
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[ce7d6e62] | 221 | #define BR0_VAL (0xFE000000 | 0x01001) |
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[42bf1b9] | 222 | #define OR0_VAL 0xFE000E54 |
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[4b23c94] | 223 | // fpga config access range (UPM_A) (32 kByte) |
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| 224 | #define BR2_VAL (FPGA_CONFIG_START | 0x01881) |
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[ce7d6e62] | 225 | #define OR2_VAL 0xFFFF9100 |
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[4b23c94] | 226 | |
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| 227 | // fpga register access range (UPM_B) (8 MByte) |
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| 228 | #define BR3_VAL (FPGA_REGISTER_START | 0x018A1) |
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[ce7d6e62] | 229 | #define OR3_VAL 0xFF801100 |
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[4b23c94] | 230 | |
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[ce7d6e62] | 231 | // fpga fifo access range (UPM_C) (8 MByte) |
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| 232 | #define BR4_VAL (FPGA_FIFO_START | 0x018C1) |
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| 233 | #define OR4_VAL 0xFF801100 |
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[4b23c94] | 234 | |
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[42bf1b9] | 235 | /* |
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[4b23c94] | 236 | * SDRAM registers |
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[42bf1b9] | 237 | */ |
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[4b23c94] | 238 | #define MRPTR_VAL 0x20000000 |
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| 239 | #define LSRT_VAL 0x32000000 |
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| 240 | #define LSDMR_VAL 0x4062D733 |
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| 241 | #define LCRR_VAL 0x80010004 |
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[42bf1b9] | 242 | |
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| 243 | /* |
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| 244 | * DDR-SDRAM registers |
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[ac7af4a] | 245 | * FIXME: decode bit settings |
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[42bf1b9] | 246 | */ |
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| 247 | #define DDRCDR_VAL 0x00000001 |
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| 248 | #define CS0_BNDS_VAL 0x0000000F |
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| 249 | #define CS0_CONFIG_VAL 0x80810102 |
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| 250 | #define TIMING_CFG_0_VAL 0x00420802 |
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| 251 | #define TIMING_CFG_1_VAL 0x3735A322 |
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| 252 | #define TIMING_CFG_2_VAL 0x2F9044C7 |
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| 253 | #define DDR_SDRAM_CFG_2_VAL 0x00401000 |
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| 254 | #define DDR_SDRAM_MODE_VAL 0x44521632 |
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| 255 | #define DDR_SDRAM_CLK_CNTL_VAL 0x01800000 |
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[d11ea4eb] | 256 | #define DDR_SDRAM_CFG_VAL 0x63000008 |
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[42bf1b9] | 257 | |
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| 258 | #define DDR_ERR_DISABLE_VAL 0x0000008D |
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| 259 | #define DDR_ERR_DISABLE_VAL2 0x00000089 |
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| 260 | #define DDR_SDRAM_DATA_INIT_VAL 0xC01DCAFE |
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| 261 | #define DDR_SDRAM_INIT_ADDR_VAL 0 |
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| 262 | #define DDR_SDRAM_INTERVAL_VAL 0x05080000 |
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[574fb67] | 263 | |
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| 264 | #elif defined( HAS_UBOOT) |
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| 265 | |
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| 266 | /* TODO */ |
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| 267 | |
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[42bf1b9] | 268 | #else |
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[574fb67] | 269 | |
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[42bf1b9] | 270 | #error "board type not defined" |
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| 271 | |
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[574fb67] | 272 | #endif |
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[42bf1b9] | 273 | |
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| 274 | /************************** |
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| 275 | * derived values for all boards |
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| 276 | */ |
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| 277 | /* value of input clock divider (derived from pll mode reg) */ |
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| 278 | #define BSP_SYSPLL_CKID (((mpc83xx.clk.spmr>>(31-8))&0x01)+1) |
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| 279 | /* value of system pll (derived from pll mode reg) */ |
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[ac7af4a] | 280 | #define BSP_SYSPLL_MF ((mpc83xx.clk.spmr>>(31-7))&0x0f) |
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[42bf1b9] | 281 | /* value of system pll (derived from pll mode reg) */ |
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[ac7af4a] | 282 | #define BSP_COREPLL_MF ((mpc83xx.clk.spmr>>(31-15))&0x7f) |
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[42bf1b9] | 283 | |
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| 284 | #endif /* __GEN83xx_HWREG_VALS_h */ |
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