source: rtems/c/src/lib/libbsp/powerpc/gen83xx/include/bsp.h @ abe0cdb1

4.104.114.95
Last change on this file since abe0cdb1 was 55a685b, checked in by Thomas Doerfler <Thomas.Doerfler@…>, on 10/25/07 at 16:17:56

added SPI support to libi2c
added IRQ support to MPC83xx i2c driver
added mpc83xx spi driver
  • Property mode set to 100644
File size: 7.4 KB
Line 
1/*===============================================================*\
2| Project: RTEMS generic MPC83xx BSP                              |
3+-----------------------------------------------------------------+
4|                    Copyright (c) 2007                           |
5|                    Embedded Brains GmbH                         |
6|                    Obere Lagerstr. 30                           |
7|                    D-82178 Puchheim                             |
8|                    Germany                                      |
9|                    rtems@embedded-brains.de                     |
10+-----------------------------------------------------------------+
11| The license and distribution terms for this file may be         |
12| found in the file LICENSE in this distribution or at            |
13|                                                                 |
14| http://www.rtems.com/license/LICENSE.                           |
15|                                                                 |
16+-----------------------------------------------------------------+
17| this file contains board specific definitions                   |
18\*===============================================================*/
19
20#ifndef __GEN83xx_BSP_h
21#define __GEN83xx_BSP_h
22
23/*
24 * distinguish board characteristics
25 */
26/*
27 * for Freescale MPC8349 EAMDS
28 */
29#if defined(MPC8349EAMDS)
30/*
31 * two DUART channels supported
32 */
33#define GEN83xx_DUART_AVAIL_MASK 0x03
34
35/* we need the low level initialization in start.S*/
36#define NEED_LOW_LEVEL_INIT
37/*
38 * clocking infos
39 */
40#define BSP_CLKIN_FRQ 66000000L
41#define BSP_SYSPLL_MF 4 /* FIXME: derive from clock register */
42
43/*
44 * Reset configuration words
45 */
46#define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 |    \
47                          RCWLR_DDRCM_1_1  |    \
48                          RCWLR_SPMF(4)    |    \
49                          RCWLR_COREPLL(4))
50
51#define RESET_CONF_WRD_H (RCWHR_PCI_HOST     |  \
52                          RCWHR_PCI_32       |  \
53                          RCWHR_PCI1ARB_EN   |  \
54                          RCWHR_PCI2ARB_EN   |  \
55                          RCWHR_CORE_EN      |  \
56                          RCWHR_BMS_LOW      |  \
57                          RCWHR_BOOTSEQ_NONE |  \
58                          RCWHR_SW_DIS       |  \
59                          RCWHR_ROMLOC_LB16  |  \
60                          RCWHR_TSEC1M_GMII  |  \
61                          RCWHR_TSEC2M_GMII  |  \
62                          RCWHR_ENDIAN_BIG   |  \
63                          RCWHR_LALE_NORM    |  \
64                          RCWHR_LDP_PAR)
65/*
66 * for JPK HSC_CM01
67 */
68#elif defined(HSC_CM01)
69/*
70 * one DUART channel (UART1) supported
71 */
72#define GEN83xx_DUART_AVAIL_MASK 0x01
73
74/* we need the low level initialization in start.S*/
75#define NEED_LOW_LEVEL_INIT
76/*
77 * clocking infos
78 */
79#define BSP_CLKIN_FRQ 66000000L
80#define BSP_SYSPLL_MF 4 /* FIXME: derive from clock register */
81
82/*
83 * Reset configuration words
84 */
85#define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 |    \
86                          RCWLR_DDRCM_1_1  |    \
87                          RCWLR_SPMF(4)    |    \
88                          RCWLR_COREPLL(4))
89
90#define RESET_CONF_WRD_H (RCWHR_PCI_HOST     |  \
91                          RCWHR_PCI_32       |  \
92                          RCWHR_PCI1ARB_EN   |  \
93                          RCWHR_PCI2ARB_EN   |  \
94                          RCWHR_CORE_EN      |  \
95                          RCWHR_BMS_LOW      |  \
96                          RCWHR_BOOTSEQ_NONE |  \
97                          RCWHR_SW_DIS       |  \
98                          RCWHR_ROMLOC_LB16  |  \
99                          RCWHR_TSEC1M_RGMII |  \
100                          RCWHR_TSEC2M_GMII  |  \
101                          RCWHR_ENDIAN_BIG   |  \
102                          RCWHR_LALE_NORM    |  \
103                          RCWHR_LDP_PAR)
104#else
105#error "board type not defined"
106#endif
107
108/*
109 * for JPK HSC_CM01 and freescale MPC8349EAMDS
110 */
111#if defined(MPC8349EAMDS) || defined(HSC_CM01)
112/*
113 * address range definitions
114 */
115/* ROM definitions (8 MB, mirrored multiple times) */
116#define ROM_START       0xFE000000
117#define ROM_SIZE        0x02000000
118#define ROM_END         (ROM_START+ROM_SIZE-1)
119#define BOOT_START      ROM_START
120#define BOOT_END        ROM_END
121
122/* SDRAM definitions (256 MB) */
123#define RAM_START       0x00000000
124#define RAM_SIZE        0x10000000
125#define RAM_END         (RAM_START+RAM_SIZE-1)
126
127
128/* working internal memory map base address */
129#define IMMRBAR         0xE0000000
130
131/*
132 * working values for various registers, used in start/start.S
133 */
134/*
135 * Local Access Windows
136 * FIXME: decode bit settings
137 */
138#define LBLAWBAR0_VAL  0xFE000000
139#define LBLAWAR0_VAL   0x80000016
140#define LBLAWBAR1_VAL  0xF8000000
141#define LBLAWAR1_VAL   0x8000000E
142#define LBLAWBAR2_VAL  0xF0000000
143#define LBLAWAR2_VAL   0x80000019
144#define DDRLAWBAR0_VAL 0x00000000
145#define DDRLAWAR0_VAL  0x8000001B
146/*
147 * Local Bus (Memory) Controller
148 * FIXME: decode bit settings
149 */
150#define BR0_VAL 0xFE001001
151#define OR0_VAL 0xFF806FF7
152#define BR1_VAL 0xF8000801
153#define OR1_VAL 0xFFFFE8F0
154#define BR2_VAL 0xF0001861
155#define OR2_VAL 0xFC006901
156/*
157 * SDRAM registers
158 * FIXME: decode bit settings
159 */
160#define MRPTR_VAL 0x20000000
161#define LSRT_VAL  0x32000000
162#define LSDMR_VAL 0x4062D733
163#define LCRR_VAL  0x80000004
164
165/*
166 * DDR-SDRAM registers
167 * FIXME: decode bit settings
168 */
169#define CS2_BNDS_VAL                 0x00000007
170#define CS3_BNDS_VAL                 0x0008000F
171#define CS2_CONFIG_VAL               0x80000101
172#define CS3_CONFIG_VAL               0x80000101
173#define TIMING_CFG_1_VAL             0x36333321
174#define TIMING_CFG_2_VAL             0x00000800
175#define DDR_SDRAM_CFG_VAL            0xC2000000
176#define DDR_SDRAM_MODE_VAL           0x00000022
177#define DDR_SDRAM_INTTVL_VAL         0x045B0100
178#define DDR_SDRAM_CLK_CNTL_VAL       0x00000000
179
180#else
181#error "board type not defined"
182#endif
183
184#ifndef ASM
185
186#ifdef __cplusplus
187extern "C" {
188#endif
189
190#include "bspopts.h"
191
192#include <rtems.h>
193#include <rtems/console.h>
194#include <rtems/clockdrv.h>
195#include <bsp/irq.h>
196#include <bsp/vectors.h>
197
198/* miscellaneous stuff assumed to exist */
199
200extern rtems_configuration_table BSP_Configuration;
201/*
202 * We need to decide how much memory will be non-cacheable. This
203 * will mainly be memory that will be used in DMA (network and serial
204 * buffers).
205 */
206/*
207 *  Stuff for Time Test 27
208 */
209#define MUST_WAIT_FOR_INTERRUPT 0
210
211/*
212 *  Device Driver Table Entries
213 */
214
215/*
216 * NOTE: Use the standard Console driver entry
217 */
218#define BSP_UART1_MINOR 0
219#define BSP_UART2_MINOR 1
220
221/*
222 * NOTE: Use the standard Clock driver entry
223 */
224
225/*
226 * indicate, that BSP has no IDE driver
227 */
228#undef RTEMS_BSP_HAS_IDE_DRIVER
229
230/*
231 * How many libio files we want
232 */
233#define BSP_LIBIO_MAX_FDS       20
234
235/* misc macros */
236#define BSP_ARRAY_CNT(arr) (sizeof(arr)/sizeof(arr[0]))
237
238/* functions */
239
240void bsp_cleanup(void);
241rtems_status_code bsp_register_i2c(void);
242rtems_status_code bsp_register_spi(void);
243
244/* console modes (only termios) */
245#ifdef  PRINTK_MINOR
246#undef  PRINTK_MINOR
247#endif
248#define PRINTK_MINOR BSP_UART1_MINOR
249
250#define SINGLE_CHAR_MODE
251#define UARTS_USE_TERMIOS_INT   1
252
253/*
254 *  Convert decrement value to tenths of microsecnds (used by
255 *  shared timer driver).
256 *
257 *    + CPU has a csb_clock bus,
258 *    + There are 4 bus cycles per click
259 *    + We return value in 1/10 microsecond units.
260 *   Modified following equation to integer equation to remove
261 *   floating point math.
262 *   (int) ((float)(_value) / ((XLB_CLOCK/1000000 * 0.1) / 4.0))
263 */
264#define BSP_CSB_CLK_FRQ (BSP_CLKIN_FRQ * BSP_SYSPLL_MF)
265#define BSP_Convert_decrementer( _value ) \
266  (int) (((_value) * 4000) / (BSP_CSB_CLK_FRQ/10000))
267
268/*
269 * Network driver configuration
270 */
271struct rtems_bsdnet_ifconfig;
272extern int BSP_tsec_attach(struct rtems_bsdnet_ifconfig *config,int attaching);
273#define RTEMS_BSP_NETWORK_DRIVER_NAME   "tsec1"
274#define RTEMS_BSP_NETWORK_DRIVER_ATTACH BSP_tsec_attach
275
276#define RTEMS_BSP_NETWORK_DRIVER_NAME2  "tsec2"
277
278/*
279 * i2c EEPROM device name
280 */
281#define RTEMS_BSP_I2C_EEPROM_DEVICE_NAME "eeprom"
282#define RTEMS_BSP_I2C_EEPROM_DEVICE_PATH "/dev/i2c1.eeprom"
283
284/*
285 * SPI Flash device name
286 */
287#define RTEMS_BSP_SPI_FLASH_DEVICE_NAME "flash"
288#define RTEMS_BSP_SPI_FLASH_DEVICE_PATH "/dev/spi.flash"
289
290#ifdef __cplusplus
291}
292#endif
293
294#endif /* ASM */
295
296#endif /* GEN83xx */
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