[f610e83f] | 1 | /*===============================================================*\ |
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| 2 | | Project: RTEMS generic MPC83xx BSP | |
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| 3 | +-----------------------------------------------------------------+ |
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| 4 | | Copyright (c) 2007 | |
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| 5 | | Embedded Brains GmbH | |
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| 6 | | Obere Lagerstr. 30 | |
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| 7 | | D-82178 Puchheim | |
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| 8 | | Germany | |
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| 9 | | rtems@embedded-brains.de | |
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| 10 | +-----------------------------------------------------------------+ |
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| 11 | | The license and distribution terms for this file may be | |
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| 12 | | found in the file LICENSE in this distribution or at | |
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| 13 | | | |
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| 14 | | http://www.rtems.com/license/LICENSE. | |
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| 15 | | | |
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| 16 | +-----------------------------------------------------------------+ |
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| 17 | | this file contains board specific definitions | |
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| 18 | \*===============================================================*/ |
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| 19 | |
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| 20 | #ifndef __GEN83xx_BSP_h |
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| 21 | #define __GEN83xx_BSP_h |
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| 22 | |
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| 23 | /* |
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| 24 | * distinguish board characteristics |
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| 25 | */ |
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| 26 | /* |
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| 27 | * for Freescale MPC8349 EAMDS |
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| 28 | */ |
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| 29 | #if defined(MPC8349EAMDS) |
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| 30 | /* |
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| 31 | * two DUART channels supported |
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| 32 | */ |
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| 33 | #define GEN83xx_DUART_AVAIL_MASK 0x03 |
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| 34 | |
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| 35 | /* we need the low level initialization in start.S*/ |
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| 36 | #define NEED_LOW_LEVEL_INIT |
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| 37 | /* |
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| 38 | * clocking infos |
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| 39 | */ |
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| 40 | #define BSP_CLKIN_FRQ 66000000L |
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| 41 | #define BSP_SYSPLL_MF 4 /* FIXME: derive from clock register */ |
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| 42 | |
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[e35c696] | 43 | /* |
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| 44 | * Reset configuration words |
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| 45 | */ |
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| 46 | #define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 | \ |
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| 47 | RCWLR_DDRCM_1_1 | \ |
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| 48 | RCWLR_SPMF(4) | \ |
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| 49 | RCWLR_COREPLL(4)) |
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| 50 | |
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| 51 | #define RESET_CONF_WRD_H (RCWHR_PCI_HOST | \ |
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| 52 | RCWHR_PCI_32 | \ |
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| 53 | RCWHR_PCI1ARB_EN | \ |
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| 54 | RCWHR_PCI2ARB_EN | \ |
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| 55 | RCWHR_CORE_EN | \ |
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| 56 | RCWHR_BMS_LOW | \ |
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| 57 | RCWHR_BOOTSEQ_NONE | \ |
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| 58 | RCWHR_SW_DIS | \ |
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| 59 | RCWHR_ROMLOC_LB16 | \ |
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| 60 | RCWHR_TSEC1M_GMII | \ |
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| 61 | RCWHR_TSEC2M_GMII | \ |
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| 62 | RCWHR_ENDIAN_BIG | \ |
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| 63 | RCWHR_LALE_NORM | \ |
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| 64 | RCWHR_LDP_PAR) |
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| 65 | /* |
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| 66 | * for JPK HSC_CM01 |
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| 67 | */ |
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[7d7d2e93] | 68 | #elif defined(HSC_CM01) |
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[e35c696] | 69 | /* |
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| 70 | * one DUART channel (UART1) supported |
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| 71 | */ |
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| 72 | #define GEN83xx_DUART_AVAIL_MASK 0x01 |
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| 73 | |
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| 74 | /* we need the low level initialization in start.S*/ |
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| 75 | #define NEED_LOW_LEVEL_INIT |
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| 76 | /* |
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| 77 | * clocking infos |
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| 78 | */ |
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| 79 | #define BSP_CLKIN_FRQ 66000000L |
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| 80 | #define BSP_SYSPLL_MF 4 /* FIXME: derive from clock register */ |
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| 81 | |
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| 82 | /* |
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| 83 | * Reset configuration words |
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| 84 | */ |
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| 85 | #define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 | \ |
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| 86 | RCWLR_DDRCM_1_1 | \ |
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| 87 | RCWLR_SPMF(4) | \ |
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| 88 | RCWLR_COREPLL(4)) |
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| 89 | |
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| 90 | #define RESET_CONF_WRD_H (RCWHR_PCI_HOST | \ |
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| 91 | RCWHR_PCI_32 | \ |
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| 92 | RCWHR_PCI1ARB_EN | \ |
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| 93 | RCWHR_PCI2ARB_EN | \ |
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| 94 | RCWHR_CORE_EN | \ |
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| 95 | RCWHR_BMS_LOW | \ |
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| 96 | RCWHR_BOOTSEQ_NONE | \ |
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| 97 | RCWHR_SW_DIS | \ |
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| 98 | RCWHR_ROMLOC_LB16 | \ |
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| 99 | RCWHR_TSEC1M_RGMII | \ |
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| 100 | RCWHR_TSEC2M_GMII | \ |
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| 101 | RCWHR_ENDIAN_BIG | \ |
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| 102 | RCWHR_LALE_NORM | \ |
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| 103 | RCWHR_LDP_PAR) |
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| 104 | #else |
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| 105 | #error "board type not defined" |
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| 106 | #endif |
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| 107 | |
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| 108 | /* |
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| 109 | * for JPK HSC_CM01 and freescale MPC8349EAMDS |
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| 110 | */ |
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| 111 | #if defined(MPC8349EAMDS) || defined(HSC_CM01) |
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[f610e83f] | 112 | /* |
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| 113 | * address range definitions |
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| 114 | */ |
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[e35c696] | 115 | /* ROM definitions (8 MB, mirrored multiple times) */ |
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| 116 | #define ROM_START 0xFE000000 |
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| 117 | #define ROM_SIZE 0x02000000 |
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[f610e83f] | 118 | #define ROM_END (ROM_START+ROM_SIZE-1) |
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| 119 | #define BOOT_START ROM_START |
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| 120 | #define BOOT_END ROM_END |
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| 121 | |
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| 122 | /* SDRAM definitions (256 MB) */ |
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| 123 | #define RAM_START 0x00000000 |
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| 124 | #define RAM_SIZE 0x10000000 |
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| 125 | #define RAM_END (RAM_START+RAM_SIZE-1) |
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| 126 | |
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[e35c696] | 127 | |
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[f610e83f] | 128 | /* working internal memory map base address */ |
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| 129 | #define IMMRBAR 0xE0000000 |
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| 130 | |
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| 131 | /* |
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| 132 | * working values for various registers, used in start/start.S |
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| 133 | */ |
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| 134 | /* |
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| 135 | * Local Access Windows |
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| 136 | * FIXME: decode bit settings |
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| 137 | */ |
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| 138 | #define LBLAWBAR0_VAL 0xFE000000 |
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| 139 | #define LBLAWAR0_VAL 0x80000016 |
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| 140 | #define LBLAWBAR1_VAL 0xF8000000 |
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| 141 | #define LBLAWAR1_VAL 0x8000000E |
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| 142 | #define LBLAWBAR2_VAL 0xF0000000 |
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| 143 | #define LBLAWAR2_VAL 0x80000019 |
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| 144 | #define DDRLAWBAR0_VAL 0x00000000 |
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| 145 | #define DDRLAWAR0_VAL 0x8000001B |
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| 146 | /* |
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| 147 | * Local Bus (Memory) Controller |
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| 148 | * FIXME: decode bit settings |
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| 149 | */ |
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| 150 | #define BR0_VAL 0xFE001001 |
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| 151 | #define OR0_VAL 0xFF806FF7 |
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| 152 | #define BR1_VAL 0xF8000801 |
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| 153 | #define OR1_VAL 0xFFFFE8F0 |
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| 154 | #define BR2_VAL 0xF0001861 |
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| 155 | #define OR2_VAL 0xFC006901 |
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| 156 | /* |
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| 157 | * SDRAM registers |
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| 158 | * FIXME: decode bit settings |
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| 159 | */ |
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| 160 | #define MRPTR_VAL 0x20000000 |
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| 161 | #define LSRT_VAL 0x32000000 |
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| 162 | #define LSDMR_VAL 0x4062D733 |
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| 163 | #define LCRR_VAL 0x80000004 |
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| 164 | |
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| 165 | /* |
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| 166 | * DDR-SDRAM registers |
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| 167 | * FIXME: decode bit settings |
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| 168 | */ |
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| 169 | #define CS2_BNDS_VAL 0x00000007 |
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| 170 | #define CS3_BNDS_VAL 0x0008000F |
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| 171 | #define CS2_CONFIG_VAL 0x80000101 |
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| 172 | #define CS3_CONFIG_VAL 0x80000101 |
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| 173 | #define TIMING_CFG_1_VAL 0x36333321 |
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| 174 | #define TIMING_CFG_2_VAL 0x00000800 |
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| 175 | #define DDR_SDRAM_CFG_VAL 0xC2000000 |
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| 176 | #define DDR_SDRAM_MODE_VAL 0x00000022 |
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| 177 | #define DDR_SDRAM_INTTVL_VAL 0x045B0100 |
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| 178 | #define DDR_SDRAM_CLK_CNTL_VAL 0x00000000 |
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| 179 | |
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| 180 | #else |
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| 181 | #error "board type not defined" |
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| 182 | #endif |
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| 183 | |
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| 184 | #ifndef ASM |
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| 185 | |
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| 186 | #ifdef __cplusplus |
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| 187 | extern "C" { |
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| 188 | #endif |
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| 189 | |
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| 190 | #include "bspopts.h" |
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| 191 | |
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| 192 | #include <rtems.h> |
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| 193 | #include <rtems/console.h> |
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| 194 | #include <rtems/clockdrv.h> |
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| 195 | #include <bsp/irq.h> |
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| 196 | #include <bsp/vectors.h> |
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| 197 | |
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| 198 | /* miscellaneous stuff assumed to exist */ |
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| 199 | |
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| 200 | extern rtems_configuration_table BSP_Configuration; |
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| 201 | /* |
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| 202 | * We need to decide how much memory will be non-cacheable. This |
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| 203 | * will mainly be memory that will be used in DMA (network and serial |
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| 204 | * buffers). |
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| 205 | */ |
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| 206 | /* |
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| 207 | * Stuff for Time Test 27 |
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| 208 | */ |
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| 209 | #define MUST_WAIT_FOR_INTERRUPT 0 |
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| 210 | |
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| 211 | /* |
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| 212 | * Device Driver Table Entries |
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| 213 | */ |
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| 214 | |
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| 215 | /* |
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| 216 | * NOTE: Use the standard Console driver entry |
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| 217 | */ |
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| 218 | #define BSP_UART1_MINOR 0 |
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| 219 | #define BSP_UART2_MINOR 1 |
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| 220 | |
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| 221 | /* |
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| 222 | * NOTE: Use the standard Clock driver entry |
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| 223 | */ |
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| 224 | |
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| 225 | /* |
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| 226 | * indicate, that BSP has no IDE driver |
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| 227 | */ |
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| 228 | #undef RTEMS_BSP_HAS_IDE_DRIVER |
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| 229 | |
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| 230 | /* |
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| 231 | * How many libio files we want |
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| 232 | */ |
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| 233 | #define BSP_LIBIO_MAX_FDS 20 |
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| 234 | |
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| 235 | /* misc macros */ |
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| 236 | #define BSP_ARRAY_CNT(arr) (sizeof(arr)/sizeof(arr[0])) |
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| 237 | |
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| 238 | /* functions */ |
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| 239 | |
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| 240 | void bsp_cleanup(void); |
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[e35c696] | 241 | rtems_status_code bsp_register_i2c(void); |
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[55a685b] | 242 | rtems_status_code bsp_register_spi(void); |
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[f610e83f] | 243 | |
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| 244 | /* console modes (only termios) */ |
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| 245 | #ifdef PRINTK_MINOR |
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| 246 | #undef PRINTK_MINOR |
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| 247 | #endif |
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| 248 | #define PRINTK_MINOR BSP_UART1_MINOR |
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| 249 | |
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| 250 | #define SINGLE_CHAR_MODE |
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| 251 | #define UARTS_USE_TERMIOS_INT 1 |
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| 252 | |
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| 253 | /* |
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| 254 | * Convert decrement value to tenths of microsecnds (used by |
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| 255 | * shared timer driver). |
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| 256 | * |
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| 257 | * + CPU has a csb_clock bus, |
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| 258 | * + There are 4 bus cycles per click |
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| 259 | * + We return value in 1/10 microsecond units. |
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| 260 | * Modified following equation to integer equation to remove |
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| 261 | * floating point math. |
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| 262 | * (int) ((float)(_value) / ((XLB_CLOCK/1000000 * 0.1) / 4.0)) |
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| 263 | */ |
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| 264 | #define BSP_CSB_CLK_FRQ (BSP_CLKIN_FRQ * BSP_SYSPLL_MF) |
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| 265 | #define BSP_Convert_decrementer( _value ) \ |
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| 266 | (int) (((_value) * 4000) / (BSP_CSB_CLK_FRQ/10000)) |
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| 267 | |
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| 268 | /* |
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| 269 | * Network driver configuration |
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| 270 | */ |
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| 271 | struct rtems_bsdnet_ifconfig; |
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| 272 | extern int BSP_tsec_attach(struct rtems_bsdnet_ifconfig *config,int attaching); |
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| 273 | #define RTEMS_BSP_NETWORK_DRIVER_NAME "tsec1" |
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| 274 | #define RTEMS_BSP_NETWORK_DRIVER_ATTACH BSP_tsec_attach |
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| 275 | |
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| 276 | #define RTEMS_BSP_NETWORK_DRIVER_NAME2 "tsec2" |
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| 277 | |
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[e35c696] | 278 | /* |
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| 279 | * i2c EEPROM device name |
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| 280 | */ |
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| 281 | #define RTEMS_BSP_I2C_EEPROM_DEVICE_NAME "eeprom" |
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| 282 | #define RTEMS_BSP_I2C_EEPROM_DEVICE_PATH "/dev/i2c1.eeprom" |
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| 283 | |
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[55a685b] | 284 | /* |
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| 285 | * SPI Flash device name |
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| 286 | */ |
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| 287 | #define RTEMS_BSP_SPI_FLASH_DEVICE_NAME "flash" |
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| 288 | #define RTEMS_BSP_SPI_FLASH_DEVICE_PATH "/dev/spi.flash" |
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| 289 | |
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[f610e83f] | 290 | #ifdef __cplusplus |
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| 291 | } |
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| 292 | #endif |
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| 293 | |
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| 294 | #endif /* ASM */ |
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| 295 | |
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| 296 | #endif /* GEN83xx */ |
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