source: rtems/c/src/lib/libbsp/powerpc/gen5200/vectors/vectors.h @ 0332481

Last change on this file since 0332481 was 0332481, checked in by Joel Sherrill <joel.sherrill@…>, on Mar 12, 2007 at 11:21:23 AM

2007-03-12 Joel Sherrill <joel@…>

  • clock/clock.c, console/console.c, ide/pcmcia_ide.c, irq/irq.c, irq/irq.h, irq/irq_asm.S, irq/irq_init.c, nvram/nvram.c, nvram/nvram.h, slicetimer/slicetimer.c, startup/bspstart.c, vectors/vectors.h, vectors/vectors_init.c: Correct license URL and/or fix mistake in copyright notice. Both of these mistakes appear to be from code submitted after these changes were made previously.
  • Property mode set to 100644
File size: 4.1 KB
Line 
1/*---------------------------------------------------------------------------*/
2/* Actually no changes made in this file but its presence is required in the */
3/* cygwin /shared directory due to development purposes!                     */
4/*                                                                           */
5/* IPR Engineering, 07/17/2003                                               */
6/*---------------------------------------------------------------------------*/
7
8/*
9 * vectors.h Exception frame related contant and API.
10 *
11 *  This include file describe the data structure and the functions implemented
12 *  by rtems to handle exceptions.
13 *
14 *  CopyRight (C) 1999 valette@crf.canon.fr
15 *
16 *  The license and distribution terms for this file may be
17 *  found in found in the file LICENSE in this distribution or at
18 *  http://www.rtems.com/license/LICENSE.
19 *
20 *  vectors.h,v 1.2 2002/05/14 17:10:17 joel Exp
21 */
22#ifndef LIBBSP_POWERPC_MCP750_VECTORS_H
23#define LIBBSP_POWERPC_MCP750_VECTORS_H
24
25/*
26 * The callee (high level exception code written in C)
27 * will store the Link Registers (return address) at entry r1 + 4 !!!.
28 * So let room for it!!!.
29 */
30#define LINK_REGISTER_CALLEE_UPDATE_ROOM 4
31#define SRR0_FRAME_OFFSET 8
32#define SRR1_FRAME_OFFSET 12
33#define EXCEPTION_NUMBER_OFFSET 16
34#define GPR0_OFFSET 20
35#define GPR1_OFFSET 24
36#define GPR2_OFFSET 28
37#define GPR3_OFFSET 32
38#define GPR4_OFFSET 36
39#define GPR5_OFFSET 40
40#define GPR6_OFFSET 44
41#define GPR7_OFFSET 48
42#define GPR8_OFFSET 52
43#define GPR9_OFFSET 56
44#define GPR10_OFFSET 60
45#define GPR11_OFFSET 64
46#define GPR12_OFFSET 68
47#define GPR13_OFFSET 72
48#define GPR14_OFFSET 76
49#define GPR15_OFFSET 80
50#define GPR16_OFFSET 84
51#define GPR17_OFFSET 88
52#define GPR18_OFFSET 92
53#define GPR19_OFFSET 96
54#define GPR20_OFFSET 100
55#define GPR21_OFFSET 104
56#define GPR22_OFFSET 108
57#define GPR23_OFFSET 112
58#define GPR24_OFFSET 116
59#define GPR25_OFFSET 120
60#define GPR26_OFFSET 124
61#define GPR27_OFFSET 128
62#define GPR28_OFFSET 132
63#define GPR29_OFFSET 136
64#define GPR30_OFFSET 140
65#define GPR31_OFFSET 144
66#define EXC_CR_OFFSET 148
67#define EXC_CTR_OFFSET 152
68#define EXC_XER_OFFSET 156
69#define EXC_LR_OFFSET 160
70#define EXC_MSR_OFFSET 164
71#define EXC_DAR_OFFSET 168
72/*
73 * maintain the EABI requested 8 bytes aligment
74 * As SVR4 ABI requires 16, make it 16 (as some
75 * exception may need more registers to be processed...)
76 */
77#define    EXCEPTION_FRAME_END 176
78
79#ifndef ASM
80/*
81 * default raw exception handlers
82 */
83
84extern  void default_exception_vector_code_prolog();
85extern  int  default_exception_vector_code_prolog_size;
86
87/* codemove is like memmove, but it also gets the cache line size
88 * as 4th parameter to synchronize them. If this last parameter is
89 * zero, it performs more or less like memmove. No copy is performed if
90 * source and destination addresses are equal. However the caches
91 * are synchronized. Note that the size is always rounded up to the
92 * next mutiple of 4.
93 */
94extern void * codemove(void *, const void *, unsigned int, unsigned long);
95extern void initialize_exceptions();
96
97typedef struct {
98  unsigned      EXC_SRR0;
99  unsigned      EXC_SRR1;
100  unsigned      _EXC_number;
101  unsigned      GPR0;
102  unsigned      GPR1;
103  unsigned      GPR2;
104  unsigned      GPR3;
105  unsigned      GPR4;
106  unsigned      GPR5;
107  unsigned      GPR6;
108  unsigned      GPR7;
109  unsigned      GPR8;
110  unsigned      GPR9;
111  unsigned      GPR10;
112  unsigned      GPR11;
113  unsigned      GPR12;
114  unsigned      GPR13;
115  unsigned      GPR14;
116  unsigned      GPR15;
117  unsigned      GPR16;
118  unsigned      GPR17;
119  unsigned      GPR18;
120  unsigned      GPR19;
121  unsigned      GPR20;
122  unsigned      GPR21;
123  unsigned      GPR22;
124  unsigned      GPR23;
125  unsigned      GPR24;
126  unsigned      GPR25;
127  unsigned      GPR26;
128  unsigned      GPR27;
129  unsigned      GPR28;
130  unsigned      GPR29;
131  unsigned      GPR30;
132  unsigned      GPR31;
133  unsigned      EXC_CR;
134  unsigned      EXC_CTR;
135  unsigned      EXC_XER;
136  unsigned      EXC_LR;
137  unsigned      EXC_MSR;
138  unsigned      EXC_DAR;
139}BSP_Exception_frame;
140
141
142typedef void (*exception_handler_t) (BSP_Exception_frame* excPtr);
143extern exception_handler_t globalExceptHdl;
144/*
145 * Compatibility with pc386
146 */
147typedef BSP_Exception_frame CPU_Exception_frame;
148typedef exception_handler_t cpuExcHandlerType;
149
150#endif /* ASM */
151
152#endif /* LIBBSP_POWERPC_MCP750_VECTORS_H */
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