1 | /*===============================================================*\ |
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2 | | Project: RTEMS generic MPC5200 BSP | |
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3 | +-----------------------------------------------------------------+ |
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4 | | Partially based on the code references which are named below. | |
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5 | | Adaptions, modifications, enhancements and any recent parts of | |
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6 | | the code are: | |
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7 | | Copyright (c) 2005 | |
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8 | | Embedded Brains GmbH | |
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9 | | Obere Lagerstr. 30 | |
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10 | | D-82178 Puchheim | |
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11 | | Germany | |
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12 | | rtems@embedded-brains.de | |
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13 | +-----------------------------------------------------------------+ |
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14 | | The license and distribution terms for this file may be | |
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15 | | found in the file LICENSE in this distribution or at | |
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16 | | | |
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17 | | http://www.rtems.com/license/LICENSE. | |
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18 | | | |
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19 | +-----------------------------------------------------------------+ |
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20 | | this file contains the irq controller handler | |
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21 | \*===============================================================*/ |
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22 | /***********************************************************************/ |
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23 | /* */ |
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24 | /* Module: vectors.s */ |
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25 | /* Date: 07/17/2003 */ |
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26 | /* Purpose: RTEMS assembly code for PowerPC exception veneers */ |
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27 | /* */ |
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28 | /*---------------------------------------------------------------------*/ |
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29 | /* */ |
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30 | /* Description: */ |
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31 | /* */ |
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32 | /*---------------------------------------------------------------------*/ |
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33 | /* */ |
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34 | /* Code */ |
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35 | /* References: This file contains the assembly code for the */ |
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36 | /* PowerPC exception veneers for RTEMS. */ |
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37 | /* Module: vectors.s */ |
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38 | /* Project: RTEMS 4.6.0pre1 / MCF8260ads BSP */ |
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39 | /* Version 1.2 */ |
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40 | /* Date: 04/18/2002 */ |
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41 | /* */ |
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42 | /* Author(s) / Copyright(s): */ |
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43 | /* */ |
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44 | /* (c) 1999, Eric Valette valette@crf.canon.fr */ |
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45 | /* */ |
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46 | /*---------------------------------------------------------------------*/ |
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47 | /* */ |
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48 | /* Partially based on the code references which are named above. */ |
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49 | /* Adaptions, modifications, enhancements and any recent parts of */ |
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50 | /* the code are under the right of */ |
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51 | /* */ |
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52 | /* IPR Engineering, Dachauer StraÃe 38, D-80335 MÃŒnchen */ |
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53 | /* Copyright(C) 2003 */ |
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54 | /* */ |
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55 | /*---------------------------------------------------------------------*/ |
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56 | /* */ |
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57 | /* IPR Engineering makes no representation or warranties with */ |
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58 | /* respect to the performance of this computer program, and */ |
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59 | /* specifically disclaims any responsibility for any damages, */ |
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60 | /* special or consequential, connected with the use of this program. */ |
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61 | /* */ |
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62 | /*---------------------------------------------------------------------*/ |
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63 | /* */ |
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64 | /* Version history: 1.0 */ |
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65 | /* */ |
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66 | /***********************************************************************/ |
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67 | |
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68 | #include <rtems/asm.h> |
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69 | #include <rtems/score/cpu.h> |
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70 | #include "vectors.h" |
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71 | |
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72 | #define SYNC \ |
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73 | sync; \ |
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74 | isync |
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75 | |
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76 | .text |
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77 | .p2align 5 |
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78 | |
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79 | PUBLIC_VAR(default_exception_vector_code_prolog) |
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80 | SYM (default_exception_vector_code_prolog): |
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81 | /* |
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82 | * let room for exception frame |
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83 | */ |
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84 | stwu r1, - (EXCEPTION_FRAME_END)(r1) |
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85 | stw r3, GPR3_OFFSET(r1) |
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86 | stw r2, GPR2_OFFSET(r1) |
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87 | mflr r2 |
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88 | stw r2, EXC_LR_OFFSET(r1) |
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89 | bl 0f |
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90 | 0: /* |
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91 | * r3 = exception vector entry point |
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92 | * (256 * vector number) + few instructions |
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93 | */ |
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94 | mflr r3 |
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95 | /* |
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96 | * r3 = r3 >> 8 = vector |
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97 | */ |
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98 | srwi r3,r3,8 |
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99 | ba push_normalized_frame |
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100 | |
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101 | PUBLIC_VAR (default_exception_vector_code_prolog_size) |
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102 | |
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103 | default_exception_vector_code_prolog_size= . - default_exception_vector_code_prolog |
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104 | |
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105 | .p2align 5 |
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106 | PUBLIC_VAR (push_normalized_frame) |
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107 | SYM (push_normalized_frame): |
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108 | stw r3, EXCEPTION_NUMBER_OFFSET(r1) |
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109 | stw r0, GPR0_OFFSET(r1) |
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110 | mfsrr0 r2 |
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111 | stw r2, SRR0_FRAME_OFFSET(r1) |
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112 | mfsrr1 r3 |
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113 | stw r3, SRR1_FRAME_OFFSET(r1) |
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114 | /* |
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115 | * Save general purpose registers |
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116 | * Already saved in prolog : R1, R2, R3, LR. |
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117 | * Saved a few line above : R0 |
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118 | * |
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119 | * Manual says that "stmw" instruction may be slower than |
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120 | * series of individual "stw" but who cares about performance |
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121 | * for the DEFAULT exception handler? |
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122 | */ |
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123 | stmw r4, GPR4_OFFSET(r1) /* save R4->R31 */ |
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124 | |
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125 | mfcr r31 |
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126 | stw r31, EXC_CR_OFFSET(r1) |
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127 | mfctr r30 |
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128 | stw r30, EXC_CTR_OFFSET(r1) |
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129 | mfxer r28 |
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130 | stw r28, EXC_XER_OFFSET(r1) |
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131 | /* |
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132 | * compute SP at exception entry |
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133 | */ |
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134 | addi r2, r1, EXCEPTION_FRAME_END |
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135 | /* |
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136 | * store it at the right place |
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137 | */ |
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138 | stw r2, GPR1_OFFSET(r1) |
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139 | |
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140 | /* |
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141 | * Enable data and instruction address translation, exception nesting |
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142 | */ |
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143 | mfmsr r3 |
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144 | ori r3,r3, MSR_RI|MSR_DR /*| MSR_IR*/ |
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145 | mtmsr r3 |
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146 | SYNC |
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147 | |
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148 | /* |
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149 | * Call C exception handler |
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150 | */ |
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151 | /* |
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152 | * store the execption frame address in r3 (first param) |
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153 | */ |
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154 | addi r3, r1, 0x8 |
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155 | /* |
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156 | * globalExceptHdl(r3) |
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157 | */ |
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158 | addis r4, 0, globalExceptHdl@ha |
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159 | lwz r5, globalExceptHdl@l(r4) |
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160 | mtlr r5 |
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161 | blrl |
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162 | /* |
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163 | * Restore registers status |
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164 | */ |
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165 | lwz r31, EXC_CR_OFFSET(r1) |
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166 | mtcr r31 |
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167 | lwz r30, EXC_CTR_OFFSET(r1) |
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168 | mtctr r30 |
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169 | lwz r29, EXC_LR_OFFSET(r1) |
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170 | mtlr r29 |
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171 | lwz r28, EXC_XER_OFFSET(r1) |
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172 | mtxer r28 |
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173 | |
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174 | lmw r4, GPR4_OFFSET(r1) |
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175 | lwz r2, GPR2_OFFSET(r1) |
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176 | lwz r0, GPR0_OFFSET(r1) |
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177 | |
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178 | /* |
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179 | * Disable data and instruction translation. Make path non recoverable... |
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180 | */ |
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181 | mfmsr r3 |
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182 | xori r3, r3, MSR_RI|MSR_DR /*| MSR_IR */ |
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183 | mtmsr r3 |
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184 | SYNC |
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185 | |
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186 | /* |
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187 | * Restore rfi related settings |
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188 | */ |
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189 | |
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190 | lwz r3, SRR1_FRAME_OFFSET(r1) |
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191 | mtsrr1 r3 |
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192 | lwz r3, SRR0_FRAME_OFFSET(r1) |
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193 | mtsrr0 r3 |
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194 | |
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195 | lwz r3, GPR3_OFFSET(r1) |
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196 | addi r1,r1, EXCEPTION_FRAME_END |
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197 | SYNC |
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198 | rfi |
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199 | |
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200 | .section .vectors,"awx",@progbits |
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201 | |
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202 | PUBLIC_VAR (__vectors) |
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203 | SYM (__vectors): |
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204 | bl start |
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205 | .rep 63 |
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206 | .long 0x04000400 |
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207 | .endr |
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208 | __vec2: b __vec2 |
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209 | .rep 63 |
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210 | .long 0x04000400 |
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211 | .endr |
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212 | __vec3: b __vec3 |
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213 | .rep 63 |
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214 | .long 0x04000400 |
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215 | .endr |
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216 | __vec4: b __vec4 |
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217 | .rep 63 |
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218 | .long 0x04000400 |
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219 | .endr |
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220 | __vec5: b __vec5 |
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221 | .rep 63 |
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222 | .long 0x04000400 |
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223 | .endr |
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224 | __vec6: b __vec6 |
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225 | .rep 63 |
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226 | .long 0x04000400 |
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227 | .endr |
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228 | __vec7: b __vec7 |
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229 | .rep 63 |
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230 | .long 0x04000400 |
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231 | .endr |
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232 | __vec8: b __vec8 |
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233 | .rep 63 |
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234 | .long 0x04000400 |
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235 | .endr |
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236 | __vec9: b __vec9 |
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237 | .rep 63 |
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238 | .long 0x04000400 |
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239 | .endr |
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240 | __veca: b __veca |
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241 | .rep 63 |
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242 | .long 0x04000400 |
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243 | .endr |
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244 | __vecb: b __vecb |
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245 | .rep 63 |
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246 | .long 0x04000400 |
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247 | .endr |
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248 | __vecc: b __vecc |
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249 | .rep 63 |
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250 | .long 0x04000400 |
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251 | .endr |
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252 | __vecd: b __vecd |
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253 | .rep 63 |
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254 | .long 0x04000400 |
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255 | .endr |
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256 | __vece: b __vece |
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257 | .rep 63 |
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258 | .long 0x04000400 |
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259 | .endr |
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260 | __vecf: b __vecf |
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261 | .rep 63+1024 |
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262 | .long 0x04000400 |
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263 | .endr |
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264 | |
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