source: rtems/c/src/lib/libbsp/powerpc/gen5200/vectors/asm_utils.S @ ca680bc5

4.104.114.84.95
Last change on this file since ca680bc5 was ca680bc5, checked in by Ralf Corsepius <ralf.corsepius@…>, on 12/31/05 at 05:09:26

New (CVS import Thomas Doerfler <Thomas.Doerfler@…>'s
submission).
  • Property mode set to 100644
File size: 1.7 KB
Line 
1/*---------------------------------------------------------------------------*/
2/* Actually no changes made in this file but its presence is required in the */
3/* cygwin /shared directory due to development purposes!                     */
4/*                                                                           */
5/* IPR Engineering, 07/17/2003                                               */
6/*---------------------------------------------------------------------------*/
7
8/*
9 *  asm_utils.s
10 *
11 *  asm_utils.S,v 1.2 2002/04/18 20:55:36 joel Exp
12 *
13 *  Copyright (C) 1999 Eric Valette (valette@crf.canon.fr)
14 *
15 *  This file contains the low-level support for moving exception
16 *  exception code to appropriate location.
17 *
18 */
19
20#include <rtems/asm.h>
21#include <rtems/score/cpu.h>
22#include <libcpu/io.h>
23
24        .globl  codemove
25codemove:
26        .type   codemove,@function
27/* r3 dest, r4 src, r5 length in bytes, r6 cachelinesize */
28        cmplw   cr1,r3,r4
29        addi    r0,r5,3
30        srwi.   r0,r0,2
31        beq     cr1,4f  /* In place copy is not necessary */
32        beq     7f      /* Protect against 0 count */
33        mtctr   r0
34        bge     cr1,2f
35       
36        la      r8,-4(r4)
37        la      r7,-4(r3)
381:      lwzu    r0,4(r8)
39        stwu    r0,4(r7)       
40        bdnz    1b
41        b       4f
42
432:      slwi    r0,r0,2
44        add     r8,r4,r0
45        add     r7,r3,r0
463:      lwzu    r0,-4(r8)
47        stwu    r0,-4(r7)
48        bdnz    3b
49       
50/* Now flush the cache: note that we must start from a cache aligned
51 * address. Otherwise we might miss one cache line.
52 */
534:      cmpwi   r6,0
54        add     r5,r3,r5
55        beq     7f      /* Always flush prefetch queue in any case */
56        subi    r0,r6,1
57        andc    r3,r3,r0
58        mr      r4,r3
595:      cmplw   r4,r5   
60        dcbst   0,r4
61        add     r4,r4,r6
62        blt     5b
63        sync            /* Wait for all dcbst to complete on bus */
64        mr      r4,r3
656:      cmplw   r4,r5   
66        icbi    0,r4
67        add     r4,r4,r6
68        blt     6b
697:      sync            /* Wait for all icbi to complete on bus */
70        isync
71        blr
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