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source: rtems/c/src/lib/libbsp/powerpc/gen5200/startup/cpuinit.c @ a877cc8e

Last change on this file since a877cc8e was a877cc8e, checked in by Ralf Corsepius <ralf.corsepius@…>, on 10/17/06 at 02:46:07
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File size: 7.4 KB

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1	/===============================================================\
2	\| Project: RTEMS generic MPC5200 BSP \|
3	+-----------------------------------------------------------------+
4	\| Partially based on the code references which are named below. \|
5	\| Adaptions, modifications, enhancements and any recent parts of \|
6	\| the code are: \|
7	\| Copyright (c) 2005 \|
8	\| Embedded Brains GmbH \|
9	\| Obere Lagerstr. 30 \|
10	\| D-82178 Puchheim \|
11	\| Germany \|
12	\| rtems@embedded-brains.de \|
13	+-----------------------------------------------------------------+
14	\| The license and distribution terms for this file may be \|
15	\| found in the file LICENSE in this distribution or at \|
16	\| \|
17	\| http://www.rtems.com/license/LICENSE. \|
18	\| \|
19	+-----------------------------------------------------------------+
20	\| this file contains the code to initialize the cpu \|
21	\===============================================================/
22	/***********************************************************************/
23	/* */
24	/* Module: cpuinit.c */
25	/* Date: 07/17/2003 */
26	/* Purpose: RTEMS MPC5x00 C level startup code */
27	/* */
28	/---------------------------------------------------------------------/
29	/* */
30	/* Description: This file contains additional functions for */
31	/* initializing the MPC5x00 CPU */
32	/* */
33	/---------------------------------------------------------------------/
34	/* */
35	/* Code */
36	/* References: MPC8260ads additional CPU initialization */
37	/* Module: cpuinit.c */
38	/* Project: RTEMS 4.6.0pre1 / MCF8260ads BSP */
39	/* Version 1.1 */
40	/* Date: 10/22/2002 */
41	/* */
42	/* Author(s) / Copyright(s): */
43	/* */
44	/* Written by Jay Monkman (jmonkman@frasca.com) */
45	/* */
46	/---------------------------------------------------------------------/
47	/* */
48	/* Partially based on the code references which are named above. */
49	/* Adaptions, modifications, enhancements and any recent parts of */
50	/* the code are under the right of */
51	/* */
52	/* IPR Engineering, Dachauer StraÃe 38, D-80335 MÃŒnchen */
53	/* Copyright(C) 2003 */
54	/* */
55	/---------------------------------------------------------------------/
56	/* */
57	/* IPR Engineering makes no representation or warranties with */
58	/* respect to the performance of this computer program, and */
59	/* specifically disclaims any responsibility for any damages, */
60	/* special or consequential, connected with the use of this program. */
61	/* */
62	/---------------------------------------------------------------------/
63	/* */
64	/* Version history: 1.0 */
65	/* */
66	/***********************************************************************/
67
68	#include <bsp.h>
69	#include <rtems/powerpc/registers.h>
70	#include "../include/mpc5200.h"
71
72	#include <libcpu/mmu.h>
73	#include <libcpu/spr.h>
74	#include <string.h>
75
76	/* Macros for HID0 access */
77	#define SET_HID0(r) __asm__ volatile ("mtspr 0x3F0,%0\n" ::"r"(r))
78	#define GET_HID0(r) __asm__ volatile ("mfspr %0,0x3F0\n" :"=r"(r))
79
80	#define DBAT_MTSPR(val,name) __MTSPR(val,name);
81	#define SET_DBAT(n,uv,lv) {DBAT_MTSPR(uv,DBAT##n##U);DBAT_MTSPR(lv,DBAT##n##L);}
82	void calc_dbat_regvals(BAT *bat_ptr,
83	uint32_t base_addr,
84	uint32_t size,
85	boolean flg_w,
86	boolean flg_i,
87	boolean flg_m,
88	boolean flg_g,
89	boolean flg_bpp)
90	{
91	uint32_t block_mask;
92	uint32_t end_addr;
93
94	/*
95	* determine block mask, that overlaps the whole block
96	*/
97	end_addr = base_addr+size-1;
98	block_mask = ~0;
99	while ((end_addr & block_mask) != (base_addr & block_mask)) {
100	block_mask <<= 1;
101	}
102
103	bat_ptr->batu.bepi = base_addr >> (32-15);
104	bat_ptr->batu.bl = ~(block_mask >> (28-11));
105	bat_ptr->batu.vs = 1;
106	bat_ptr->batu.vp = 1;
107
108	bat_ptr->batl.brpn = base_addr >> (32-15);
109	bat_ptr->batl.w = flg_w;
110	bat_ptr->batl.i = flg_i;
111	bat_ptr->batl.m = flg_m;
112	bat_ptr->batl.g = flg_g;
113	bat_ptr->batl.pp = flg_bpp;
114	}
115
116	void cpu_init(void)
117	{
118	register unsigned long reg;
119	BAT dbat;
120
121	/*
122	* clear dbat
123	*/
124	memset(&dbat, 0,sizeof(dbat));
125
126	/* enable instruction cache */
127	GET_HID0(reg);
128	reg \|= HID0_ICE;
129	SET_HID0(reg);
130
131
132	/*
133	* set up DBAT registers in MMU
134	*/
135	#if defined (BRS5L)
136	calc_dbat_regvals(&dbat,RAM_START,RAM_SIZE,1,0,0,0,BPP_RW);
137	SET_DBAT(0,dbat.batu,dbat.batl);
138
139	calc_dbat_regvals(&dbat,ROM_START,ROM_SIZE,1,0,0,0,BPP_RX);
140	SET_DBAT(1,dbat.batu,dbat.batl);
141
142	calc_dbat_regvals(&dbat,MBAR,128*1024,1,1,1,1,BPP_RW);
143	SET_DBAT(2,dbat.batu,dbat.batl);
144
145	calc_dbat_regvals(&dbat,DPRAM_START,128*1024,1,1,1,1,BPP_RW);
146	SET_DBAT(3,dbat.batu,dbat.batl);
147	#endif
148	#if defined (HAS_UBOOT)
149	calc_dbat_regvals(&dbat,
150	uboot_bdinfo_ptr->bi_memstart,
151	uboot_bdinfo_ptr->bi_memsize,
152	1,0,0,0,BPP_RW);
153	SET_DBAT(0,dbat.batu,dbat.batl);
154
155	calc_dbat_regvals(&dbat,
156	uboot_bdinfo_ptr->bi_flashstart,
157	uboot_bdinfo_ptr->bi_flashsize,
158	1,0,0,0,BPP_RX);
159	SET_DBAT(1,dbat.batu,dbat.batl);
160
161	calc_dbat_regvals(&dbat,MBAR,128*1024,1,1,1,1,BPP_RW);
162	SET_DBAT(2,dbat.batu,dbat.batl);
163
164	if (uboot_bdinfo_ptr->bi_sramsize != 0) {
165	calc_dbat_regvals(&dbat,
166	uboot_bdinfo_ptr->bi_sramstart,
167	uboot_bdinfo_ptr->bi_sramsize,
168	0,1,1,1,BPP_RW);
169	SET_DBAT(3,dbat.batu,dbat.batl);
170	}
171	#endif
172
173	/*
174	* enable data MMU in MSR
175	*/
176	_write_MSR(_read_MSR() \| MSR_DR);
177
178	#if 1 /* TRACE32 now supports data cache for MGT5x00 */
179	/*
180	* enable data cache
181	*/
182	GET_HID0(reg);
183	reg \|= HID0_DCE;
184	SET_HID0(reg);
185	#endif
186	}

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