1 | /*===============================================================*\ |
---|
2 | | Project: RTEMS generic MPC5200 BSP | |
---|
3 | +-----------------------------------------------------------------+ |
---|
4 | | Partially based on the code references which are named below. | |
---|
5 | | Adaptions, modifications, enhancements and any recent parts of | |
---|
6 | | the code are: | |
---|
7 | | Copyright (c) 2005 | |
---|
8 | | Embedded Brains GmbH | |
---|
9 | | Obere Lagerstr. 30 | |
---|
10 | | D-82178 Puchheim | |
---|
11 | | Germany | |
---|
12 | | rtems@embedded-brains.de | |
---|
13 | +-----------------------------------------------------------------+ |
---|
14 | | The license and distribution terms for this file may be | |
---|
15 | | found in the file LICENSE in this distribution or at | |
---|
16 | | | |
---|
17 | | http://www.rtems.com/license/LICENSE. | |
---|
18 | | | |
---|
19 | +-----------------------------------------------------------------+ |
---|
20 | | this file contains the code to initialize the cpu | |
---|
21 | \*===============================================================*/ |
---|
22 | /***********************************************************************/ |
---|
23 | /* */ |
---|
24 | /* Module: cpuinit.c */ |
---|
25 | /* Date: 07/17/2003 */ |
---|
26 | /* Purpose: RTEMS MPC5x00 C level startup code */ |
---|
27 | /* */ |
---|
28 | /*---------------------------------------------------------------------*/ |
---|
29 | /* */ |
---|
30 | /* Description: This file contains additional functions for */ |
---|
31 | /* initializing the MPC5x00 CPU */ |
---|
32 | /* */ |
---|
33 | /*---------------------------------------------------------------------*/ |
---|
34 | /* */ |
---|
35 | /* Code */ |
---|
36 | /* References: MPC8260ads additional CPU initialization */ |
---|
37 | /* Module: cpuinit.c */ |
---|
38 | /* Project: RTEMS 4.6.0pre1 / MCF8260ads BSP */ |
---|
39 | /* Version 1.1 */ |
---|
40 | /* Date: 10/22/2002 */ |
---|
41 | /* */ |
---|
42 | /* Author(s) / Copyright(s): */ |
---|
43 | /* */ |
---|
44 | /* Written by Jay Monkman (jmonkman@frasca.com) */ |
---|
45 | /* */ |
---|
46 | /*---------------------------------------------------------------------*/ |
---|
47 | /* */ |
---|
48 | /* Partially based on the code references which are named above. */ |
---|
49 | /* Adaptions, modifications, enhancements and any recent parts of */ |
---|
50 | /* the code are under the right of */ |
---|
51 | /* */ |
---|
52 | /* IPR Engineering, Dachauer StraÃe 38, D-80335 MÃŒnchen */ |
---|
53 | /* Copyright(C) 2003 */ |
---|
54 | /* */ |
---|
55 | /*---------------------------------------------------------------------*/ |
---|
56 | /* */ |
---|
57 | /* IPR Engineering makes no representation or warranties with */ |
---|
58 | /* respect to the performance of this computer program, and */ |
---|
59 | /* specifically disclaims any responsibility for any damages, */ |
---|
60 | /* special or consequential, connected with the use of this program. */ |
---|
61 | /* */ |
---|
62 | /*---------------------------------------------------------------------*/ |
---|
63 | /* */ |
---|
64 | /* Version history: 1.0 */ |
---|
65 | /* */ |
---|
66 | /***********************************************************************/ |
---|
67 | |
---|
68 | #include <bsp.h> |
---|
69 | #include <rtems/powerpc/registers.h> |
---|
70 | #include "../include/mpc5200.h" |
---|
71 | |
---|
72 | #include <libcpu/mmu.h> |
---|
73 | #include <libcpu/spr.h> |
---|
74 | #include <string.h> |
---|
75 | |
---|
76 | /* Macros for HID0 access */ |
---|
77 | #define SET_HID0(r) __asm__ volatile ("mtspr 0x3F0,%0\n" ::"r"(r)) |
---|
78 | #define GET_HID0(r) __asm__ volatile ("mfspr %0,0x3F0\n" :"=r"(r)) |
---|
79 | |
---|
80 | #define DBAT_MTSPR(val,name) __MTSPR(val,name); |
---|
81 | #define SET_DBAT(n,uv,lv) {DBAT_MTSPR(uv,DBAT##n##U);DBAT_MTSPR(lv,DBAT##n##L);} |
---|
82 | void calc_dbat_regvals(BAT *bat_ptr, |
---|
83 | uint32_t base_addr, |
---|
84 | uint32_t size, |
---|
85 | boolean flg_w, |
---|
86 | boolean flg_i, |
---|
87 | boolean flg_m, |
---|
88 | boolean flg_g, |
---|
89 | boolean flg_bpp) |
---|
90 | { |
---|
91 | uint32_t block_mask; |
---|
92 | uint32_t end_addr; |
---|
93 | |
---|
94 | /* |
---|
95 | * clear dbat |
---|
96 | */ |
---|
97 | memset(bat_ptr, 0,sizeof(BAT)); |
---|
98 | |
---|
99 | /* |
---|
100 | * determine block mask, that overlaps the whole block |
---|
101 | */ |
---|
102 | end_addr = base_addr+size-1; |
---|
103 | block_mask = ~0; |
---|
104 | while ((end_addr & block_mask) != (base_addr & block_mask)) { |
---|
105 | block_mask <<= 1; |
---|
106 | } |
---|
107 | |
---|
108 | bat_ptr->batu.bepi = base_addr >> (32-15); |
---|
109 | bat_ptr->batu.bl = ~(block_mask >> (28-11)); |
---|
110 | bat_ptr->batu.vs = 1; |
---|
111 | bat_ptr->batu.vp = 1; |
---|
112 | |
---|
113 | bat_ptr->batl.brpn = base_addr >> (32-15); |
---|
114 | bat_ptr->batl.w = flg_w; |
---|
115 | bat_ptr->batl.i = flg_i; |
---|
116 | bat_ptr->batl.m = flg_m; |
---|
117 | bat_ptr->batl.g = flg_g; |
---|
118 | bat_ptr->batl.pp = flg_bpp; |
---|
119 | } |
---|
120 | |
---|
121 | #if defined (BRS5L) |
---|
122 | void cpu_init_bsp(void) |
---|
123 | { |
---|
124 | BAT dbat; |
---|
125 | |
---|
126 | calc_dbat_regvals(&dbat,RAM_START,RAM_SIZE,1,0,0,0,BPP_RW); |
---|
127 | SET_DBAT(0,dbat.batu,dbat.batl); |
---|
128 | |
---|
129 | calc_dbat_regvals(&dbat,ROM_START,ROM_SIZE,1,0,0,0,BPP_RX); |
---|
130 | SET_DBAT(1,dbat.batu,dbat.batl); |
---|
131 | |
---|
132 | calc_dbat_regvals(&dbat,MBAR,128*1024,1,1,1,1,BPP_RW); |
---|
133 | SET_DBAT(2,dbat.batu,dbat.batl); |
---|
134 | |
---|
135 | calc_dbat_regvals(&dbat,DPRAM_START,128*1024,1,1,1,1,BPP_RW); |
---|
136 | SET_DBAT(3,dbat.batu,dbat.batl); |
---|
137 | } |
---|
138 | #elif defined (HAS_UBOOT) |
---|
139 | void cpu_init_bsp(void) |
---|
140 | { |
---|
141 | BAT dbat; |
---|
142 | |
---|
143 | /* |
---|
144 | * Program BAT0 for RAM |
---|
145 | */ |
---|
146 | calc_dbat_regvals(&dbat, |
---|
147 | uboot_bdinfo_ptr->bi_memstart, |
---|
148 | uboot_bdinfo_ptr->bi_memsize, |
---|
149 | 1,0,0,0,BPP_RW); |
---|
150 | SET_DBAT(0,dbat.batu,dbat.batl); |
---|
151 | |
---|
152 | /* |
---|
153 | * Program BAT1 for Flash |
---|
154 | * |
---|
155 | * WARNING!! Some Freescale LITE5200B boards ship with a version of |
---|
156 | * U-Boot that lies about the starting address of Flash. This check |
---|
157 | * corrects that. |
---|
158 | */ |
---|
159 | if ( (uboot_bdinfo_ptr->bi_flashstart + uboot_bdinfo_ptr->bi_flashsize) < |
---|
160 | uboot_bdinfo_ptr->bi_flashstart ) { |
---|
161 | uint32_t start = 0 - uboot_bdinfo_ptr->bi_flashsize; |
---|
162 | calc_dbat_regvals(&dbat, |
---|
163 | start, uboot_bdinfo_ptr->bi_flashsize, 1,0,0,0,BPP_RX); |
---|
164 | } else { |
---|
165 | calc_dbat_regvals(&dbat, |
---|
166 | uboot_bdinfo_ptr->bi_flashstart, |
---|
167 | uboot_bdinfo_ptr->bi_flashsize, |
---|
168 | 1,0,0,0,BPP_RX); |
---|
169 | } |
---|
170 | SET_DBAT(1,dbat.batu,dbat.batl); |
---|
171 | |
---|
172 | /* |
---|
173 | * Program BAT2 for the MBAR |
---|
174 | */ |
---|
175 | calc_dbat_regvals(&dbat,MBAR,128*1024,1,1,1,1,BPP_RW); |
---|
176 | SET_DBAT(2,dbat.batu,dbat.batl); |
---|
177 | |
---|
178 | /* |
---|
179 | * If there is SRAM, program BAT3 for that memory |
---|
180 | */ |
---|
181 | if (uboot_bdinfo_ptr->bi_sramsize != 0) { |
---|
182 | calc_dbat_regvals(&dbat, |
---|
183 | uboot_bdinfo_ptr->bi_sramstart, |
---|
184 | uboot_bdinfo_ptr->bi_sramsize, |
---|
185 | 0,1,1,1,BPP_RW); |
---|
186 | SET_DBAT(3,dbat.batu,dbat.batl); |
---|
187 | } |
---|
188 | } |
---|
189 | #else |
---|
190 | #warning "Using BAT register values set by environment" |
---|
191 | #endif |
---|
192 | |
---|
193 | |
---|
194 | |
---|
195 | void cpu_init(void) |
---|
196 | { |
---|
197 | register unsigned long reg; |
---|
198 | |
---|
199 | /* |
---|
200 | * Enable instruction cache |
---|
201 | */ |
---|
202 | GET_HID0(reg); |
---|
203 | reg |= HID0_ICE; |
---|
204 | SET_HID0(reg); |
---|
205 | |
---|
206 | /* |
---|
207 | * set up DBAT registers in MMU |
---|
208 | */ |
---|
209 | cpu_init_bsp(); |
---|
210 | |
---|
211 | #if defined(SHOW_MORE_INIT_SETTINGS) |
---|
212 | { extern void ShowBATS(void); |
---|
213 | ShowBATS(); |
---|
214 | } |
---|
215 | #endif |
---|
216 | |
---|
217 | /* |
---|
218 | * enable data MMU in MSR |
---|
219 | */ |
---|
220 | _write_MSR(_read_MSR() | MSR_DR); |
---|
221 | |
---|
222 | /* |
---|
223 | * enable data cache |
---|
224 | * |
---|
225 | * NOTE: TRACE32 now supports data cache for MGT5x00 |
---|
226 | */ |
---|
227 | GET_HID0(reg); |
---|
228 | reg |= HID0_DCE; |
---|
229 | SET_HID0(reg); |
---|
230 | } |
---|