1 | /*===============================================================*\ |
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2 | | Project: RTEMS generic MPC5200 BSP | |
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3 | +-----------------------------------------------------------------+ |
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4 | | Partially based on the code references which are named below. | |
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5 | | Adaptions, modifications, enhancements and any recent parts of | |
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6 | | the code are: | |
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7 | | Copyright (c) 2005 | |
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8 | | Embedded Brains GmbH | |
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9 | | Obere Lagerstr. 30 | |
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10 | | D-82178 Puchheim | |
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11 | | Germany | |
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12 | | rtems@embedded-brains.de | |
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13 | +-----------------------------------------------------------------+ |
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14 | | The license and distribution terms for this file may be | |
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15 | | found in the file LICENSE in this distribution or at | |
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16 | | | |
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17 | | http://www.rtems.com/license/LICENSE. | |
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18 | | | |
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19 | +-----------------------------------------------------------------+ |
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20 | | this file contains the code to initialize the cpu | |
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21 | \*===============================================================*/ |
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22 | /***********************************************************************/ |
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23 | /* */ |
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24 | /* Module: cpuinit.c */ |
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25 | /* Date: 07/17/2003 */ |
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26 | /* Purpose: RTEMS MPC5x00 C level startup code */ |
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27 | /* */ |
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28 | /*---------------------------------------------------------------------*/ |
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29 | /* */ |
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30 | /* Description: This file contains additional functions for */ |
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31 | /* initializing the MPC5x00 CPU */ |
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32 | /* */ |
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33 | /*---------------------------------------------------------------------*/ |
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34 | /* */ |
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35 | /* Code */ |
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36 | /* References: MPC8260ads additional CPU initialization */ |
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37 | /* Module: cpuinit.c */ |
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38 | /* Project: RTEMS 4.6.0pre1 / MCF8260ads BSP */ |
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39 | /* Version 1.1 */ |
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40 | /* Date: 10/22/2002 */ |
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41 | /* */ |
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42 | /* Author(s) / Copyright(s): */ |
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43 | /* */ |
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44 | /* Written by Jay Monkman (jmonkman@frasca.com) */ |
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45 | /* */ |
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46 | /*---------------------------------------------------------------------*/ |
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47 | /* */ |
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48 | /* Partially based on the code references which are named above. */ |
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49 | /* Adaptions, modifications, enhancements and any recent parts of */ |
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50 | /* the code are under the right of */ |
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51 | /* */ |
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52 | /* IPR Engineering, Dachauer StraÃe 38, D-80335 MÃŒnchen */ |
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53 | /* Copyright(C) 2003 */ |
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54 | /* */ |
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55 | /*---------------------------------------------------------------------*/ |
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56 | /* */ |
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57 | /* IPR Engineering makes no representation or warranties with */ |
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58 | /* respect to the performance of this computer program, and */ |
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59 | /* specifically disclaims any responsibility for any damages, */ |
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60 | /* special or consequential, connected with the use of this program. */ |
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61 | /* */ |
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62 | /*---------------------------------------------------------------------*/ |
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63 | /* */ |
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64 | /* Version history: 1.0 */ |
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65 | /* */ |
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66 | /***********************************************************************/ |
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67 | |
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68 | #include <stdbool.h> |
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69 | #include <string.h> |
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70 | |
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71 | #include <libcpu/powerpc-utility.h> |
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72 | #include <libcpu/mmu.h> |
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73 | |
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74 | #include <bsp.h> |
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75 | #include <bsp/mpc5200.h> |
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76 | |
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77 | #define SET_DBAT( n, uv, lv) \ |
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78 | do { \ |
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79 | PPC_SET_SPECIAL_PURPOSE_REGISTER( DBAT##n##L, lv); \ |
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80 | PPC_SET_SPECIAL_PURPOSE_REGISTER( DBAT##n##U, uv); \ |
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81 | } while (0) |
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82 | |
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83 | static void calc_dbat_regvals( |
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84 | BAT *bat_ptr, |
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85 | uint32_t base_addr, |
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86 | uint32_t size, |
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87 | bool flg_w, |
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88 | bool flg_i, |
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89 | bool flg_m, |
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90 | bool flg_g, |
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91 | uint32_t flg_bpp |
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92 | ) |
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93 | { |
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94 | uint32_t block_mask = 0xffffffff; |
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95 | uint32_t end_addr = base_addr + size - 1; |
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96 | |
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97 | /* Determine block mask, that overlaps the whole block */ |
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98 | while ((end_addr & block_mask) != (base_addr & block_mask)) { |
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99 | block_mask <<= 1; |
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100 | } |
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101 | |
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102 | bat_ptr->batu.bepi = base_addr >> (32 - 15); |
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103 | bat_ptr->batu.bl = ~(block_mask >> (28 - 11)); |
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104 | bat_ptr->batu.vs = 1; |
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105 | bat_ptr->batu.vp = 1; |
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106 | |
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107 | bat_ptr->batl.brpn = base_addr >> (32 - 15); |
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108 | bat_ptr->batl.w = flg_w; |
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109 | bat_ptr->batl.i = flg_i; |
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110 | bat_ptr->batl.m = flg_m; |
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111 | bat_ptr->batl.g = flg_g; |
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112 | bat_ptr->batl.pp = flg_bpp; |
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113 | } |
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114 | |
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115 | static void cpu_init_bsp(void) |
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116 | { |
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117 | #if defined (MPC5200_BOARD_BRS5L) |
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118 | BAT dbat; |
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119 | |
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120 | calc_dbat_regvals( |
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121 | &dbat, |
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122 | (uint32_t) bsp_ram_start, |
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123 | (uint32_t) bsp_ram_size, |
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124 | false, |
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125 | false, |
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126 | false, |
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127 | false, |
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128 | BPP_RW |
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129 | ); |
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130 | SET_DBAT(0,dbat.batu,dbat.batl); |
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131 | |
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132 | calc_dbat_regvals( |
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133 | &dbat, |
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134 | (uint32_t) bsp_rom_start, |
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135 | (uint32_t) bsp_rom_size, |
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136 | false, |
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137 | false, |
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138 | false, |
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139 | false, |
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140 | BPP_RX |
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141 | ); |
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142 | SET_DBAT(1,dbat.batu,dbat.batl); |
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143 | |
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144 | calc_dbat_regvals( |
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145 | &dbat, |
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146 | (uint32_t) MBAR, |
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147 | 128 * 1024, |
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148 | false, |
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149 | true, |
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150 | false, |
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151 | true, |
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152 | BPP_RW |
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153 | ); |
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154 | SET_DBAT(2,dbat.batu,dbat.batl); |
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155 | |
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156 | calc_dbat_regvals( |
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157 | &dbat, |
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158 | (uint32_t) bsp_dpram_start, |
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159 | 128 * 1024, |
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160 | false, |
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161 | true, |
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162 | false, |
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163 | true, |
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164 | BPP_RW |
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165 | ); |
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166 | SET_DBAT(3,dbat.batu,dbat.batl); |
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167 | #elif defined (HAS_UBOOT) |
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168 | BAT dbat; |
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169 | uint32_t start = 0; |
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170 | |
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171 | /* |
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172 | * Accesses (also speculative accesses) outside of the RAM area are a |
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173 | * disaster especially in combination with the BestComm. For safety reasons |
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174 | * we make the available RAM a little bit smaller to have an unused area at |
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175 | * the end. |
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176 | */ |
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177 | bsp_uboot_board_info.bi_memsize -= 4 * 1024; |
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178 | |
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179 | /* |
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180 | * Program BAT0 for RAM |
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181 | */ |
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182 | calc_dbat_regvals( |
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183 | &dbat, |
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184 | bsp_uboot_board_info.bi_memstart, |
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185 | bsp_uboot_board_info.bi_memsize, |
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186 | false, |
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187 | false, |
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188 | false, |
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189 | false, |
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190 | BPP_RW |
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191 | ); |
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192 | SET_DBAT(0,dbat.batu,dbat.batl); |
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193 | |
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194 | /* |
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195 | * Program BAT1 for Flash |
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196 | * |
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197 | * WARNING!! Some Freescale LITE5200B boards ship with a version of |
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198 | * U-Boot that lies about the starting address of Flash. This check |
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199 | * corrects that. |
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200 | */ |
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201 | if ((bsp_uboot_board_info.bi_flashstart + bsp_uboot_board_info.bi_flashsize) |
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202 | < bsp_uboot_board_info.bi_flashstart) { |
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203 | start = 0 - bsp_uboot_board_info.bi_flashsize; |
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204 | } else { |
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205 | start = bsp_uboot_board_info.bi_flashstart; |
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206 | } |
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207 | calc_dbat_regvals( |
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208 | &dbat, |
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209 | start, |
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210 | bsp_uboot_board_info.bi_flashsize, |
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211 | false, |
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212 | false, |
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213 | false, |
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214 | false, |
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215 | BPP_RX |
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216 | ); |
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217 | SET_DBAT(1,dbat.batu,dbat.batl); |
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218 | |
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219 | /* |
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220 | * Program BAT2 for the MBAR |
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221 | */ |
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222 | calc_dbat_regvals( |
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223 | &dbat, |
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224 | (uint32_t) MBAR, |
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225 | 128 * 1024, |
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226 | false, |
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227 | true, |
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228 | false, |
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229 | true, |
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230 | BPP_RW |
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231 | ); |
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232 | SET_DBAT(2,dbat.batu,dbat.batl); |
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233 | |
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234 | /* |
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235 | * If there is SRAM, program BAT3 for that memory |
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236 | */ |
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237 | if (bsp_uboot_board_info.bi_sramsize != 0) { |
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238 | calc_dbat_regvals( |
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239 | &dbat, |
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240 | bsp_uboot_board_info.bi_sramstart, |
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241 | bsp_uboot_board_info.bi_sramsize, |
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242 | false, |
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243 | true, |
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244 | true, |
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245 | true, |
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246 | BPP_RW |
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247 | ); |
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248 | SET_DBAT(3,dbat.batu,dbat.batl); |
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249 | } |
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250 | #else |
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251 | #warning "Using BAT register values set by environment" |
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252 | #endif |
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253 | |
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254 | #if defined(MPC5200_BOARD_DP2) |
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255 | /* Enable BAT4-7 */ |
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256 | PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS(HID2, BSP_BBIT32(13)); |
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257 | |
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258 | /* FPGA */ |
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259 | calc_dbat_regvals( |
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260 | &dbat, |
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261 | 0xf0020000, |
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262 | 128 * 1024, |
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263 | false, |
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264 | true, |
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265 | false, |
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266 | true, |
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267 | BPP_RW |
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268 | ); |
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269 | SET_DBAT(4, dbat.batu, dbat.batl); |
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270 | #elif defined(MPC5200_BOARD_PM520_ZE30) |
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271 | /* Enable BAT4-7 */ |
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272 | PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS(HID2, BSP_BBIT32(13)); |
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273 | |
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274 | /* External CC770 CAN controller available in version 2 */ |
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275 | calc_dbat_regvals( |
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276 | &dbat, |
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277 | 0xf2000000, |
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278 | 128 * 1024, |
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279 | false, |
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280 | true, |
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281 | false, |
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282 | true, |
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283 | BPP_RW |
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284 | ); |
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285 | SET_DBAT(4, dbat.batu, dbat.batl); |
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286 | #endif |
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287 | } |
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288 | |
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289 | void cpu_init(void) |
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290 | { |
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291 | uint32_t msr; |
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292 | |
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293 | /* Enable instruction cache */ |
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294 | PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS( HID0, HID0_ICE); |
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295 | |
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296 | /* Set up DBAT registers in MMU */ |
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297 | cpu_init_bsp(); |
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298 | |
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299 | #if defined(SHOW_MORE_INIT_SETTINGS) |
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300 | { extern void ShowBATS(void); |
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301 | ShowBATS(); |
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302 | } |
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303 | #endif |
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304 | |
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305 | /* Read MSR */ |
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306 | msr = ppc_machine_state_register(); |
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307 | |
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308 | /* Enable data MMU in MSR */ |
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309 | msr |= MSR_DR; |
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310 | |
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311 | /* Update MSR */ |
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312 | ppc_set_machine_state_register( msr); |
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313 | |
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314 | /* |
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315 | * Enable data cache. |
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316 | * |
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317 | * NOTE: TRACE32 now supports data cache for MGT5x00. |
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318 | */ |
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319 | PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS( HID0, HID0_DCE); |
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320 | } |
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