1 | /*===============================================================*\ |
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2 | | Project: RTEMS generic MPC5200 BSP | |
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3 | +-----------------------------------------------------------------+ |
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4 | | File: $File$ |
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5 | +-----------------------------------------------------------------+ |
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6 | | Partially based on the code references which are named below. | |
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7 | | Adaptions, modifications, enhancements and any recent parts of | |
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8 | | the code are: | |
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9 | | Copyright (c) 2005 | |
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10 | | Embedded Brains GmbH | |
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11 | | Obere Lagerstr. 30 | |
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12 | | D-82178 Puchheim | |
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13 | | Germany | |
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14 | | rtems@embedded-brains.de | |
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15 | +-----------------------------------------------------------------+ |
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16 | | The license and distribution terms for this file may be | |
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17 | | found in the file LICENSE in this distribution or at | |
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18 | | | |
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19 | | http://www.rtems.com/license/LICENSE. | |
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20 | | | |
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21 | +-----------------------------------------------------------------+ |
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22 | | this file contains the BSP initialization code | |
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23 | +-----------------------------------------------------------------+ |
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24 | | date history ID | |
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25 | | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
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26 | | 01.12.05 creation doe | |
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27 | |*****************************************************************| |
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28 | |*CVS information: | |
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29 | |*(the following information is created automatically, | |
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30 | |*do not edit here) | |
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31 | |*****************************************************************| |
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32 | |* $Log$ |
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33 | |* Revision 1.8 2005/12/09 08:57:03 thomas |
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34 | |* added/modifed file headers |
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35 | |* |
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36 | |* Revision 1.7 2005/12/06 14:11:12 thomas |
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37 | |* added EB file headers |
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38 | |* |
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39 | * |
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40 | |*****************************************************************| |
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41 | \*===============================================================*/ |
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42 | /***********************************************************************/ |
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43 | /* */ |
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44 | /* Module: bspstart.c */ |
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45 | /* Date: 07/17/2003 */ |
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46 | /* Purpose: RTEMS MPC5x00 C level startup code */ |
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47 | /* */ |
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48 | /*---------------------------------------------------------------------*/ |
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49 | /* */ |
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50 | /* Description: This routine starts the application. It includes */ |
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51 | /* application, board, and monitor specific */ |
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52 | /* initialization and configuration. The generic CPU */ |
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53 | /* dependent initialization has been performed before */ |
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54 | /* this routine is invoked. */ |
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55 | /* */ |
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56 | /*---------------------------------------------------------------------*/ |
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57 | /* */ |
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58 | /* Code */ |
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59 | /* References: MPC8260ads C level startup code */ |
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60 | /* Module: bspstart.c */ |
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61 | /* Project: RTEMS 4.6.0pre1 / MCF8260ads BSP */ |
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62 | /* Version 1.2 */ |
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63 | /* Date: 04/17/2002 */ |
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64 | /* */ |
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65 | /* Author(s) / Copyright(s): */ |
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66 | /* */ |
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67 | /* The MPC860 specific stuff was written by Jay Monkman */ |
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68 | /* (jmonkman@frasca.com) */ |
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69 | /* */ |
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70 | /* Modified for the MPC8260ADS board by Andy Dachs */ |
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71 | /* <a.dachs@sstl.co.uk> */ |
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72 | /* Surrey Satellite Technology Limited, 2001 */ |
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73 | /* A 40MHz system clock is assumed. */ |
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74 | /* The PON. RST.CONF. Dip switches (DS1) are */ |
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75 | /* 1 - Off */ |
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76 | /* 2 - On */ |
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77 | /* 3 - Off */ |
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78 | /* 4 - On */ |
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79 | /* 5 - Off */ |
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80 | /* 6 - Off */ |
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81 | /* 7 - Off */ |
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82 | /* 8 - Off */ |
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83 | /* Dip switches on DS2 and DS3 are all set to ON */ |
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84 | /* The LEDs on the board are used to signal panic and fatal_error */ |
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85 | /* conditions. */ |
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86 | /* The mmu is unused at this time. */ |
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87 | /* */ |
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88 | /* COPYRIGHT (c) 1989-1999. */ |
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89 | /* On-Line Applications Research Corporation (OAR). */ |
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90 | /* */ |
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91 | /* The license and distribution terms for this file may be */ |
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92 | /* found in found in the file LICENSE in this distribution or at */ |
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93 | /* http://www.OARcorp.com/rtems/license.html. */ |
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94 | /* */ |
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95 | /*---------------------------------------------------------------------*/ |
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96 | /* */ |
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97 | /* Partially based on the code references which are named above. */ |
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98 | /* Adaptions, modifications, enhancements and any recent parts of */ |
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99 | /* the code are under the right of */ |
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100 | /* */ |
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101 | /* IPR Engineering, Dachauer Straße 38, D-80335 München */ |
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102 | /* Copyright(C) 2003 */ |
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103 | /* */ |
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104 | /*---------------------------------------------------------------------*/ |
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105 | /* */ |
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106 | /* IPR Engineering makes no representation or warranties with */ |
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107 | /* respect to the performance of this computer program, and */ |
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108 | /* specifically disclaims any responsibility for any damages, */ |
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109 | /* special or consequential, connected with the use of this program. */ |
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110 | /* */ |
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111 | /*---------------------------------------------------------------------*/ |
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112 | /* */ |
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113 | /* Version history: 1.0 */ |
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114 | /* */ |
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115 | /***********************************************************************/ |
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116 | |
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117 | /*#include "../include/bsp.h"*/ |
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118 | #include "../include/bsp.h" |
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119 | |
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120 | #include <rtems/libio.h> |
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121 | #include <rtems/libcsupport.h> |
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122 | #include <rtems/powerpc/powerpc.h> |
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123 | #include <rtems/score/thread.h> |
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124 | |
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125 | #include <rtems/bspIo.h> |
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126 | #include <libcpu/cpuIdent.h> |
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127 | #include <libcpu/spr.h> |
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128 | #include "../irq/irq.h" |
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129 | |
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130 | #include <string.h> |
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131 | |
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132 | #ifdef STACK_CHECKER_ON |
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133 | #include <stackchk.h> |
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134 | #endif |
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135 | |
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136 | #if defined(HAS_UBOOT) |
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137 | bd_t *uboot_bdinfo_ptr = (bd_t *)1; /* will be overwritten from startup code */ |
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138 | bd_t uboot_bdinfo_copy; /* will be overwritten with copy of bdinfo */ |
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139 | #endif |
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140 | |
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141 | SPR_RW(SPRG0) |
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142 | SPR_RW(SPRG1) |
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143 | |
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144 | /* |
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145 | * The original table from the application (in ROM) and our copy of it with |
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146 | * some changes. Configuration is defined in <confdefs.h>. Make sure that |
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147 | * our configuration tables are uninitialized so that they get allocated in |
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148 | * the .bss section (RAM). |
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149 | */ |
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150 | extern rtems_configuration_table Configuration; |
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151 | extern unsigned long intrStackPtr; |
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152 | rtems_configuration_table BSP_Configuration; |
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153 | rtems_cpu_table Cpu_table; |
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154 | char *rtems_progname; |
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155 | |
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156 | |
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157 | /* |
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158 | * Use the shared implementations of the following routines. |
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159 | * Look in rtems/c/src/lib/libbsp/shared/bsppost.c and |
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160 | * rtems/c/src/lib/libbsp/shared/bsplibc.c. |
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161 | */ |
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162 | void bsp_postdriver_hook(void); |
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163 | void bsp_libc_init( void *, uint32_t, int ); |
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164 | extern void initialize_exceptions(void); |
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165 | extern void cpu_init(void); |
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166 | |
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167 | void BSP_panic(char *s) |
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168 | { |
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169 | printk("%s PANIC %s\n",_RTEMS_version, s); |
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170 | __asm__ __volatile ("sc"); |
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171 | } |
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172 | |
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173 | void _BSP_Fatal_error(unsigned int v) |
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174 | { |
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175 | printk("%s PANIC ERROR %x\n",_RTEMS_version, v); |
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176 | __asm__ __volatile ("sc"); |
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177 | } |
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178 | |
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179 | /* |
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180 | * Function: bsp_pretasking_hook |
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181 | * Created: 95/03/10 |
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182 | * |
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183 | * Description: |
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184 | * BSP pretasking hook. Called just before drivers are initialized. |
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185 | * Used to setup libc and install any BSP extensions. |
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186 | * |
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187 | * NOTES: |
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188 | * Must not use libc (to do io) from here, since drivers are |
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189 | * not yet initialized. |
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190 | * |
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191 | */ |
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192 | |
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193 | void |
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194 | bsp_pretasking_hook(void) |
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195 | { |
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196 | /* |
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197 | * These are assigned addresses in the linkcmds file for the BSP. This |
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198 | * approach is better than having these defined as manifest constants and |
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199 | * compiled into the kernel, but it is still not ideal when dealing with |
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200 | * multiprocessor configuration in which each board as a different memory |
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201 | * map. A better place for defining these symbols might be the makefiles. |
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202 | * Consideration should also be given to developing an approach in which |
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203 | * the kernel and the application can be linked and burned into ROM |
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204 | * independently of each other. |
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205 | */ |
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206 | |
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207 | #if defined(HAS_UBOOT) |
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208 | extern unsigned char _HeapStart; |
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209 | |
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210 | bsp_libc_init( &_HeapStart, |
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211 | uboot_bdinfo_ptr->bi_memstart |
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212 | + uboot_bdinfo_ptr->bi_memsize |
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213 | - (uint32_t)&_HeapStart |
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214 | , 0 ); |
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215 | #else |
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216 | extern unsigned char _HeapStart; |
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217 | extern unsigned char _HeapEnd; |
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218 | |
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219 | bsp_libc_init( &_HeapStart, &_HeapEnd - &_HeapStart, 0 ); |
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220 | #endif |
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221 | |
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222 | |
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223 | #ifdef STACK_CHECKER_ON |
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224 | /* |
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225 | * Initialize the stack bounds checker |
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226 | * We can either turn it on here or from the app. |
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227 | */ |
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228 | |
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229 | Stack_check_Initialize(); |
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230 | #endif |
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231 | |
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232 | #ifdef RTEMS_DEBUG |
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233 | rtems_debug_enable( RTEMS_DEBUG_ALL_MASK ); |
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234 | #endif |
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235 | } |
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236 | |
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237 | |
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238 | |
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239 | void bsp_predriver_hook(void) |
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240 | { |
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241 | #if 0 |
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242 | init_RTC(); |
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243 | |
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244 | init_PCI(); |
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245 | initialize_universe(); |
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246 | initialize_PCI_bridge (); |
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247 | |
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248 | #if (HAS_PMC_PSC8) |
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249 | initialize_PMC(); |
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250 | #endif |
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251 | |
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252 | /* |
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253 | * Initialize Bsp General purpose vector table. |
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254 | */ |
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255 | initialize_external_exception_vector(); |
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256 | |
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257 | #if (0) |
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258 | /* |
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259 | * XXX - Modify this to write a 48000000 (loop to self) command |
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260 | * to each interrupt location. This is better for debug. |
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261 | */ |
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262 | bsp_spurious_initialize(); |
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263 | #endif |
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264 | |
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265 | #endif |
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266 | } |
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267 | |
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268 | |
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269 | |
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270 | void bsp_start(void) |
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271 | { |
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272 | extern void *_WorkspaceBase; |
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273 | ppc_cpu_id_t myCpu; |
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274 | ppc_cpu_revision_t myCpuRevision; |
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275 | register unsigned char* intrStack; |
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276 | |
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277 | /* |
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278 | * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function |
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279 | * store the result in global variables so that it can be used latter... |
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280 | */ |
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281 | myCpu = get_ppc_cpu_type(); |
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282 | myCpuRevision = get_ppc_cpu_revision(); |
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283 | |
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284 | #if defined(HAS_UBOOT) |
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285 | uboot_bdinfo_copy = *uboot_bdinfo_ptr; |
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286 | uboot_bdinfo_ptr = &uboot_bdinfo_copy; |
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287 | #endif |
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288 | cpu_init(); |
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289 | |
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290 | /* |
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291 | * Initialize some SPRG registers related to irq handling |
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292 | */ |
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293 | |
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294 | intrStack = (((unsigned char*)&intrStackPtr) - PPC_MINIMUM_STACK_FRAME_SIZE); |
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295 | |
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296 | _write_SPRG1((unsigned int)intrStack); |
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297 | |
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298 | /* Signal them that this BSP has fixed PR288 - eventually, this should go away */ |
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299 | _write_SPRG0(PPC_BSP_HAS_FIXED_PR288); |
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300 | |
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301 | /* |
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302 | * initialize the CPU table for this BSP |
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303 | */ |
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304 | |
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305 | Cpu_table.pretasking_hook = bsp_pretasking_hook; /* init libc, etc. */ |
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306 | Cpu_table.predriver_hook = bsp_predriver_hook; /* init PCI / RTC ... */ |
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307 | Cpu_table.postdriver_hook = bsp_postdriver_hook; |
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308 | Cpu_table.clicks_per_usec = (IPB_CLOCK/1000000); |
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309 | Cpu_table.do_zero_of_workspace = TRUE; |
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310 | Cpu_table.exceptions_in_RAM = TRUE; |
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311 | |
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312 | if( Cpu_table.interrupt_stack_size < 4*1024 ) |
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313 | Cpu_table.interrupt_stack_size = 4 * 1024; |
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314 | |
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315 | /* |
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316 | * Install our own set of exception vectors |
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317 | */ |
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318 | |
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319 | initialize_exceptions(); |
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320 | |
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321 | /* |
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322 | * Enable instruction and data caches. Do not force writethrough mode. |
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323 | */ |
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324 | #if INSTRUCTION_CACHE_ENABLE |
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325 | rtems_cache_enable_instruction(); |
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326 | #endif |
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327 | #if DATA_CACHE_ENABLE |
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328 | rtems_cache_enable_data(); |
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329 | #endif |
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330 | |
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331 | /* |
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332 | * Allocate the memory for the RTEMS Work Space. This can come from |
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333 | * a variety of places: hard coded address, malloc'ed from outside |
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334 | * RTEMS world (e.g. simulator or primitive memory manager), or (as |
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335 | * typically done by stock BSPs) by subtracting the required amount |
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336 | * of work space from the last physical address on the CPU board. |
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337 | */ |
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338 | |
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339 | /* |
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340 | * Need to "allocate" the memory for the RTEMS Workspace and |
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341 | * tell the RTEMS configuration where it is. This memory is |
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342 | * not malloc'ed. It is just "pulled from the air". |
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343 | */ |
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344 | BSP_Configuration.work_space_start = (void *)&_WorkspaceBase; |
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345 | |
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346 | |
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347 | /* |
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348 | BSP_Configuration.microseconds_per_tick = 1000; |
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349 | */ |
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350 | |
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351 | /* |
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352 | * Initalize RTEMS IRQ system |
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353 | */ |
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354 | BSP_rtems_irq_mng_init(0); |
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355 | |
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356 | #ifdef SHOW_MORE_INIT_SETTINGS |
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357 | printk("Exit from bspstart\n"); |
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358 | #endif |
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359 | |
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360 | } |
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361 | |
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362 | /* |
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363 | * |
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364 | * _Thread_Idle_body |
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365 | * |
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366 | * Replaces the one in c/src/exec/score/src/threadidlebody.c |
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367 | * The MSR[POW] bit is set to put the CPU into the low power mode |
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368 | * defined in HID0. HID0 is set during starup in start.S. |
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369 | * |
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370 | */ |
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371 | Thread _Thread_Idle_body(uint32_t ignored ) |
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372 | { |
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373 | |
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374 | for(;;) |
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375 | { |
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376 | |
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377 | asm volatile("mfmsr 3; oris 3,3,4; sync; mtmsr 3; isync; ori 3,3,0; ori 3,3,0"); |
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378 | |
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379 | } |
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380 | |
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381 | return 0; |
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382 | |
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383 | } |
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384 | |
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