source: rtems/c/src/lib/libbsp/powerpc/gen5200/startup/bspstart.c @ a86f3aac

4.104.114.9
Last change on this file since a86f3aac was a86f3aac, checked in by Thomas Doerfler <Thomas.Doerfler@…>, on Jul 11, 2008 at 10:01:37 AM

adapted powerpc BSPs to new exception code

  • Property mode set to 100644
File size: 12.0 KB
Line 
1/*===============================================================*\
2| Project: RTEMS generic MPC5200 BSP                              |
3+-----------------------------------------------------------------+
4| Partially based on the code references which are named below.   |
5| Adaptions, modifications, enhancements and any recent parts of  |
6| the code are:                                                   |
7|                    Copyright (c) 2005                           |
8|                    Embedded Brains GmbH                         |
9|                    Obere Lagerstr. 30                           |
10|                    D-82178 Puchheim                             |
11|                    Germany                                      |
12|                    rtems@embedded-brains.de                     |
13+-----------------------------------------------------------------+
14| The license and distribution terms for this file may be         |
15| found in the file LICENSE in this distribution or at            |
16|                                                                 |
17| http://www.rtems.com/license/LICENSE.                           |
18|                                                                 |
19+-----------------------------------------------------------------+
20| this file contains the BSP initialization code                  |
21\*===============================================================*/
22/***********************************************************************/
23/*                                                                     */
24/*   Module:       bspstart.c                                          */
25/*   Date:         07/17/2003                                          */
26/*   Purpose:      RTEMS MPC5x00 C level startup code                  */
27/*                                                                     */
28/*---------------------------------------------------------------------*/
29/*                                                                     */
30/*   Description:  This routine starts the application. It includes    */
31/*                 application, board, and monitor specific            */
32/*                 initialization and configuration. The generic CPU   */
33/*                 dependent initialization has been performed before  */
34/*                 this routine is invoked.                            */
35/*                                                                     */
36/*---------------------------------------------------------------------*/
37/*                                                                     */
38/*   Code                                                              */
39/*   References:   MPC8260ads C level startup code                     */
40/*   Module:       bspstart.c                                          */
41/*   Project:      RTEMS 4.6.0pre1 / MCF8260ads BSP                    */
42/*   Version       1.2                                                 */
43/*   Date:         04/17/2002                                          */
44/*                                                                     */
45/*   Author(s) / Copyright(s):                                         */
46/*                                                                     */
47/*   The MPC860 specific stuff was written by Jay Monkman              */
48/*   (jmonkman@frasca.com)                                             */
49/*                                                                     */
50/*   Modified for the MPC8260ADS board by Andy Dachs                   */
51/*   <a.dachs@sstl.co.uk>                                              */
52/*   Surrey Satellite Technology Limited, 2001                         */
53/*   A 40MHz system clock is assumed.                                  */
54/*   The PON. RST.CONF. Dip switches (DS1) are                         */
55/*   1 - Off                                                           */
56/*   2 - On                                                            */
57/*   3 - Off                                                           */
58/*   4 - On                                                            */
59/*   5 - Off                                                           */
60/*   6 - Off                                                           */
61/*   7 - Off                                                           */
62/*   8 - Off                                                           */
63/*   Dip switches on DS2 and DS3 are all set to ON                     */
64/*   The LEDs on the board are used to signal panic and fatal_error    */
65/*   conditions.                                                       */
66/*   The mmu is unused at this time.                                   */
67/*                                                                     */
68/*   COPYRIGHT (c) 1989-2007.                                          */
69/*   On-Line Applications Research Corporation (OAR).                  */
70/*                                                                     */
71/*   The license and distribution terms for this file may be           */
72/*   found in found in the file LICENSE in this distribution or at     */
73/*   http://www.rtems.com/license/LICENSE.                             */
74/*                                                                     */
75/*---------------------------------------------------------------------*/
76/*                                                                     */
77/*   Partially based on the code references which are named above.     */
78/*   Adaptions, modifications, enhancements and any recent parts of    */
79/*   the code are under the right of                                   */
80/*                                                                     */
81/*         IPR Engineering, Dachauer Straße 38, D-80335 MÃŒnchen        */
82/*                        Copyright(C) 2003                            */
83/*                                                                     */
84/*---------------------------------------------------------------------*/
85/*                                                                     */
86/*   IPR Engineering makes no representation or warranties with        */
87/*   respect to the performance of this computer program, and          */
88/*   specifically disclaims any responsibility for any damages,        */
89/*   special or consequential, connected with the use of this program. */
90/*                                                                     */
91/*---------------------------------------------------------------------*/
92/*                                                                     */
93/*   Version history:  1.0                                             */
94/*                                                                     */
95/***********************************************************************/
96
97#warning The interrupt disable mask is now stored in SPRG0, please verify that this is compatible to this BSP (see also bootcard.c).
98
99#include <bsp.h>
100
101#include <rtems/libio.h>
102#include <rtems/libcsupport.h>
103#include <rtems/powerpc/powerpc.h>
104#include <rtems/score/thread.h>
105
106#include <rtems/bspIo.h>
107#include <libcpu/cpuIdent.h>
108#include <libcpu/spr.h>
109#include "../irq/irq.h"
110
111#include <string.h>
112
113#if defined(HAS_UBOOT)
114bd_t *uboot_bdinfo_ptr = (bd_t *)1; /* will be overwritten from startup code */
115bd_t uboot_bdinfo_copy;             /* will be overwritten with copy of bdinfo */
116#endif
117
118SPR_RW(SPRG1)
119
120extern unsigned long intrStackPtr;
121
122/*
123 *  Driver configuration parameters
124 */
125uint32_t   bsp_clicks_per_usec;
126
127/*
128 *  Use the shared implementations of the following routines.
129 *  Look in rtems/c/src/lib/libbsp/shared/bsplibc.c.
130 */
131void bsp_libc_init( void *, uint32_t, int );
132extern void initialize_exceptions(void);
133extern void cpu_init(void);
134
135void BSP_panic(char *s)
136  {
137  printk("%s PANIC %s\n",_RTEMS_version, s);
138  __asm__ __volatile ("sc");
139  }
140
141void _BSP_Fatal_error(unsigned int v)
142  {
143  printk("%s PANIC ERROR %x\n",_RTEMS_version, v);
144  __asm__ __volatile ("sc");
145  }
146
147/*
148 *  Function:   bsp_pretasking_hook
149 *  Created:    95/03/10
150 *
151 *  Description:
152 *      BSP pretasking hook.  Called just before drivers are initialized.
153 *      Used to setup libc and install any BSP extensions.
154 *
155 *  NOTES:
156 *      Must not use libc (to do io) from here, since drivers are
157 *      not yet initialized.
158 *
159 */
160
161void
162bsp_pretasking_hook(void)
163{
164  /*
165   *  These are assigned addresses in the linkcmds file for the BSP. This
166   *  approach is better than having these defined as manifest constants and
167   *  compiled into the kernel, but it is still not ideal when dealing with
168   *  multiprocessor configuration in which each board as a different memory
169   *  map. A better place for defining these symbols might be the makefiles.
170   *  Consideration should also be given to developing an approach in which
171   *  the kernel and the application can be linked and burned into ROM
172   *  independently of each other.
173   */
174
175#if defined(HAS_UBOOT)
176    extern unsigned char _HeapStart;
177
178    bsp_libc_init( &_HeapStart, 
179                   uboot_bdinfo_ptr->bi_memstart
180                   + uboot_bdinfo_ptr->bi_memsize
181                   - (uint32_t)&_HeapStart
182                   , 0 );
183#else
184    extern unsigned char _HeapStart;
185    extern unsigned char _HeapEnd;
186
187    bsp_libc_init( &_HeapStart, &_HeapEnd - &_HeapStart, 0 );
188#endif
189}
190
191void bsp_predriver_hook(void)
192  {
193#if 0
194  init_RTC();
195
196  init_PCI();
197  initialize_universe();
198  initialize_PCI_bridge ();
199
200#if (HAS_PMC_PSC8)
201  initialize_PMC();
202#endif
203
204 /*
205  * Initialize Bsp General purpose vector table.
206  */
207 initialize_external_exception_vector();
208
209#if (0)
210  /*
211   * XXX - Modify this to write a 48000000 (loop to self) command
212   *       to each interrupt location.  This is better for debug.
213   */
214 bsp_spurious_initialize();
215#endif
216
217#endif
218}
219
220void bsp_start(void)
221{
222  extern void *_WorkspaceBase;
223  ppc_cpu_id_t myCpu;
224  ppc_cpu_revision_t myCpuRevision;
225  register unsigned char* intrStack;
226
227  /*
228   * Get CPU identification dynamically. Note that the get_ppc_cpu_type()
229   * function store the result in global variables so that it can be used
230   * later...
231   */
232  myCpu         = get_ppc_cpu_type();
233  myCpuRevision = get_ppc_cpu_revision();
234
235  #if defined(HAS_UBOOT)
236    uboot_bdinfo_copy = *uboot_bdinfo_ptr;
237    uboot_bdinfo_ptr = &uboot_bdinfo_copy;
238  #endif 
239
240  #if defined(HAS_UBOOT) && defined(SHOW_MORE_INIT_SETTINGS)
241    {
242      void dumpUBootBDInfo( bd_t * );
243      dumpUBootBDInfo( uboot_bdinfo_ptr );
244    }
245  #endif
246
247  cpu_init();
248
249  /*
250   * Initialize some SPRG registers related to irq handling
251   */
252
253  intrStack = (((unsigned char*)&intrStackPtr) - PPC_MINIMUM_STACK_FRAME_SIZE);
254
255  _write_SPRG1((unsigned int)intrStack);
256
257 bsp_clicks_per_usec    = (IPB_CLOCK/1000000);
258
259 /*
260  * Install our own set of exception vectors
261  */
262
263  initialize_exceptions();
264
265  /*
266   * Enable instruction and data caches. Do not force writethrough mode.
267   */
268  #if INSTRUCTION_CACHE_ENABLE
269    rtems_cache_enable_instruction();
270  #endif
271  #if DATA_CACHE_ENABLE
272    rtems_cache_enable_data();
273  #endif
274
275  /*
276   *  Need to "allocate" the memory for the RTEMS Workspace and
277   *  tell the RTEMS configuration where it is.  This memory is
278   *  not malloc'ed.  It is just "pulled from the air".
279   */
280  Configuration.work_space_start = (void *)&_WorkspaceBase;
281  #ifdef SHOW_MORE_INIT_SETTINGS
282    printk( "workspace=%p\n", Configuration.work_space_start );
283    printk( "workspace size=%d\n", Configuration.work_space_size );
284  #endif
285
286  /*
287   * Initalize RTEMS IRQ system
288   */
289  BSP_rtems_irq_mng_init(0);
290
291  /*
292   *  If the BSP was built with IRQ benchmarking enabled,
293   *  then intialize it.
294   */
295  #if (BENCHMARK_IRQ_PROCESSING == 1)
296    BSP_IRQ_Benchmarking_Reset();
297  #endif
298
299  #ifdef SHOW_MORE_INIT_SETTINGS
300    printk("Exit from bspstart\n");
301  #endif
302
303}
304
305/*
306 *
307 *  _Thread_Idle_body
308 *
309 *  Replaces the one in c/src/exec/score/src/threadidlebody.c
310 *  The MSR[POW] bit is set to put the CPU into the low power mode
311 *  defined in HID0.  HID0 is set during starup in start.S.
312 *
313 */
314Thread _Thread_Idle_body(uint32_t ignored)
315{
316  for(;;) {
317    asm volatile(
318      "mfmsr 3; oris 3,3,4; sync; mtmsr 3; isync; ori 3,3,0; ori 3,3,0"
319     );
320  }
321  return 0;
322}
323
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