1 | /*===============================================================*\ |
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2 | | Project: RTEMS generic MPC5200 BSP | |
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3 | +-----------------------------------------------------------------+ |
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4 | | Partially based on the code references which are named below. | |
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5 | | Adaptions, modifications, enhancements and any recent parts of | |
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6 | | the code are: | |
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7 | | Copyright (c) 2005 | |
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8 | | Embedded Brains GmbH | |
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9 | | Obere Lagerstr. 30 | |
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10 | | D-82178 Puchheim | |
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11 | | Germany | |
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12 | | rtems@embedded-brains.de | |
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13 | +-----------------------------------------------------------------+ |
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14 | | The license and distribution terms for this file may be | |
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15 | | found in the file LICENSE in this distribution or at | |
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16 | | | |
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17 | | http://www.rtems.com/license/LICENSE. | |
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18 | | | |
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19 | +-----------------------------------------------------------------+ |
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20 | | this file contains the BSP initialization code | |
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21 | \*===============================================================*/ |
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22 | /***********************************************************************/ |
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23 | /* */ |
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24 | /* Module: bspstart.c */ |
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25 | /* Date: 07/17/2003 */ |
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26 | /* Purpose: RTEMS MPC5x00 C level startup code */ |
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27 | /* */ |
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28 | /*---------------------------------------------------------------------*/ |
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29 | /* */ |
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30 | /* Description: This routine starts the application. It includes */ |
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31 | /* application, board, and monitor specific */ |
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32 | /* initialization and configuration. The generic CPU */ |
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33 | /* dependent initialization has been performed before */ |
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34 | /* this routine is invoked. */ |
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35 | /* */ |
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36 | /*---------------------------------------------------------------------*/ |
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37 | /* */ |
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38 | /* Code */ |
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39 | /* References: MPC8260ads C level startup code */ |
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40 | /* Module: bspstart.c */ |
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41 | /* Project: RTEMS 4.6.0pre1 / MCF8260ads BSP */ |
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42 | /* Version 1.2 */ |
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43 | /* Date: 04/17/2002 */ |
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44 | /* */ |
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45 | /* Author(s) / Copyright(s): */ |
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46 | /* */ |
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47 | /* The MPC860 specific stuff was written by Jay Monkman */ |
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48 | /* (jmonkman@frasca.com) */ |
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49 | /* */ |
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50 | /* Modified for the MPC8260ADS board by Andy Dachs */ |
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51 | /* <a.dachs@sstl.co.uk> */ |
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52 | /* Surrey Satellite Technology Limited, 2001 */ |
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53 | /* A 40MHz system clock is assumed. */ |
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54 | /* The PON. RST.CONF. Dip switches (DS1) are */ |
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55 | /* 1 - Off */ |
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56 | /* 2 - On */ |
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57 | /* 3 - Off */ |
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58 | /* 4 - On */ |
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59 | /* 5 - Off */ |
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60 | /* 6 - Off */ |
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61 | /* 7 - Off */ |
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62 | /* 8 - Off */ |
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63 | /* Dip switches on DS2 and DS3 are all set to ON */ |
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64 | /* The LEDs on the board are used to signal panic and fatal_error */ |
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65 | /* conditions. */ |
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66 | /* The mmu is unused at this time. */ |
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67 | /* */ |
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68 | /* COPYRIGHT (c) 1989-2007. */ |
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69 | /* On-Line Applications Research Corporation (OAR). */ |
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70 | /* */ |
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71 | /* The license and distribution terms for this file may be */ |
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72 | /* found in the file LICENSE in this distribution or at */ |
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73 | /* http://www.rtems.com/license/LICENSE. */ |
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74 | /* */ |
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75 | /*---------------------------------------------------------------------*/ |
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76 | /* */ |
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77 | /* Partially based on the code references which are named above. */ |
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78 | /* Adaptions, modifications, enhancements and any recent parts of */ |
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79 | /* the code are under the right of */ |
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80 | /* */ |
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81 | /* IPR Engineering, Dachauer StraÃe 38, D-80335 MÃŒnchen */ |
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82 | /* Copyright(C) 2003 */ |
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83 | /* */ |
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84 | /*---------------------------------------------------------------------*/ |
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85 | /* */ |
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86 | /* IPR Engineering makes no representation or warranties with */ |
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87 | /* respect to the performance of this computer program, and */ |
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88 | /* specifically disclaims any responsibility for any damages, */ |
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89 | /* special or consequential, connected with the use of this program. */ |
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90 | /* */ |
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91 | /*---------------------------------------------------------------------*/ |
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92 | /* */ |
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93 | /* Version history: 1.0 */ |
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94 | /* */ |
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95 | /***********************************************************************/ |
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96 | |
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97 | #include <rtems.h> |
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98 | |
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99 | #include <libcpu/powerpc-utility.h> |
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100 | |
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101 | #include <bsp.h> |
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102 | #include <bsp/vectors.h> |
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103 | #include <bsp/bootcard.h> |
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104 | #include <bsp/irq.h> |
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105 | #include <bsp/irq-generic.h> |
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106 | |
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107 | /* |
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108 | * Driver configuration parameters |
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109 | */ |
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110 | uint32_t bsp_clicks_per_usec; |
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111 | |
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112 | void BSP_panic(char *s) |
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113 | { |
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114 | printk("%s PANIC %s\n",_RTEMS_version, s); |
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115 | __asm__ __volatile ("sc"); |
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116 | } |
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117 | |
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118 | void _BSP_Fatal_error(unsigned int v) |
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119 | { |
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120 | printk("%s PANIC ERROR %x\n",_RTEMS_version, v); |
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121 | __asm__ __volatile ("sc"); |
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122 | } |
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123 | |
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124 | void bsp_start(void) |
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125 | { |
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126 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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127 | ppc_cpu_id_t myCpu; |
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128 | ppc_cpu_revision_t myCpuRevision; |
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129 | |
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130 | /* |
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131 | * Get CPU identification dynamically. Note that the get_ppc_cpu_type() |
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132 | * function store the result in global variables so that it can be used |
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133 | * later... |
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134 | */ |
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135 | myCpu = get_ppc_cpu_type(); |
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136 | myCpuRevision = get_ppc_cpu_revision(); |
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137 | |
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138 | #if defined(HAS_UBOOT) && defined(SHOW_MORE_INIT_SETTINGS) |
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139 | { |
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140 | void dumpUBootBDInfo( bd_t * ); |
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141 | dumpUBootBDInfo( &bsp_uboot_board_info ); |
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142 | } |
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143 | #endif |
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144 | |
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145 | cpu_init(); |
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146 | |
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147 | bsp_clicks_per_usec = (XLB_CLOCK/4000000); |
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148 | |
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149 | /* |
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150 | * Enable instruction and data caches. Do not force writethrough mode. |
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151 | */ |
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152 | #if INSTRUCTION_CACHE_ENABLE |
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153 | rtems_cache_enable_instruction(); |
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154 | #endif |
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155 | #if DATA_CACHE_ENABLE |
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156 | rtems_cache_enable_data(); |
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157 | #endif |
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158 | |
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159 | /* Initialize exception handler */ |
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160 | ppc_exc_cache_wb_check = 0; |
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161 | sc = ppc_exc_initialize( |
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162 | PPC_INTERRUPT_DISABLE_MASK_DEFAULT, |
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163 | (uintptr_t) bsp_interrupt_stack_start, |
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164 | (uintptr_t) bsp_interrupt_stack_size |
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165 | ); |
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166 | if (sc != RTEMS_SUCCESSFUL) { |
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167 | BSP_panic("cannot initialize exceptions"); |
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168 | } |
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169 | |
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170 | /* Initalize interrupt support */ |
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171 | sc = bsp_interrupt_initialize(); |
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172 | if (sc != RTEMS_SUCCESSFUL) { |
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173 | BSP_panic("cannot intitialize interrupts"); |
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174 | } |
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175 | |
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176 | /* |
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177 | * If the BSP was built with IRQ benchmarking enabled, |
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178 | * then intialize it. |
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179 | */ |
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180 | #if (BENCHMARK_IRQ_PROCESSING == 1) |
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181 | BSP_IRQ_Benchmarking_Reset(); |
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182 | #endif |
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183 | |
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184 | #ifdef SHOW_MORE_INIT_SETTINGS |
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185 | printk("Exit from bspstart\n"); |
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186 | #endif |
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187 | } |
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