source: rtems/c/src/lib/libbsp/powerpc/gen5200/startup/bspstart.c @ 09038441

4.104.114.95
Last change on this file since 09038441 was 09038441, checked in by Joel Sherrill <joel.sherrill@…>, on 12/14/07 at 22:00:59

2007-12-14 Joel Sherrill <joel.sherrill@…>

  • irq/irq.c, startup/bspclean.c, startup/bspstart.c: I give. The code is now in conditionally so I can avoid putting it in accidently again.
  • Property mode set to 100644
File size: 12.1 KB
Line 
1/*===============================================================*\
2| Project: RTEMS generic MPC5200 BSP                              |
3+-----------------------------------------------------------------+
4| Partially based on the code references which are named below.   |
5| Adaptions, modifications, enhancements and any recent parts of  |
6| the code are:                                                   |
7|                    Copyright (c) 2005                           |
8|                    Embedded Brains GmbH                         |
9|                    Obere Lagerstr. 30                           |
10|                    D-82178 Puchheim                             |
11|                    Germany                                      |
12|                    rtems@embedded-brains.de                     |
13+-----------------------------------------------------------------+
14| The license and distribution terms for this file may be         |
15| found in the file LICENSE in this distribution or at            |
16|                                                                 |
17| http://www.rtems.com/license/LICENSE.                           |
18|                                                                 |
19+-----------------------------------------------------------------+
20| this file contains the BSP initialization code                  |
21\*===============================================================*/
22/***********************************************************************/
23/*                                                                     */
24/*   Module:       bspstart.c                                          */
25/*   Date:         07/17/2003                                          */
26/*   Purpose:      RTEMS MPC5x00 C level startup code                  */
27/*                                                                     */
28/*---------------------------------------------------------------------*/
29/*                                                                     */
30/*   Description:  This routine starts the application. It includes    */
31/*                 application, board, and monitor specific            */
32/*                 initialization and configuration. The generic CPU   */
33/*                 dependent initialization has been performed before  */
34/*                 this routine is invoked.                            */
35/*                                                                     */
36/*---------------------------------------------------------------------*/
37/*                                                                     */
38/*   Code                                                              */
39/*   References:   MPC8260ads C level startup code                     */
40/*   Module:       bspstart.c                                          */
41/*   Project:      RTEMS 4.6.0pre1 / MCF8260ads BSP                    */
42/*   Version       1.2                                                 */
43/*   Date:         04/17/2002                                          */
44/*                                                                     */
45/*   Author(s) / Copyright(s):                                         */
46/*                                                                     */
47/*   The MPC860 specific stuff was written by Jay Monkman              */
48/*   (jmonkman@frasca.com)                                             */
49/*                                                                     */
50/*   Modified for the MPC8260ADS board by Andy Dachs                   */
51/*   <a.dachs@sstl.co.uk>                                              */
52/*   Surrey Satellite Technology Limited, 2001                         */
53/*   A 40MHz system clock is assumed.                                  */
54/*   The PON. RST.CONF. Dip switches (DS1) are                         */
55/*   1 - Off                                                           */
56/*   2 - On                                                            */
57/*   3 - Off                                                           */
58/*   4 - On                                                            */
59/*   5 - Off                                                           */
60/*   6 - Off                                                           */
61/*   7 - Off                                                           */
62/*   8 - Off                                                           */
63/*   Dip switches on DS2 and DS3 are all set to ON                     */
64/*   The LEDs on the board are used to signal panic and fatal_error    */
65/*   conditions.                                                       */
66/*   The mmu is unused at this time.                                   */
67/*                                                                     */
68/*   COPYRIGHT (c) 1989-2007.
69/*   On-Line Applications Research Corporation (OAR).                  */
70/*                                                                     */
71/*   The license and distribution terms for this file may be           */
72/*   found in found in the file LICENSE in this distribution or at     */
73/*   http://www.rtems.com/license/LICENSE.                        */
74/*                                                                     */
75/*---------------------------------------------------------------------*/
76/*                                                                     */
77/*   Partially based on the code references which are named above.     */
78/*   Adaptions, modifications, enhancements and any recent parts of    */
79/*   the code are under the right of                                   */
80/*                                                                     */
81/*         IPR Engineering, Dachauer Straße 38, D-80335 MÃŒnchen        */
82/*                        Copyright(C) 2003                            */
83/*                                                                     */
84/*---------------------------------------------------------------------*/
85/*                                                                     */
86/*   IPR Engineering makes no representation or warranties with        */
87/*   respect to the performance of this computer program, and          */
88/*   specifically disclaims any responsibility for any damages,        */
89/*   special or consequential, connected with the use of this program. */
90/*                                                                     */
91/*---------------------------------------------------------------------*/
92/*                                                                     */
93/*   Version history:  1.0                                             */
94/*                                                                     */
95/***********************************************************************/
96
97#include <bsp.h>
98
99#include <rtems/libio.h>
100#include <rtems/libcsupport.h>
101#include <rtems/powerpc/powerpc.h>
102#include <rtems/score/thread.h>
103
104#include <rtems/bspIo.h>
105#include <libcpu/cpuIdent.h>
106#include <libcpu/spr.h>
107#include "../irq/irq.h"
108
109#include <string.h>
110
111#ifdef STACK_CHECKER_ON
112#include <stackchk.h>
113#endif
114
115#if defined(HAS_UBOOT)
116bd_t *uboot_bdinfo_ptr = (bd_t *)1; /* will be overwritten from startup code */
117bd_t uboot_bdinfo_copy;             /* will be overwritten with copy of bdinfo */
118#endif
119
120SPR_RW(SPRG0)
121SPR_RW(SPRG1)
122
123extern unsigned long intrStackPtr;
124
125/*
126 *  Driver configuration parameters
127 */
128uint32_t   bsp_clicks_per_usec;
129
130/*
131 *  Use the shared implementations of the following routines.
132 *  Look in rtems/c/src/lib/libbsp/shared/bsppost.c and
133 *  rtems/c/src/lib/libbsp/shared/bsplibc.c.
134 */
135void bsp_postdriver_hook(void);
136void bsp_libc_init( void *, uint32_t, int );
137extern void initialize_exceptions(void);
138extern void cpu_init(void);
139
140void BSP_panic(char *s)
141  {
142  printk("%s PANIC %s\n",_RTEMS_version, s);
143  __asm__ __volatile ("sc");
144  }
145
146void _BSP_Fatal_error(unsigned int v)
147  {
148  printk("%s PANIC ERROR %x\n",_RTEMS_version, v);
149  __asm__ __volatile ("sc");
150  }
151
152/*
153 *  Function:   bsp_pretasking_hook
154 *  Created:    95/03/10
155 *
156 *  Description:
157 *      BSP pretasking hook.  Called just before drivers are initialized.
158 *      Used to setup libc and install any BSP extensions.
159 *
160 *  NOTES:
161 *      Must not use libc (to do io) from here, since drivers are
162 *      not yet initialized.
163 *
164 */
165
166void
167bsp_pretasking_hook(void)
168{
169  /*
170   *  These are assigned addresses in the linkcmds file for the BSP. This
171   *  approach is better than having these defined as manifest constants and
172   *  compiled into the kernel, but it is still not ideal when dealing with
173   *  multiprocessor configuration in which each board as a different memory
174   *  map. A better place for defining these symbols might be the makefiles.
175   *  Consideration should also be given to developing an approach in which
176   *  the kernel and the application can be linked and burned into ROM
177   *  independently of each other.
178   */
179
180#if defined(HAS_UBOOT)
181    extern unsigned char _HeapStart;
182
183    bsp_libc_init( &_HeapStart,
184                   uboot_bdinfo_ptr->bi_memstart
185                   + uboot_bdinfo_ptr->bi_memsize
186                   - (uint32_t)&_HeapStart
187                   , 0 );
188#else
189    extern unsigned char _HeapStart;
190    extern unsigned char _HeapEnd;
191
192    bsp_libc_init( &_HeapStart, &_HeapEnd - &_HeapStart, 0 );
193#endif
194
195
196#ifdef STACK_CHECKER_ON
197  /*
198   *  Initialize the stack bounds checker
199   *  We can either turn it on here or from the app.
200   */
201
202  Stack_check_Initialize();
203#endif
204
205#ifdef RTEMS_DEBUG
206  rtems_debug_enable( RTEMS_DEBUG_ALL_MASK );
207#endif
208}
209
210
211
212void bsp_predriver_hook(void)
213  {
214#if 0
215  init_RTC();
216
217  init_PCI();
218  initialize_universe();
219  initialize_PCI_bridge ();
220
221#if (HAS_PMC_PSC8)
222  initialize_PMC();
223#endif
224
225 /*
226  * Initialize Bsp General purpose vector table.
227  */
228 initialize_external_exception_vector();
229
230#if (0)
231  /*
232   * XXX - Modify this to write a 48000000 (loop to self) command
233   *       to each interrupt location.  This is better for debug.
234   */
235 bsp_spurious_initialize();
236#endif
237
238#endif
239}
240
241void bsp_start(void)
242{
243  extern void *_WorkspaceBase;
244  ppc_cpu_id_t myCpu;
245  ppc_cpu_revision_t myCpuRevision;
246  register unsigned char* intrStack;
247
248  /*
249   * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function
250   * store the result in global variables so that it can be used latter...
251   */
252  myCpu         = get_ppc_cpu_type();
253  myCpuRevision = get_ppc_cpu_revision();
254
255#if defined(HAS_UBOOT)
256  uboot_bdinfo_copy = *uboot_bdinfo_ptr;
257  uboot_bdinfo_ptr = &uboot_bdinfo_copy;
258#endif 
259
260#if defined(HAS_UBOOT) && defined(SHOW_MORE_INIT_SETTINGS)
261  {
262    void dumpUBootBDInfo( bd_t * );
263    dumpUBootBDInfo( uboot_bdinfo_ptr );
264  }
265#endif
266
267  cpu_init();
268
269  /*
270   * Initialize some SPRG registers related to irq handling
271   */
272
273  intrStack = (((unsigned char*)&intrStackPtr) - PPC_MINIMUM_STACK_FRAME_SIZE);
274
275  _write_SPRG1((unsigned int)intrStack);
276
277  /* Signal them that this BSP has fixed PR288 - eventually, this should go away */
278  _write_SPRG0(PPC_BSP_HAS_FIXED_PR288);
279
280 bsp_clicks_per_usec    = (IPB_CLOCK/1000000);
281
282 /*
283  * Install our own set of exception vectors
284  */
285
286  initialize_exceptions();
287
288  /*
289   * Enable instruction and data caches. Do not force writethrough mode.
290   */
291#if INSTRUCTION_CACHE_ENABLE
292  rtems_cache_enable_instruction();
293#endif
294#if DATA_CACHE_ENABLE
295  rtems_cache_enable_data();
296#endif
297
298  /*
299   *  Need to "allocate" the memory for the RTEMS Workspace and
300   *  tell the RTEMS configuration where it is.  This memory is
301   *  not malloc'ed.  It is just "pulled from the air".
302   */
303  Configuration.work_space_start = (void *)&_WorkspaceBase;
304
305  /*
306   * Initalize RTEMS IRQ system
307   */
308  BSP_rtems_irq_mng_init(0);
309
310#if defined(TIME_IRQs)
311  {
312    void BSP_initialize_IRQ_Timing(void);
313    BSP_initialize_IRQ_Timing();
314  }
315#endif
316
317#ifdef SHOW_MORE_INIT_SETTINGS
318  printk("Exit from bspstart\n");
319#endif
320
321  }
322
323/*
324 *
325 *  _Thread_Idle_body
326 *
327 *  Replaces the one in c/src/exec/score/src/threadidlebody.c
328 *  The MSR[POW] bit is set to put the CPU into the low power mode
329 *  defined in HID0.  HID0 is set during starup in start.S.
330 *
331 */
332Thread _Thread_Idle_body(uint32_t ignored)
333{
334  for(;;) {
335    asm volatile(
336      "mfmsr 3; oris 3,3,4; sync; mtmsr 3; isync; ori 3,3,0; ori 3,3,0"
337     );
338  }
339  return 0;
340}
341
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