[ca680bc5] | 1 | /*===============================================================*\ |
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| 2 | | Project: RTEMS generic MPC5200 BSP | |
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| 3 | +-----------------------------------------------------------------+ |
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| 4 | | Partially based on the code references which are named below. | |
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| 5 | | Adaptions, modifications, enhancements and any recent parts of | |
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| 6 | | the code are: | |
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| 7 | | Copyright (c) 2005 | |
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| 8 | | Embedded Brains GmbH | |
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| 9 | | Obere Lagerstr. 30 | |
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| 10 | | D-82178 Puchheim | |
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| 11 | | Germany | |
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| 12 | | rtems@embedded-brains.de | |
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| 13 | +-----------------------------------------------------------------+ |
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| 14 | | The license and distribution terms for this file may be | |
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| 15 | | found in the file LICENSE in this distribution or at | |
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| 16 | | | |
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| 17 | | http://www.rtems.com/license/LICENSE. | |
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| 18 | | | |
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| 19 | +-----------------------------------------------------------------+ |
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| 20 | | this file contains the BSP initialization code | |
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| 21 | \*===============================================================*/ |
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| 22 | /***********************************************************************/ |
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| 23 | /* */ |
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| 24 | /* Module: bspstart.c */ |
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| 25 | /* Date: 07/17/2003 */ |
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| 26 | /* Purpose: RTEMS MPC5x00 C level startup code */ |
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| 27 | /* */ |
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| 28 | /*---------------------------------------------------------------------*/ |
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| 29 | /* */ |
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| 30 | /* Description: This routine starts the application. It includes */ |
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| 31 | /* application, board, and monitor specific */ |
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| 32 | /* initialization and configuration. The generic CPU */ |
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| 33 | /* dependent initialization has been performed before */ |
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| 34 | /* this routine is invoked. */ |
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| 35 | /* */ |
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| 36 | /*---------------------------------------------------------------------*/ |
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| 37 | /* */ |
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| 38 | /* Code */ |
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| 39 | /* References: MPC8260ads C level startup code */ |
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| 40 | /* Module: bspstart.c */ |
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| 41 | /* Project: RTEMS 4.6.0pre1 / MCF8260ads BSP */ |
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| 42 | /* Version 1.2 */ |
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| 43 | /* Date: 04/17/2002 */ |
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| 44 | /* */ |
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| 45 | /* Author(s) / Copyright(s): */ |
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| 46 | /* */ |
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| 47 | /* The MPC860 specific stuff was written by Jay Monkman */ |
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| 48 | /* (jmonkman@frasca.com) */ |
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| 49 | /* */ |
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| 50 | /* Modified for the MPC8260ADS board by Andy Dachs */ |
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| 51 | /* <a.dachs@sstl.co.uk> */ |
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| 52 | /* Surrey Satellite Technology Limited, 2001 */ |
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| 53 | /* A 40MHz system clock is assumed. */ |
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| 54 | /* The PON. RST.CONF. Dip switches (DS1) are */ |
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| 55 | /* 1 - Off */ |
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| 56 | /* 2 - On */ |
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| 57 | /* 3 - Off */ |
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| 58 | /* 4 - On */ |
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| 59 | /* 5 - Off */ |
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| 60 | /* 6 - Off */ |
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| 61 | /* 7 - Off */ |
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| 62 | /* 8 - Off */ |
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| 63 | /* Dip switches on DS2 and DS3 are all set to ON */ |
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| 64 | /* The LEDs on the board are used to signal panic and fatal_error */ |
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| 65 | /* conditions. */ |
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| 66 | /* The mmu is unused at this time. */ |
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| 67 | /* */ |
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[eabd9f0] | 68 | /* COPYRIGHT (c) 1989-2007. */ |
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[ca680bc5] | 69 | /* On-Line Applications Research Corporation (OAR). */ |
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| 70 | /* */ |
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| 71 | /* The license and distribution terms for this file may be */ |
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| 72 | /* found in found in the file LICENSE in this distribution or at */ |
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[eabd9f0] | 73 | /* http://www.rtems.com/license/LICENSE. */ |
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[ca680bc5] | 74 | /* */ |
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| 75 | /*---------------------------------------------------------------------*/ |
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| 76 | /* */ |
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| 77 | /* Partially based on the code references which are named above. */ |
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| 78 | /* Adaptions, modifications, enhancements and any recent parts of */ |
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| 79 | /* the code are under the right of */ |
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| 80 | /* */ |
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[1af911b8] | 81 | /* IPR Engineering, Dachauer StraÃe 38, D-80335 MÃŒnchen */ |
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[ca680bc5] | 82 | /* Copyright(C) 2003 */ |
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| 83 | /* */ |
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| 84 | /*---------------------------------------------------------------------*/ |
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| 85 | /* */ |
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| 86 | /* IPR Engineering makes no representation or warranties with */ |
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| 87 | /* respect to the performance of this computer program, and */ |
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| 88 | /* specifically disclaims any responsibility for any damages, */ |
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| 89 | /* special or consequential, connected with the use of this program. */ |
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| 90 | /* */ |
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| 91 | /*---------------------------------------------------------------------*/ |
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| 92 | /* */ |
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| 93 | /* Version history: 1.0 */ |
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| 94 | /* */ |
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| 95 | /***********************************************************************/ |
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| 96 | |
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[a86f3aac] | 97 | #warning The interrupt disable mask is now stored in SPRG0, please verify that this is compatible to this BSP (see also bootcard.c). |
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| 98 | |
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[da261595] | 99 | #include <bsp.h> |
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[ca680bc5] | 100 | |
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| 101 | #include <rtems/libio.h> |
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| 102 | #include <rtems/libcsupport.h> |
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| 103 | #include <rtems/powerpc/powerpc.h> |
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| 104 | #include <rtems/score/thread.h> |
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| 105 | |
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| 106 | #include <rtems/bspIo.h> |
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| 107 | #include <libcpu/cpuIdent.h> |
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| 108 | #include <libcpu/spr.h> |
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| 109 | #include "../irq/irq.h" |
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| 110 | |
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| 111 | #include <string.h> |
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| 112 | |
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| 113 | #if defined(HAS_UBOOT) |
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| 114 | bd_t *uboot_bdinfo_ptr = (bd_t *)1; /* will be overwritten from startup code */ |
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| 115 | bd_t uboot_bdinfo_copy; /* will be overwritten with copy of bdinfo */ |
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| 116 | #endif |
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| 117 | |
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| 118 | SPR_RW(SPRG1) |
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| 119 | |
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| 120 | extern unsigned long intrStackPtr; |
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| 121 | |
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[62577f9] | 122 | /* |
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| 123 | * Driver configuration parameters |
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| 124 | */ |
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| 125 | uint32_t bsp_clicks_per_usec; |
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[ca680bc5] | 126 | |
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| 127 | /* |
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| 128 | * Use the shared implementations of the following routines. |
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[6ea100c1] | 129 | * Look in rtems/c/src/lib/libbsp/shared/bsplibc.c. |
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[ca680bc5] | 130 | */ |
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| 131 | void bsp_libc_init( void *, uint32_t, int ); |
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| 132 | extern void initialize_exceptions(void); |
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| 133 | extern void cpu_init(void); |
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| 134 | |
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| 135 | void BSP_panic(char *s) |
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| 136 | { |
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| 137 | printk("%s PANIC %s\n",_RTEMS_version, s); |
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| 138 | __asm__ __volatile ("sc"); |
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| 139 | } |
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| 140 | |
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| 141 | void _BSP_Fatal_error(unsigned int v) |
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| 142 | { |
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| 143 | printk("%s PANIC ERROR %x\n",_RTEMS_version, v); |
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| 144 | __asm__ __volatile ("sc"); |
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| 145 | } |
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| 146 | |
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| 147 | /* |
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| 148 | * Function: bsp_pretasking_hook |
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| 149 | * Created: 95/03/10 |
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| 150 | * |
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| 151 | * Description: |
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| 152 | * BSP pretasking hook. Called just before drivers are initialized. |
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| 153 | * Used to setup libc and install any BSP extensions. |
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| 154 | * |
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| 155 | * NOTES: |
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| 156 | * Must not use libc (to do io) from here, since drivers are |
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| 157 | * not yet initialized. |
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| 158 | * |
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| 159 | */ |
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| 160 | |
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| 161 | void |
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| 162 | bsp_pretasking_hook(void) |
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| 163 | { |
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| 164 | /* |
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| 165 | * These are assigned addresses in the linkcmds file for the BSP. This |
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| 166 | * approach is better than having these defined as manifest constants and |
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| 167 | * compiled into the kernel, but it is still not ideal when dealing with |
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| 168 | * multiprocessor configuration in which each board as a different memory |
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| 169 | * map. A better place for defining these symbols might be the makefiles. |
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| 170 | * Consideration should also be given to developing an approach in which |
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| 171 | * the kernel and the application can be linked and burned into ROM |
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| 172 | * independently of each other. |
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| 173 | */ |
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| 174 | |
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| 175 | #if defined(HAS_UBOOT) |
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| 176 | extern unsigned char _HeapStart; |
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| 177 | |
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| 178 | bsp_libc_init( &_HeapStart, |
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| 179 | uboot_bdinfo_ptr->bi_memstart |
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| 180 | + uboot_bdinfo_ptr->bi_memsize |
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| 181 | - (uint32_t)&_HeapStart |
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| 182 | , 0 ); |
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| 183 | #else |
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| 184 | extern unsigned char _HeapStart; |
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| 185 | extern unsigned char _HeapEnd; |
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| 186 | |
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| 187 | bsp_libc_init( &_HeapStart, &_HeapEnd - &_HeapStart, 0 ); |
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| 188 | #endif |
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| 189 | } |
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| 190 | |
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| 191 | void bsp_predriver_hook(void) |
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| 192 | { |
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| 193 | #if 0 |
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| 194 | init_RTC(); |
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| 195 | |
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| 196 | init_PCI(); |
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| 197 | initialize_universe(); |
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| 198 | initialize_PCI_bridge (); |
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| 199 | |
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| 200 | #if (HAS_PMC_PSC8) |
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| 201 | initialize_PMC(); |
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| 202 | #endif |
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| 203 | |
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| 204 | /* |
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| 205 | * Initialize Bsp General purpose vector table. |
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| 206 | */ |
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| 207 | initialize_external_exception_vector(); |
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| 208 | |
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| 209 | #if (0) |
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| 210 | /* |
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| 211 | * XXX - Modify this to write a 48000000 (loop to self) command |
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| 212 | * to each interrupt location. This is better for debug. |
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| 213 | */ |
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| 214 | bsp_spurious_initialize(); |
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| 215 | #endif |
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| 216 | |
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| 217 | #endif |
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| 218 | } |
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| 219 | |
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| 220 | void bsp_start(void) |
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| 221 | { |
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| 222 | extern void *_WorkspaceBase; |
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| 223 | ppc_cpu_id_t myCpu; |
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| 224 | ppc_cpu_revision_t myCpuRevision; |
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| 225 | register unsigned char* intrStack; |
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| 226 | |
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| 227 | /* |
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[6826a4c] | 228 | * Get CPU identification dynamically. Note that the get_ppc_cpu_type() |
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| 229 | * function store the result in global variables so that it can be used |
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| 230 | * later... |
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[ca680bc5] | 231 | */ |
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[7da3405] | 232 | myCpu = get_ppc_cpu_type(); |
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[ca680bc5] | 233 | myCpuRevision = get_ppc_cpu_revision(); |
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| 234 | |
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[6826a4c] | 235 | #if defined(HAS_UBOOT) |
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| 236 | uboot_bdinfo_copy = *uboot_bdinfo_ptr; |
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| 237 | uboot_bdinfo_ptr = &uboot_bdinfo_copy; |
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| 238 | #endif |
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[7da3405] | 239 | |
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[6826a4c] | 240 | #if defined(HAS_UBOOT) && defined(SHOW_MORE_INIT_SETTINGS) |
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| 241 | { |
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| 242 | void dumpUBootBDInfo( bd_t * ); |
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| 243 | dumpUBootBDInfo( uboot_bdinfo_ptr ); |
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| 244 | } |
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| 245 | #endif |
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[7da3405] | 246 | |
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[ca680bc5] | 247 | cpu_init(); |
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| 248 | |
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| 249 | /* |
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| 250 | * Initialize some SPRG registers related to irq handling |
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| 251 | */ |
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| 252 | |
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| 253 | intrStack = (((unsigned char*)&intrStackPtr) - PPC_MINIMUM_STACK_FRAME_SIZE); |
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| 254 | |
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| 255 | _write_SPRG1((unsigned int)intrStack); |
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| 256 | |
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[faf168f] | 257 | bsp_clicks_per_usec = (IPB_CLOCK/1000000); |
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[62577f9] | 258 | |
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[ca680bc5] | 259 | /* |
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| 260 | * Install our own set of exception vectors |
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| 261 | */ |
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| 262 | |
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| 263 | initialize_exceptions(); |
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| 264 | |
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| 265 | /* |
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| 266 | * Enable instruction and data caches. Do not force writethrough mode. |
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| 267 | */ |
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[6826a4c] | 268 | #if INSTRUCTION_CACHE_ENABLE |
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| 269 | rtems_cache_enable_instruction(); |
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| 270 | #endif |
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| 271 | #if DATA_CACHE_ENABLE |
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| 272 | rtems_cache_enable_data(); |
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| 273 | #endif |
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[ca680bc5] | 274 | |
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| 275 | /* |
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| 276 | * Need to "allocate" the memory for the RTEMS Workspace and |
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| 277 | * tell the RTEMS configuration where it is. This memory is |
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| 278 | * not malloc'ed. It is just "pulled from the air". |
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| 279 | */ |
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[5023c874] | 280 | Configuration.work_space_start = (void *)&_WorkspaceBase; |
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[6826a4c] | 281 | #ifdef SHOW_MORE_INIT_SETTINGS |
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| 282 | printk( "workspace=%p\n", Configuration.work_space_start ); |
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| 283 | printk( "workspace size=%d\n", Configuration.work_space_size ); |
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| 284 | #endif |
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[ca680bc5] | 285 | |
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| 286 | /* |
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| 287 | * Initalize RTEMS IRQ system |
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| 288 | */ |
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| 289 | BSP_rtems_irq_mng_init(0); |
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| 290 | |
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[6826a4c] | 291 | /* |
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| 292 | * If the BSP was built with IRQ benchmarking enabled, |
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| 293 | * then intialize it. |
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| 294 | */ |
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| 295 | #if (BENCHMARK_IRQ_PROCESSING == 1) |
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| 296 | BSP_IRQ_Benchmarking_Reset(); |
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| 297 | #endif |
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[5023c874] | 298 | |
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[6826a4c] | 299 | #ifdef SHOW_MORE_INIT_SETTINGS |
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| 300 | printk("Exit from bspstart\n"); |
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| 301 | #endif |
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[ca680bc5] | 302 | |
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[6826a4c] | 303 | } |
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[ca680bc5] | 304 | |
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| 305 | /* |
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| 306 | * |
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| 307 | * _Thread_Idle_body |
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| 308 | * |
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| 309 | * Replaces the one in c/src/exec/score/src/threadidlebody.c |
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| 310 | * The MSR[POW] bit is set to put the CPU into the low power mode |
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| 311 | * defined in HID0. HID0 is set during starup in start.S. |
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| 312 | * |
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| 313 | */ |
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[5023c874] | 314 | Thread _Thread_Idle_body(uint32_t ignored) |
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| 315 | { |
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| 316 | for(;;) { |
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| 317 | asm volatile( |
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| 318 | "mfmsr 3; oris 3,3,4; sync; mtmsr 3; isync; ori 3,3,0; ori 3,3,0" |
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| 319 | ); |
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[ca680bc5] | 320 | } |
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[5023c874] | 321 | return 0; |
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| 322 | } |
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[ca680bc5] | 323 | |
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