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start.S @ efdfd48

4.104.115

Last change on this file since efdfd48 was efdfd48, checked in by Ralf Corsepius <ralf.corsepius@…>, on 11/29/09 at 15:27:07
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1	/===============================================================\
2	\| Project: RTEMS generic MPC5200 BSP \|
3	+-----------------------------------------------------------------+
4	\| Partially based on the code references which are named below. \|
5	\| Adaptions, modifications, enhancements and any recent parts of \|
6	\| the code are: \|
7	\| Copyright (c) 2005 \|
8	\| Embedded Brains GmbH \|
9	\| Obere Lagerstr. 30 \|
10	\| D-82178 Puchheim \|
11	\| Germany \|
12	\| rtems@embedded-brains.de \|
13	+-----------------------------------------------------------------+
14	\| The license and distribution terms for this file may be \|
15	\| found in the file LICENSE in this distribution or at \|
16	\| \|
17	\| http://www.rtems.com/license/LICENSE. \|
18	\| \|
19	+-----------------------------------------------------------------+
20	\| this file contains the startup assembly code \|
21	\===============================================================/
22	/***********************************************************************/
23	/* */
24	/* Module: start.S */
25	/* Date: 07/17/2003 */
26	/* Purpose: RTEMS MPC5x00 CPU assembly startup */
27	/* */
28	/---------------------------------------------------------------------/
29	/* */
30	/* Description: This file contains the assembler portion of MPC5x00 */
31	/* startup code */
32	/* */
33	/---------------------------------------------------------------------/
34	/* */
35	/* Code */
36	/* References: startup code for Motorola PQII ADS board */
37	/* Module: start.S */
38	/* Project: RTEMS 4.6.0pre1 / MCF8260ads BSP */
39	/* Version 1.2 */
40	/* Date: 04/18/2002 */
41	/* */
42	/* Author(s) / Copyright(s): */
43	/* */
44	/* Modified for the Motorola PQII ADS board by */
45	/* Andy Dachs <a.dachs@sstl.co.uk> 23-11-00. */
46	/* Surrey Satellite Technology Limited */
47	/* */
48	/* I have a proprietary bootloader programmed into the flash */
49	/* on the board which initialises the SDRAM prior to calling */
50	/* this function. */
51	/* */
52	/* This file is based on the one by Jay Monkman (jmonkman@fracsa.com)*/
53	/* which in turn was based on the dlentry.s file for the Papyrus BSP,*/
54	/* written by: */
55	/* */
56	/* Author: Andrew Bray <andy@i-cubed.co.uk> */
57	/* */
58	/* COPYRIGHT (c) 1995 by i-cubed ltd. */
59	/* */
60	/* To anyone who acknowledges that this file is provided "AS IS" */
61	/* without any express or implied warranty: */
62	/* permission to use, copy, modify, and distribute this file */
63	/* for any purpose is hereby granted without fee, provided that */
64	/* the above copyright notice and this notice appears in all */
65	/* copies, and that the name of i-cubed limited not be used in */
66	/* advertising or publicity pertaining to distribution of the */
67	/* software without specific, written prior permission. */
68	/* i-cubed limited makes no representations about the suitability */
69	/* of this software for any purpose. */
70	/* */
71	/---------------------------------------------------------------------/
72	/* */
73	/* Partially based on the code references which are named above. */
74	/* Adaptions, modifications, enhancements and any recent parts of */
75	/* the code are under the right of */
76	/* */
77	/* IPR Engineering, Dachauer StraÃe 38, D-80335 MÃŒnchen */
78	/* Copyright(C) 2003 */
79	/* */
80	/---------------------------------------------------------------------/
81	/* */
82	/* IPR Engineering makes no representation or warranties with */
83	/* respect to the performance of this computer program, and */
84	/* specifically disclaims any responsibility for any damages, */
85	/* special or consequential, connected with the use of this program. */
86	/* */
87	/---------------------------------------------------------------------/
88	/* */
89	/* Version history: 1.0 */
90	/* */
91	/***********************************************************************/
92
93	#include <rtems/powerpc/cache.h>
94
95	#include <bsp.h>
96	#include <bsp/mpc5200.h>
97
98	/* Some register offsets of MPC5x00 memory map registers */
99	.set CS0STR, 0x04
100	.set CS0STP, 0x08
101	.set CS1STR, 0x0C
102	.set CS1STP, 0x10
103	.set SDRAMCS0, 0x34
104	.set SDRAMCS1, 0x38
105	.set BOOTSTR, 0x4C
106	.set BOOTSTP, 0x50
107	.set ADREN, 0x54
108	.set CSSR0, 0x58 /* Critical Interrupt SSR0 (603le only) */
109	.set CSSR1, 0x59 /* Critical Interrupt SSR1 (603le only) */
110	.set CFG, 0x20C
111	.set CSBOOTROM, 0x300
112	.set CSCONTROL, 0x318
113	.set CS1CONF, 0x304
114
115
116	/* Register offsets of MPC5x00 SDRAM memory controller registers */
117	.set MOD, 0x100
118	.set CTRL, 0x104
119	.set CFG1, 0x108
120	.set CFG2, 0x10C
121	.set ADRSEL, 0x110
122
123	/* Register offsets of MPC5x00 GPIO registers needed */
124	.set GPIOPCR, 0xb00
125	.set GPIOWE, 0xc00
126	.set GPIOWOD, 0xc04
127	.set GPIOWDD, 0xc08
128	.set GPIOWDO, 0xc0c
129
130	.set GPIOSEN, 0xb04
131	.set GPIOSDD, 0xb0c
132	.set GPIOSDO, 0xb10
133
134	/* Register offsets of MPC5x00 Arbiter registers */
135	.set ARBCFG, 0x1f40
136	.set ARBMPREN, 0x1f64
137	.set ARBMPRIO, 0x1f68
138	.set ARBSNOOP, 0x1f70
139
140	/* Some bit encodings for MGT5100 registers */
141	.set ADREN_SDRAM_EN, (1<<22)
142	.set ADREN_BOOT_EN, (1<<25)
143	.set ADREN_CS0_EN, (1<<16)
144	.set ADREN_CS1_EN, (1<<17)
145
146	.set CTRL_PRECHARGE, (1<<1)
147	.set CTRL_REFRESH, (1<<2)
148	.set CTRL_BA1, (1<<31)
149
150	.set CSCONF_CE, (1<<12)
151
152	/* Some fixed values for MPC5x00 registers */
153	.set CSBOOTROM_VAL, 0x0101D910
154	.set CSCONTROL_VAL, 0x91000000
155	.set CFG_VAL, 0x00000100
156
157	.extern boot_card
158
159	.section ".entry"
160	PUBLIC_VAR (start)
161	start:
162	/* 1st: initialization work (common for RAM/ROM startup) */
163	mfmsr r30
164	SETBITS r30, r29, MSR_ME\|MSR_RI
165	CLRBITS r30, r29, MSR_EE
166	mtmsr r30 /* Set RI/ME, Clr EE in MSR */
167
168	#if defined(HAS_UBOOT)
169	/* store pointer to UBoot bd_info board info structure */
170	LWI r31,bsp_uboot_board_info_ptr
171	stw r3,0(r31)
172	#endif /* defined(HAS_UBOOT) */
173
174	#if defined(NEED_LOW_LEVEL_INIT)
175	/* initialize the MBAR (common RAM/ROM startup) */
176	LWI r31, MBAR_RESET
177	LWI r29, MBAR
178	rlwinm r30, r29,16,16,31
179	stw r30, 0(r31) /* Set the MBAR */
180	#endif
181
182	LWI r31, MBAR /* set r31 to current MBAR */
183	/* init GPIOPCR */
184	lwz r29,GPIOPCR(r31)
185	LWI r30, GPIOPCR_INITMASK
186	not r30,r30
187	and r29,r29,r30
188	LWI r30, GPIOPCR_INITVAL
189	or r29,r29,r30
190	stw r29, GPIOPCR(r31)
191
192	/* further initialization work (common RAM/ROM startup) */
193	bl TLB_init /* Initialize TLBs */
194
195
196	bl FID_DCache /* Flush, inhibit and disable data cache */
197
198
199	bl IDUL_ICache /* Inhibit, disable and unlock instruction cache */
200
201
202	bl FPU_init /* Initialize FPU */
203
204
205	#if defined(NEED_LOW_LEVEL_INIT)
206	bl SPRG_init /* Initialize special purpose registers */
207	#endif
208
209	#if defined(NEED_LOW_LEVEL_INIT)
210	/* detect RAM/ROM startup (common for RAM/ROM startup) */
211	LWI r20, bsp_rom_start /* set the relocation offset */
212
213
214	LWI r30, CFG_VAL /* get CFG register content */
215	lwz r30, CFG(r31) /* set SDRAM single data rate / XLB_CLK=FVCO/4 / IPB_CLK=XLB_CLK/2 / PCICLK=IPB_CLK */
216
217
218
219	lwz r30, ADREN(r31) /* get content of ADREN */
220
221
222
223	TSTBITS r30, r29, ADREN_BOOT_EN
224	bne skip_ROM_start /* If BOOT_ROM is not enabled, skip further initialization */
225
226	/* do some board dependent configuration (unique for ROM startup) */
227	bl SPRG_brk_init /* Initialize special purpose onchip breakpoint registers */
228
229
230	LWI r30, CSCONTROL_VAL /* get CSCONTROL register content */
231	stw r30, CSCONTROL(r31) /* enable internal/external bus error and master for CS */
232
233
234
235	#ifdef BRS5L
236	LWI r30, CSBOOTROM_VAL
237	stw r30, CSBOOTROM(r31) /* Set CSBOOTROM */
238
239
240	#endif
241
242
243	/* FIXME: map BOOT ROM into final location with CS0 registers */
244	LWI r30, bsp_rom_start
245	rlwinm r30, r30,17,15,31
246	stw r30, CS0STR(r31) /* Set CS0STR */
247
248	LWI r30, bsp_rom_end
249
250	rlwinm r30, r30,17,15,31
251	stw r30, CS0STP(r31) /* Set CS0STP */
252
253	lwz r30, ADREN(r31) /* get content of ADREN */
254	SETBITS r30, r29, ADREN_CS0_EN
255	stw r30, ADREN(r31) /* enable CS0 mapping */
256	isync
257	/* jump to same code in final BOOT ROM location */
258	LWI r30, reloc_in_CS0
259	LWI r29, bsp_ram_start
260	sub r30,r30,r29
261	LWI r29, bsp_rom_start
262	add r30,r30,r29
263	mtctr r30
264	bctr
265
266	reloc_in_CS0:
267	/* disable CSBOOT (or map it to CS0 range) */
268	lwz r30, ADREN(r31) /* get content of ADREN */
269	CLRBITS r30, r29, ADREN_BOOT_EN
270	stw r30, ADREN(r31) /* disable BOOT mapping */
271
272	/* init SDRAM */
273	LWI r30, bsp_ram_start
274	ori r30, r30, 0x1a /* size code: bank is 128MByte */
275	stw r30, SDRAMCS0(r31) /* Set SDRAMCS0 */
276
277	LWI r30, bsp_ram_size
278	srawi r30, r30, 1
279	ori r30, r30, 0x1a /* size code: bank is 128MByte */
280	stw r30, SDRAMCS1(r31) /* Set SDRAMCS1 */
281
282	bl SDRAM_init /* Initialize SDRAM controller */
283
284	/* init arbiter and stuff... */
285	LWI r30, 0x8000a06e
286	stw r30, ARBCFG(r31) /* Set ARBCFG */
287
288	LWI r30, 0x000000ff
289	stw r30, ARBMPREN(r31) /* Set ARBMPREN */
290
291	LWI r30, 0x00001234
292	stw r30, ARBMPRIO(r31) /* Set ARBPRIO */
293
294	LWI r30, 0x0000001e
295	stw r30, ARBSNOOP(r31) /* Set ARBSNOOP */
296	/* copy .text section from ROM to RAM location (unique for ROM startup) */
297	LA r30, bsp_section_text_start /* get start address of text section in RAM */
298
299
300	add r30, r20, r30 /* get start address of text section in ROM (add reloc offset) */
301
302
303	LA r29, bsp_section_text_start /* get start address of text section in RAM */
304
305
306	LA r28, bsp_section_text_size /* get size of RAM image */
307
308
309	bl copy_image /* copy text section from ROM to RAM location */
310
311
312	/* copy .data section from ROM to RAM location (unique for ROM startup) */
313	LA r30, bsp_section_data_start /* get start address of data section in RAM */
314
315
316	add r30, r20, r30 /* get start address of data section in ROM (add reloc offset) */
317
318
319	LA r29, bsp_section_data_start /* get start address of data section in RAM */
320
321
322	LA r28, bsp_section_data_size /* get size of RAM image */
323
324
325	bl copy_image /* copy initialized data section from ROM to RAM location */
326
327
328	LA r29, remap_rom /* get compile time address of label */
329	mtlr r29
330
331	blrl /* now further execution RAM */
332
333	remap_rom:
334	/* remap BOOT ROM to CS0 (common for RAM/ROM startup) */
335	lwz r30, CSBOOTROM(r31) /* get content of CSBOOTROM */
336
337
338
339	CLRBITS r30, r29, CSCONF_CE
340	stw r30, CSBOOTROM(r31) /* disable BOOT CS */
341
342
343
344	lwz r30, ADREN(r31) /* get content of ADREN */
345
346
347
348	mr r29, r30 /* move content of r30 to r29 */
349
350
351	LWI r30, ADREN_BOOT_EN /* mask ADREN_BOOT_EN */
352	andc r29,r29,r30
353
354
355	LWI r30, ADREN_CS0_EN /* unmask ADREN_CS0_EN */
356	or r29,r29,r30
357
358
359	stw r29,ADREN(r31) /* Simultaneous enable CS0 and disable BOOT address space */
360
361
362
363	lwz r30, CSBOOTROM(r31) /* get content of CSBOOTROM */
364
365
366
367	SETBITS r30, r29, CSCONF_CE
368	stw r30, CSBOOTROM(r31) /* disable BOOT CS */
369
370
371
372	skip_ROM_start:
373	/* configure external DPRAM CS1 */
374	LWI r30, 0xFFFFFB10
375	stw r30, CS1CONF(r31)
376
377	/* map external DPRAM (CS1) */
378	LWI r30, bsp_dpram_start
379	srawi r30, r30, 16
380	stw r30, CS1STR(r31)
381
382	LWI r30, bsp_dpram_end
383	srawi r30, r30, 16
384	stw r30, CS1STP(r31)
385
386	lwz r30, ADREN(r31) /* get content of ADREN */
387
388	LWI r29, ADREN_CS1_EN /* unmask ADREN_CS1_EN */
389	or r30, r30,r29
390
391	stw r30, ADREN(r31) /* enable CS1 */
392
393	/* clear entire on chip SRAM (unique for ROM startup) */
394	lis r30, (MBAR+ONCHIP_SRAM_OFFSET)@h /* get start address of onchip SRAM */
395	ori r30, r30,(MBAR+ONCHIP_SRAM_OFFSET)@l
396	LWI r29, ONCHIP_SRAM_SIZE /* get size of onchip SRAM */
397
398	bl clr_mem /* Clear onchip SRAM */
399
400	#endif /* defined(BRS5L) */
401	/* clear .bss section (unique for ROM startup) */
402	LWI r30, bsp_section_bss_start /* get start address of bss section */
403	LWI r29, bsp_section_bss_size /* get size of bss section */
404
405
406	bl clr_mem /* Clear the bss section */
407
408
409	/* set stack pointer (common for RAM/ROM startup) */
410	LA r1, bsp_section_text_start
411	addi r1, r1, -0x10 /* Set up stack pointer = beginning of text section - 0x10 */
412
413	bl __eabi /* Set up EABI and SYSV environment */
414
415	/* enable dynamic power management(common for RAM/ROM startup) */
416	bl PPC_HID0_rd /* Get the content of HID0 */
417
418	SETBITS r30, r29, HID0_DPM
419	bl PPC_HID0_wr /* Set DPM in HID0 */
420
421	/* clear arguments and do further init. in C (common for RAM/ROM startup) */
422
423	/* Clear cmdline */
424	xor r3, r3, r3
425
426	bl SYM (boot_card) /* Call the first C routine */
427
428	#if defined(BRS5L)
429	twiddle:
430	b twiddle /* We don't expect to return from boot_card but if we do */
431	/* wait here for watchdog to kick us into hard reset */
432
433	SDRAM_init:
434	#if defined (BRS5L)
435	/* set GPIO_WKUP7 pin low for 66MHz buffering */
436	/* or high for 133MHz registered buffering */
437	LWI r30, 0x80000000
438
439	lwz r29, GPIOWE(r31)
440	or r29,r29,r30 /* set bit 0 in r29/GPIOWE */
441	stw r29,GPIOWE(r31)
442
443	lwz r29, GPIOWOD(r31)
444	andc r29,r29,r30 /* clear bit 0 in r29/GPIOWOD */
445	stw r29,GPIOWOD(r31)
446
447	lwz r29, GPIOWDO(r31)
448	andc r29,r29,r30 /* clear bit 0 in r29/GPIOWDO */
449	stw r29,GPIOWDO(r31)
450
451	lwz r29, GPIOWDD(r31)
452	or r29,r29,r30 /* set bit 0 in r29/GPIOWDD */
453	stw r29,GPIOWDD(r31)
454
455	/* activate MEM_CS1 output */
456	lwz r29, GPIOPCR(r31)
457	or r29,r29,r30 /* set bit 0 in r29/GPIOPCR */
458	stw r29,GPIOPCR(r31)
459
460	#endif
461	#if 0
462	LWI r30, 0xC2222600 /* Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x2 */
463	stw r30, CFG1(r31) /* Read CAS latency=0x2, Active2Read delay=0x2, Prec.2active delay=0x2 */
464	/* Refr.2No-Read delay=0x06, Write latency=0x0 */
465	#else
466	/* See Erratum 342/339 in MPC5200_Errata_L25R_3_June.pdf: */
467	/* set 5 delays to their maximum to support two banks */
468	LWI r30, 0xCC222600 /* Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x2 */
469	stw r30, CFG1(r31) /* Read CAS latency=0x2, Active2Read delay=0x2, Prec.2active delay=0x2 */
470	/* Refr.2No-Read delay=0x06, Write latency=0x0 */
471	#endif
472
473	LWI r30, 0xCCC70004 /* Burst2Read Prec.delay=0x8, Burst Write delay=0x8 */
474	stw r30, CFG2(r31) /* Burst Read2Write delay=0xB, Burst length=0x7, Read Tap=0x4 */
475
476	#ifdef BRS5L
477	LWI r30, 0xD1470000 /* Mode Set enabled, Clock enabled, Auto refresh enabled, Mem. data drv */
478	stw r30, CTRL(r31) /* Refresh counter=0xFFFF */
479
480
481	#else
482	LWI r30, 0xD04F0000 /* Mode Set enabled, Clock enabled, Auto refresh enabled, Mem. data drv */
483	stw r30, CTRL(r31) /* Refresh counter=0xFFFF */
484
485
486	#endif
487	lwz r30, CTRL(r31)
488
489
490	SETBITS r30, r29, CTRL_PRECHARGE /* send two times precharge */
491	stw r30, CTRL(r31)
492
493
494	stw r30, CTRL(r31)
495
496
497
498	lwz r30, CTRL(r31)
499
500
501	SETBITS r30, r29, CTRL_REFRESH /* send two times refresh */
502	stw r30, CTRL(r31)
503
504
505	stw r30, CTRL(r31)
506
507
508
509	LWI r30, 0x008D0000 /* Op.Mode=0x0, Read CAS latency=0x2, Burst length=0x3, Write strobe puls */
510	stw r30, MOD(r31)
511
512
513
514	lwz r30, CTRL(r31) /* Clock enabled, Auto refresh enabled, Mem. data drv. Refresh counter=0xFFFF */
515
516
517	CLRBITS r30, r29, CTRL_BA1
518	stw r30, CTRL(r31)
519
520
521
522	blr
523
524
525	copy_image:
526	mr r27, r28
527	srwi r28, r28, 2
528	mtctr r28
529
530
531	slwi r28, r28, 2
532	sub r27, r27, r28 /* maybe some residual bytes */
533
534
535	copy_image_word:
536	lswi r28, r30, 0x04
537
538	stswi r28, r29, 0x04 /* do word copy ROM -> RAM */
539
540
541	addi r30, r30, 0x04 /* increment source pointer */
542	addi r29, r29, 0x04 /* increment destination pointer */
543
544	bdnz copy_image_word /* decrement ctr and branch if not 0 */
545
546	cmpwi r27, 0x00 /* copy image finished ? */
547	beq copy_image_end;
548	mtctr r27 /* reload counter for residual bytes */
549	copy_image_byte:
550	lswi r28, r30, 0x01
551
552	stswi r28, r29, 0x01 /* do byte copy ROM -> RAM */
553
554
555	addi r30, r30, 0x01 /* increment source pointer */
556	addi r29, r29, 0x01 /* increment destination pointer */
557
558	bdnz copy_image_byte /* decrement ctr and branch if not 0 */
559
560	copy_image_end:
561	blr
562	#endif /* defined(BRS5L) */
563
564	FID_DCache:
565	mflr r26
566
567	bl PPC_HID0_rd
568	TSTBITS r30, r29, HID0_DCE
569	bne FID_DCache_exit /* If data cache is switched of, skip further actions */
570
571	li r29, PPC_D_CACHE /* 16 Kb data cache on 603e */
572	LWI r28, bsp_section_text_start /* Load base address (begin of RAM) */
573
574	FID_DCache_loop_1:
575	lwz r27, 0(r28) /* Load data at address */
576
577	addi r28, r28, PPC_CACHE_ALIGNMENT /* increment cache line address */
578	subi r29, r29, PPC_CACHE_ALIGNMENT /* increment loop counter */
579	cmpwi r29, 0x0
580	bne FID_DCache_loop_1 /* Loop until cache size is reached */
581
582	li r29, PPC_D_CACHE /* 16 Kb data cache on 603e */
583	LWI r28, bsp_section_text_start /* Reload base address (begin of RAM) */
584	xor r27, r27, r27
585	FID_DCache_loop_2:
586
587	dcbf r27, r28 /* Flush and invalidate cache */
588
589	addi r28, r28, PPC_CACHE_ALIGNMENT /* increment cache line address */
590	subi r29, r29, PPC_CACHE_ALIGNMENT /* increment loop counter */
591	cmpwi r29, 0x0
592	bne FID_DCache_loop_2 /* Loop around until cache size is reached */
593
594	bl PPC_HID0_rd /* Read HID0 */
595	CLRBITS r30, r29, HID0_DCE
596	bl PPC_HID0_wr /* Clear DCE */
597
598	FID_DCache_exit:
599	mtlr r26
600	blr
601
602	IDUL_ICache:
603	mflr r26
604
605	bl PPC_HID0_rd
606	TSTBITS r30, r29, HID0_ICE
607	bne IDUL_ICache_exit /* If instruction cache is switched of, skip further actions */
608
609	CLRBITS r30, r29, HID0_ICE
610	bl PPC_HID0_wr /* Disable ICE bit */
611
612	SETBITS r30, r29, HID0_ICFI
613	bl PPC_HID0_wr /* Invalidate instruction cache */
614
615	CLRBITS r30, r29, HID0_ICFI
616	bl PPC_HID0_wr /* Disable cache invalidate */
617
618	CLRBITS r30, r29, HID0_ILOCK
619	bl PPC_HID0_wr /* Disable instruction cache lock */
620
621	IDUL_ICache_exit:
622	mtlr r26
623	blr
624
625
626	TLB_init: /* Initialize translation lookaside buffers (TLBs) */
627	xor r30, r30, r30
628	xor r29, r29, r29
629
630	TLB_init_loop:
631	tlbie r29
632	tlbsync
633	addi r29, r29, 0x1000
634	addi r30, r30, 0x01
635	cmpli 0, 0, r30, 0x0080
636	bne TLB_init_loop
637	blr
638
639	FPU_init:
640	mfmsr r30 /* get content of MSR */
641
642
643	SETBITS r30, r29, MSR_FP
644	mtmsr r30 /* enable FPU and FPU exceptions */
645
646	#if 0
647	LA r29, bsp_ram_start
648	stw r29, 0x0(r29)
649	#endif
650
651	lfd f0, 0(r29)
652	fmr f1, f0
653	fmr f2, f0
654	fmr f3, f0
655	fmr f4, f0
656	fmr f5, f0
657	fmr f6, f0
658	fmr f7, f0
659	fmr f8, f0
660	fmr f9, f0
661	fmr f10, f0
662	fmr f11, f0
663	fmr f12, f0
664	fmr f13, f0
665	fmr f14, f0
666	fmr f15, f0
667	fmr f16, f0
668	fmr f17, f0
669	fmr f18, f0
670	fmr f19, f0
671	fmr f20, f0
672	fmr f21, f0
673	fmr f22, f0
674	fmr f23, f0
675	fmr f24, f0
676	fmr f25, f0
677	fmr f26, f0
678	fmr f27, f0
679	fmr f28, f0
680	fmr f29, f0
681	fmr f30, f0
682	fmr f31, f0
683
684
685	mtfsfi 0, 0 /* initialize bit positons in FPSCR */
686	mtfsfi 1, 0
687	mtfsfi 2, 0
688	mtfsfi 3, 0
689	mtfsfi 4, 0
690	mtfsfi 5, 0
691	mtfsfi 6, 0
692	mtfsfi 7, 0
693
694	blr
695
696	SPRG_init: /* initialize registers */
697	xor r30, r30, r30
698
699	mtspr XER, r30
700	mtspr CTR, r30
701	mtspr DSISR, r30
702	mtspr DAR, r30
703	mtspr DEC, r30
704	mtspr SDR1, r30
705	mtspr SRR0, r30
706	mtspr SRR1, r30
707	mtspr CSSR0, r30
708	mtspr CSSR1, r30
709	mtspr SPRG0, r30
710	mtspr SPRG1, r30
711	mtspr SPRG2, r30
712	mtspr SPRG3, r30
713	mtspr SPRG4, r30
714	mtspr SPRG5, r30
715	mtspr SPRG6, r30
716	mtspr SPRG7, r30
717	mtspr EAR, r30
718	mtspr TBWU, r30
719	mtspr TBWL, r30
720	mtspr IBAT0U, r30
721	mtspr IBAT0L, r30
722	mtspr IBAT1U, r30
723	mtspr IBAT1L, r30
724	mtspr IBAT2U, r30
725	mtspr IBAT2L, r30
726	mtspr IBAT3U, r30
727	mtspr IBAT3L, r30
728	mtspr IBAT4U, r30
729	mtspr IBAT4L, r30
730	mtspr IBAT5U, r30
731	mtspr IBAT5L, r30
732	mtspr IBAT6U, r30
733	mtspr IBAT6L, r30
734	mtspr IBAT7U, r30
735	mtspr IBAT7L, r30
736	mtspr DBAT0U, r30
737	mtspr DBAT0L, r30
738	mtspr DBAT1U, r30
739	mtspr DBAT1L, r30
740	mtspr DBAT2U, r30
741	mtspr DBAT2L, r30
742	mtspr DBAT3U, r30
743	mtspr DBAT3L, r30
744	mtspr DBAT4U, r30
745	mtspr DBAT4L, r30
746	mtspr DBAT5U, r30
747	mtspr DBAT5L, r30
748	mtspr DBAT6U, r30
749	mtspr DBAT6L, r30
750	mtspr DBAT7U, r30
751	mtspr DBAT7L, r30
752	mtspr DMISS, r30
753	mtspr DCMP, r30
754	mtspr HASH1, r30
755	mtspr HASH2, r30
756	mtspr IMISS, r30
757	mtspr ICMP, r30
758	mtspr RPA, r30
759	mtsr SR0, r30
760	mtsr SR1, r30
761	mtsr SR2, r30
762	mtsr SR3, r30
763	mtsr SR4, r30
764	mtsr SR5, r30
765	mtsr SR6, r30
766	mtsr SR7, r30
767	mtsr SR8, r30
768	mtsr SR9, r30
769	mtsr SR10, r30
770	mtsr SR12, r30
771	mtsr SR13, r30
772	mtsr SR14, r30
773	mtsr SR15, r30
774
775
776
777
778
779	blr
780
781	SPRG_brk_init:
782	xor r30, r30, r30
783
784	mtspr DABR2, r30
785	mtspr DBCR, r30
786	mtspr IBCR, r30
787	mtspr IABR, r30
788	mtspr HID2, r30
789	mtspr DABR, r30
790	mtspr IABR2, r30
791
792
793
794
795	blr
796
797
798	PPC_HID0_rd: /* get HID0 content to r30 */
799
800
801	mfspr r30, HID0
802
803	blr
804
805
806	PPC_HID0_wr: /* put r30 content to HID0 */
807
808
809	mtspr HID0, r30
810
811	blr
812
813	clr_mem:
814	mr r28, r29
815	srwi r29, r29, 2
816	mtctr r29 /* set ctr reg */
817
818
819	slwi r29, r29, 2
820	sub r28, r28, r29 /* maybe some residual bytes */
821	xor r29, r29, r29
822
823
824	clr_mem_word:
825	stswi r29, r30, 0x04 /* store r29 (word) to r30 memory location */
826	addi r30, r30, 0x04 /* increment r30 */
827
828	bdnz clr_mem_word /* dec counter and loop */
829
830
831	cmpwi r28, 0x00 /* clear mem. finished ? */
832	beq clr_mem_end;
833	mtctr r28 /* reload counter for residual bytes */
834	clr_mem_byte:
835	stswi r29, r30, 0x01 /* store r29 (byte) to r30 memory location */
836	addi r30, r30, 0x01 /* update r30 */
837
838	bdnz clr_mem_byte /* dec counter and loop */
839
840	clr_mem_end:
841	blr /* return */
842
843
844

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