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start.S @ dbe6aae7

4.115

Last change on this file since dbe6aae7 was dbe6aae7, checked in by Sebastian Huber <sebastian.huber@…>, on 04/19/13 at 11:51:54
bsp/mpc5200: Move CSBOOTROM_VAL definition
Property mode set to `100644`
File size: 23.6 KB

Line
1	/===============================================================\
2	\| Project: RTEMS generic MPC5200 BSP \|
3	+-----------------------------------------------------------------+
4	\| Partially based on the code references which are named below. \|
5	\| Adaptions, modifications, enhancements and any recent parts of \|
6	\| the code are: \|
7	\| Copyright (c) 2005 \|
8	\| Embedded Brains GmbH \|
9	\| Obere Lagerstr. 30 \|
10	\| D-82178 Puchheim \|
11	\| Germany \|
12	\| rtems@embedded-brains.de \|
13	+-----------------------------------------------------------------+
14	\| The license and distribution terms for this file may be \|
15	\| found in the file LICENSE in this distribution or at \|
16	\| \|
17	\| http://www.rtems.com/license/LICENSE. \|
18	\| \|
19	+-----------------------------------------------------------------+
20	\| this file contains the startup assembly code \|
21	\===============================================================/
22	/***********************************************************************/
23	/* */
24	/* Module: start.S */
25	/* Date: 07/17/2003 */
26	/* Purpose: RTEMS MPC5x00 CPU assembly startup */
27	/* */
28	/---------------------------------------------------------------------/
29	/* */
30	/* Description: This file contains the assembler portion of MPC5x00 */
31	/* startup code */
32	/* */
33	/---------------------------------------------------------------------/
34	/* */
35	/* Code */
36	/* References: startup code for Motorola PQII ADS board */
37	/* Module: start.S */
38	/* Project: RTEMS 4.6.0pre1 / MCF8260ads BSP */
39	/* Version 1.2 */
40	/* Date: 04/18/2002 */
41	/* */
42	/* Author(s) / Copyright(s): */
43	/* */
44	/* Modified for the Motorola PQII ADS board by */
45	/* Andy Dachs <a.dachs@sstl.co.uk> 23-11-00. */
46	/* Surrey Satellite Technology Limited */
47	/* */
48	/* I have a proprietary bootloader programmed into the flash */
49	/* on the board which initialises the SDRAM prior to calling */
50	/* this function. */
51	/* */
52	/* This file is based on the one by Jay Monkman (jmonkman@fracsa.com)*/
53	/* which in turn was based on the dlentry.s file for the Papyrus BSP,*/
54	/* written by: */
55	/* */
56	/* Author: Andrew Bray <andy@i-cubed.co.uk> */
57	/* */
58	/* COPYRIGHT (c) 1995 by i-cubed ltd. */
59	/* */
60	/* To anyone who acknowledges that this file is provided "AS IS" */
61	/* without any express or implied warranty: */
62	/* permission to use, copy, modify, and distribute this file */
63	/* for any purpose is hereby granted without fee, provided that */
64	/* the above copyright notice and this notice appears in all */
65	/* copies, and that the name of i-cubed limited not be used in */
66	/* advertising or publicity pertaining to distribution of the */
67	/* software without specific, written prior permission. */
68	/* i-cubed limited makes no representations about the suitability */
69	/* of this software for any purpose. */
70	/* */
71	/---------------------------------------------------------------------/
72	/* */
73	/* Partially based on the code references which are named above. */
74	/* Adaptions, modifications, enhancements and any recent parts of */
75	/* the code are under the right of */
76	/* */
77	/* IPR Engineering, Dachauer StraÃe 38, D-80335 MÃŒnchen */
78	/* Copyright(C) 2003 */
79	/* */
80	/---------------------------------------------------------------------/
81	/* */
82	/* IPR Engineering makes no representation or warranties with */
83	/* respect to the performance of this computer program, and */
84	/* specifically disclaims any responsibility for any damages, */
85	/* special or consequential, connected with the use of this program. */
86	/* */
87	/---------------------------------------------------------------------/
88	/* */
89	/* Version history: 1.0 */
90	/* */
91	/***********************************************************************/
92
93	#include <rtems/powerpc/cache.h>
94
95	#include <bsp.h>
96	#include <bsp/mpc5200.h>
97
98	/* Some register offsets of MPC5x00 memory map registers */
99	.set CS0STR, 0x04
100	.set CS0STP, 0x08
101	.set CS1STR, 0x0C
102	.set CS1STP, 0x10
103	.set SDRAMCS0, 0x34
104	.set SDRAMCS1, 0x38
105	.set BOOTSTR, 0x4C
106	.set BOOTSTP, 0x50
107	.set ADREN, 0x54
108	.set CSSR0, 0x58 /* Critical Interrupt SSR0 (603le only) */
109	.set CSSR1, 0x59 /* Critical Interrupt SSR1 (603le only) */
110	.set CFG, 0x20C
111	.set CSBOOTROM, 0x300
112	.set CSCONTROL, 0x318
113	.set CS1CONF, 0x304
114
115
116	/* Register offsets of MPC5x00 SDRAM memory controller registers */
117	.set MOD, 0x100
118	.set CTRL, 0x104
119	.set CFG1, 0x108
120	.set CFG2, 0x10C
121	.set ADRSEL, 0x110
122
123	/* Register offsets of MPC5x00 GPIO registers needed */
124	.set GPIOPCR, 0xb00
125	.set GPIOWE, 0xc00
126	.set GPIOWOD, 0xc04
127	.set GPIOWDD, 0xc08
128	.set GPIOWDO, 0xc0c
129
130	.set GPIOSEN, 0xb04
131	.set GPIOSDD, 0xb0c
132	.set GPIOSDO, 0xb10
133
134	/* Register offsets of MPC5x00 Arbiter registers */
135	.set ARBCFG, 0x1f40
136	.set ARBADRTO, 0x1f58
137	.set ARBDATTO, 0x1f5c
138	.set ARBMPREN, 0x1f64
139	.set ARBMPRIO, 0x1f68
140	.set ARBSNOOP, 0x1f70
141
142	/* Some bit encodings for MGT5100 registers */
143	.set ADREN_BOOT_EN, (1 << (31 - 6))
144	.set ADREN_CS0_EN, (1 << (31 - 15))
145	.set ADREN_CS1_EN, (1 << (31 - 14))
146	.set ADREN_WSE, (1 << (31 - 31))
147
148	.set CTRL_PRECHARGE, (1<<1)
149	.set CTRL_REFRESH, (1<<2)
150	.set CTRL_BA1, (1<<31)
151
152	.set CSCONF_CE, (1<<12)
153
154	/* Some fixed values for MPC5x00 registers */
155	.set CSCONTROL_VAL, 0x91000000
156
157	/*
158	* The DDR_MODE bit is a read-only status and should be written as 0.
159	*
160	* XLB_CLK = FVCO / 4
161	* IPB_CLK = XLB_CLK / 2
162	* PCI_CLK = IPB_CLK
163	*/
164	.set CFG_VAL, 0x00000100
165
166	.extern boot_card
167
168	.section ".vectors", "ax"
169	bl start
170	.rep 63
171	.long 0x04000400
172	.endr
173	__vec2: b __vec2
174	.rep 63
175	.long 0x04000400
176	.endr
177	__vec3: b __vec3
178	.rep 63
179	.long 0x04000400
180	.endr
181	__vec4: b __vec4
182	.rep 63
183	.long 0x04000400
184	.endr
185	__vec5: b __vec5
186	.rep 63
187	.long 0x04000400
188	.endr
189	__vec6: b __vec6
190	.rep 63
191	.long 0x04000400
192	.endr
193	__vec7: b __vec7
194	.rep 63
195	.long 0x04000400
196	.endr
197	__vec8: b __vec8
198	.rep 63
199	.long 0x04000400
200	.endr
201	__vec9: b __vec9
202	.rep 63
203	.long 0x04000400
204	.endr
205	__veca: b __veca
206	.rep 63
207	.long 0x04000400
208	.endr
209	__vecb: b __vecb
210	.rep 63
211	.long 0x04000400
212	.endr
213	__vecc: b __vecc
214	.rep 63
215	.long 0x04000400
216	.endr
217	__vecd: b __vecd
218	.rep 63
219	.long 0x04000400
220	.endr
221	__vece: b __vece
222	.rep 63
223	.long 0x04000400
224	.endr
225	__vecf: b __vecf
226	.rep 63+1024
227	.long 0x04000400
228	.endr
229
230	.section ".entry"
231	PUBLIC_VAR (start)
232	start:
233	/* 1st: initialization work (common for RAM/ROM startup) */
234	mfmsr r30
235	SETBITS r30, r29, MSR_ME\|MSR_RI
236	CLRBITS r30, r29, MSR_EE
237	mtmsr r30 /* Set RI/ME, Clr EE in MSR */
238
239	#ifdef HAS_UBOOT
240	mr r14, r3
241	#endif /* HAS_UBOOT */
242
243	#if defined(NEED_LOW_LEVEL_INIT)
244	/* initialize the MBAR (common RAM/ROM startup) */
245	LWI r31, MBAR_RESET
246	LWI r29, MBAR
247	rlwinm r30, r29,16,16,31
248	stw r30, 0(r31) /* Set the MBAR */
249	#endif
250
251	LWI r31, MBAR /* set r31 to current MBAR */
252	/* init GPIOPCR */
253	lwz r29,GPIOPCR(r31)
254	LWI r30, BSP_GPIOPCR_INITMASK
255	not r30,r30
256	and r29,r29,r30
257	LWI r30, BSP_GPIOPCR_INITVAL
258	or r29,r29,r30
259	stw r29, GPIOPCR(r31)
260
261	/* further initialization work (common RAM/ROM startup) */
262	bl TLB_init /* Initialize TLBs */
263
264
265	bl FID_DCache /* Flush, inhibit and disable data cache */
266
267
268	bl IDUL_ICache /* Inhibit, disable and unlock instruction cache */
269
270
271	bl FPU_init /* Initialize FPU */
272
273
274	#if defined(NEED_LOW_LEVEL_INIT)
275	bl SPRG_init /* Initialize special purpose registers */
276	#endif
277
278	#if defined(NEED_LOW_LEVEL_INIT)
279	/* detect RAM/ROM startup (common for RAM/ROM startup) */
280	LWI r20, bsp_rom_start /* set the relocation offset */
281
282
283	LWI r30, CFG_VAL /* get CFG register content */
284	lwz r30, CFG(r31) /* set CFG register */
285
286
287
288	lwz r30, ADREN(r31) /* get content of ADREN */
289
290
291
292	TSTBITS r30, r29, ADREN_BOOT_EN
293	bne skip_ROM_start /* If BOOT_ROM is not enabled, skip further initialization */
294
295	/* do some board dependent configuration (unique for ROM startup) */
296	LWI r30, CSCONTROL_VAL /* get CSCONTROL register content */
297	stw r30, CSCONTROL(r31) /* enable internal/external bus error and master for CS */
298
299
300	#if defined(MPC5200_BOARD_BRS5L)
301	#define CSBOOTROM_VAL 0x0101D910
302	#endif
303
304	#ifdef CSBOOTROM_VAL
305	LWI r30, CSBOOTROM_VAL
306	stw r30, CSBOOTROM(r31) /* Set CSBOOTROM */
307	#endif
308
309	/* FIXME: map BOOT ROM into final location with CS0 registers */
310	LWI r30, bsp_rom_start
311	rlwinm r30, r30,17,15,31
312	stw r30, CS0STR(r31) /* Set CS0STR */
313
314	LWI r30, bsp_rom_end - 1
315
316	rlwinm r30, r30,17,15,31
317	stw r30, CS0STP(r31) /* Set CS0STP */
318
319	lwz r30, ADREN(r31) /* get content of ADREN */
320	SETBITS r30, r29, ADREN_CS0_EN
321	stw r30, ADREN(r31) /* enable CS0 mapping */
322	isync
323	/* jump to same code in final BOOT ROM location */
324	LWI r30, reloc_in_CS0
325	LWI r29, bsp_ram_start
326	sub r30,r30,r29
327	LWI r29, bsp_rom_start
328	add r30,r30,r29
329	mtctr r30
330	bctr
331
332	reloc_in_CS0:
333	/* disable CSBOOT (or map it to CS0 range) */
334	lwz r30, ADREN(r31) /* get content of ADREN */
335	CLRBITS r30, r29, ADREN_BOOT_EN
336	stw r30, ADREN(r31) /* disable BOOT mapping */
337
338	/* init SDRAM */
339	LWI r30, bsp_ram_start
340	ori r30, r30, 0x1a /* size code: bank is 128MByte */
341	stw r30, SDRAMCS0(r31) /* Set SDRAMCS0 */
342
343	LWI r30, bsp_ram_size
344	srawi r30, r30, 1
345	ori r30, r30, 0x1a /* size code: bank is 128MByte */
346	stw r30, SDRAMCS1(r31) /* Set SDRAMCS1 */
347
348	bl SDRAM_init /* Initialize SDRAM controller */
349
350	bl XLB_init
351	/* copy .text section from ROM to RAM location (unique for ROM startup) */
352	LA r30, bsp_section_text_start /* get start address of text section in RAM */
353
354
355	add r30, r20, r30 /* get start address of text section in ROM (add reloc offset) */
356
357
358	LA r29, bsp_section_text_start /* get start address of text section in RAM */
359
360
361	LA r28, bsp_section_text_size /* get size of RAM image */
362
363
364	bl copy_image /* copy text section from ROM to RAM location */
365
366
367	/* copy .data section from ROM to RAM location (unique for ROM startup) */
368	LA r30, bsp_section_data_start /* get start address of data section in RAM */
369
370
371	add r30, r20, r30 /* get start address of data section in ROM (add reloc offset) */
372
373
374	LA r29, bsp_section_data_start /* get start address of data section in RAM */
375
376
377	LA r28, bsp_section_data_size /* get size of RAM image */
378
379
380	bl copy_image /* copy initialized data section from ROM to RAM location */
381
382
383	LA r29, remap_rom /* get compile time address of label */
384	mtlr r29
385
386	blrl /* now further execution RAM */
387
388	remap_rom:
389	/* remap BOOT ROM to CS0 (common for RAM/ROM startup) */
390	lwz r30, CSBOOTROM(r31) /* get content of CSBOOTROM */
391
392
393
394	CLRBITS r30, r29, CSCONF_CE
395	stw r30, CSBOOTROM(r31) /* disable BOOT CS */
396
397
398
399	lwz r30, ADREN(r31) /* get content of ADREN */
400
401
402
403	mr r29, r30 /* move content of r30 to r29 */
404
405
406	LWI r30, ADREN_BOOT_EN /* mask ADREN_BOOT_EN */
407	andc r29,r29,r30
408
409
410	LWI r30, ADREN_CS0_EN /* unmask ADREN_CS0_EN */
411	or r29,r29,r30
412
413
414	stw r29,ADREN(r31) /* Simultaneous enable CS0 and disable BOOT address space */
415
416
417
418	lwz r30, CSBOOTROM(r31) /* get content of CSBOOTROM */
419
420
421
422	SETBITS r30, r29, CSCONF_CE
423	stw r30, CSBOOTROM(r31) /* disable BOOT CS */
424
425
426
427	skip_ROM_start:
428	/* configure external DPRAM CS1 */
429	LWI r30, 0xFFFFFB10
430	stw r30, CS1CONF(r31)
431
432	/* map external DPRAM (CS1) */
433	LWI r30, bsp_dpram_start
434	srawi r30, r30, 16
435	stw r30, CS1STR(r31)
436
437	LWI r30, bsp_dpram_end
438	srawi r30, r30, 16
439	stw r30, CS1STP(r31)
440
441	lwz r30, ADREN(r31) /* get content of ADREN */
442
443	LWI r29, ADREN_CS1_EN /* unmask ADREN_CS1_EN */
444	or r30, r30,r29
445
446	stw r30, ADREN(r31) /* enable CS1 */
447
448	/* clear entire on chip SRAM (unique for ROM startup) */
449	lis r30, (MBAR+ONCHIP_SRAM_OFFSET)@h /* get start address of onchip SRAM */
450	ori r30, r30,(MBAR+ONCHIP_SRAM_OFFSET)@l
451	LWI r29, ONCHIP_SRAM_SIZE /* get size of onchip SRAM */
452
453	bl clr_mem /* Clear onchip SRAM */
454
455	#else /* defined(NEED_LOW_LEVEL_INIT) */
456	bl XLB_init
457	#endif /* defined(NEED_LOW_LEVEL_INIT) */
458	/* clear .bss section (unique for ROM startup) */
459	LWI r30, bsp_section_bss_start /* get start address of bss section */
460	LWI r29, bsp_section_bss_size /* get size of bss section */
461
462
463	bl clr_mem /* Clear the bss section */
464
465	#ifdef HAS_UBOOT
466	mr r3, r14
467	bl bsp_uboot_copy_board_info
468	#endif /* HAS_UBOOT */
469
470	/* set stack pointer (common for RAM/ROM startup) */
471	LA r1, bsp_section_text_start
472	addi r1, r1, -0x10 /* Set up stack pointer = beginning of text section - 0x10 */
473	/* tag TOS with a NULL pointer (termination mark for stack dump) */
474	li r0, 0
475	stw r0, 0(r1)
476
477	bl __eabi /* Set up EABI and SYSV environment */
478
479	/* enable dynamic power management(common for RAM/ROM startup) */
480	bl PPC_HID0_rd /* Get the content of HID0 */
481
482	SETBITS r30, r29, HID0_DPM
483	bl PPC_HID0_wr /* Set DPM in HID0 */
484
485	/* clear arguments and do further init. in C (common for RAM/ROM startup) */
486
487	/* Clear cmdline */
488	xor r3, r3, r3
489
490	bl SYM (boot_card) /* Call the first C routine */
491
492	twiddle:
493	b twiddle /* We don't expect to return from boot_card but if we do */
494	/* wait here for watchdog to kick us into hard reset */
495
496	#if defined(NEED_LOW_LEVEL_INIT)
497	SDRAM_init:
498	#if defined(MPC5200_BOARD_BRS5L)
499	/* set GPIO_WKUP7 pin low for 66MHz buffering */
500	/* or high for 133MHz registered buffering */
501	LWI r30, 0x80000000
502
503	lwz r29, GPIOWE(r31)
504	or r29,r29,r30 /* set bit 0 in r29/GPIOWE */
505	stw r29,GPIOWE(r31)
506
507	lwz r29, GPIOWOD(r31)
508	andc r29,r29,r30 /* clear bit 0 in r29/GPIOWOD */
509	stw r29,GPIOWOD(r31)
510
511	lwz r29, GPIOWDO(r31)
512	andc r29,r29,r30 /* clear bit 0 in r29/GPIOWDO */
513	stw r29,GPIOWDO(r31)
514
515	lwz r29, GPIOWDD(r31)
516	or r29,r29,r30 /* set bit 0 in r29/GPIOWDD */
517	stw r29,GPIOWDD(r31)
518
519	/* activate MEM_CS1 output */
520	lwz r29, GPIOPCR(r31)
521	or r29,r29,r30 /* set bit 0 in r29/GPIOPCR */
522	stw r29,GPIOPCR(r31)
523
524	#endif
525	LWI r30, 0xC4222600 /* Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x4 */
526	stw r30, CFG1(r31) /* Read CAS latency=0x2, Active2Read delay=0x2, Prec.2active delay=0x2 */
527	/* Refr.2No-Read delay=0x06, Write latency=0x0 */
528
529	LWI r30, 0xCCC70004 /* Burst2Read Prec.delay=0x8, Burst Write delay=0x8 */
530	stw r30, CFG2(r31) /* Burst Read2Write delay=0xB, Burst length=0x7, Read Tap=0x4 */
531
532	#ifdef MPC5200_BOARD_BRS5L
533	LWI r30, 0xD1470000 /* Mode Set enabled, Clock enabled, Auto refresh enabled, Mem. data drv */
534	stw r30, CTRL(r31) /* Refresh counter=0xFFFF */
535
536
537	#else
538	LWI r30, 0xD04F0000 /* Mode Set enabled, Clock enabled, Auto refresh enabled, Mem. data drv */
539	stw r30, CTRL(r31) /* Refresh counter=0xFFFF */
540
541
542	#endif
543	lwz r30, CTRL(r31)
544
545
546	SETBITS r30, r29, CTRL_PRECHARGE /* send two times precharge */
547	stw r30, CTRL(r31)
548
549
550	stw r30, CTRL(r31)
551
552
553
554	lwz r30, CTRL(r31)
555
556
557	SETBITS r30, r29, CTRL_REFRESH /* send two times refresh */
558	stw r30, CTRL(r31)
559
560
561	stw r30, CTRL(r31)
562
563
564
565	LWI r30, 0x008D0000 /* Op.Mode=0x0, Read CAS latency=0x2, Burst length=0x3, Write strobe puls */
566	stw r30, MOD(r31)
567
568
569
570	lwz r30, CTRL(r31) /* Clock enabled, Auto refresh enabled, Mem. data drv. Refresh counter=0xFFFF */
571
572
573	CLRBITS r30, r29, CTRL_BA1
574	stw r30, CTRL(r31)
575
576
577
578	blr
579
580
581	copy_image:
582	mr r27, r28
583	srwi r28, r28, 2
584	mtctr r28
585
586
587	slwi r28, r28, 2
588	sub r27, r27, r28 /* maybe some residual bytes */
589
590
591	copy_image_word:
592	lswi r28, r30, 0x04
593
594	stswi r28, r29, 0x04 /* do word copy ROM -> RAM */
595
596
597	addi r30, r30, 0x04 /* increment source pointer */
598	addi r29, r29, 0x04 /* increment destination pointer */
599
600	bdnz copy_image_word /* decrement ctr and branch if not 0 */
601
602	cmpwi r27, 0x00 /* copy image finished ? */
603	beq copy_image_end;
604	mtctr r27 /* reload counter for residual bytes */
605	copy_image_byte:
606	lswi r28, r30, 0x01
607
608	stswi r28, r29, 0x01 /* do byte copy ROM -> RAM */
609
610
611	addi r30, r30, 0x01 /* increment source pointer */
612	addi r29, r29, 0x01 /* increment destination pointer */
613
614	bdnz copy_image_byte /* decrement ctr and branch if not 0 */
615
616	copy_image_end:
617	blr
618	#endif /* defined(NEED_LOW_LEVEL_INIT) */
619
620	FID_DCache:
621	mflr r26
622
623	bl PPC_HID0_rd
624	TSTBITS r30, r29, HID0_DCE
625	bne FID_DCache_exit /* If data cache is switched of, skip further actions */
626
627	li r29, PPC_D_CACHE /* 16 Kb data cache on 603e */
628	LWI r28, bsp_section_text_start /* Load base address (begin of RAM) */
629
630	FID_DCache_loop_1:
631	lwz r27, 0(r28) /* Load data at address */
632
633	addi r28, r28, PPC_CACHE_ALIGNMENT /* increment cache line address */
634	subi r29, r29, PPC_CACHE_ALIGNMENT /* increment loop counter */
635	cmpwi r29, 0x0
636	bne FID_DCache_loop_1 /* Loop until cache size is reached */
637
638	li r29, PPC_D_CACHE /* 16 Kb data cache on 603e */
639	LWI r28, bsp_section_text_start /* Reload base address (begin of RAM) */
640	xor r27, r27, r27
641	FID_DCache_loop_2:
642
643	dcbf r27, r28 /* Flush and invalidate cache */
644
645	addi r28, r28, PPC_CACHE_ALIGNMENT /* increment cache line address */
646	subi r29, r29, PPC_CACHE_ALIGNMENT /* increment loop counter */
647	cmpwi r29, 0x0
648	bne FID_DCache_loop_2 /* Loop around until cache size is reached */
649
650	bl PPC_HID0_rd /* Read HID0 */
651	CLRBITS r30, r29, HID0_DCE
652	bl PPC_HID0_wr /* Clear DCE */
653
654	FID_DCache_exit:
655	mtlr r26
656	blr
657
658	IDUL_ICache:
659	mflr r26
660
661	bl PPC_HID0_rd
662	TSTBITS r30, r29, HID0_ICE
663	bne IDUL_ICache_exit /* If instruction cache is switched of, skip further actions */
664
665	CLRBITS r30, r29, HID0_ICE
666	bl PPC_HID0_wr /* Disable ICE bit */
667
668	SETBITS r30, r29, HID0_ICFI
669	bl PPC_HID0_wr /* Invalidate instruction cache */
670
671	CLRBITS r30, r29, HID0_ICFI
672	bl PPC_HID0_wr /* Disable cache invalidate */
673
674	CLRBITS r30, r29, HID0_ILOCK
675	bl PPC_HID0_wr /* Disable instruction cache lock */
676
677	IDUL_ICache_exit:
678	mtlr r26
679	blr
680
681
682	TLB_init: /* Initialize translation lookaside buffers (TLBs) */
683	xor r30, r30, r30
684	xor r29, r29, r29
685
686	TLB_init_loop:
687	tlbie r29
688	tlbsync
689	addi r29, r29, 0x1000
690	addi r30, r30, 0x01
691	cmpli 0, 0, r30, 0x0080
692	bne TLB_init_loop
693	blr
694
695	FPU_init:
696	mfmsr r30 /* get content of MSR */
697
698
699	SETBITS r30, r29, MSR_FP
700	mtmsr r30 /* enable FPU and FPU exceptions */
701	sync
702
703	lfd f0, 0(r29)
704	fmr f1, f0
705	fmr f2, f0
706	fmr f3, f0
707	fmr f4, f0
708	fmr f5, f0
709	fmr f6, f0
710	fmr f7, f0
711	fmr f8, f0
712	fmr f9, f0
713	fmr f10, f0
714	fmr f11, f0
715	fmr f12, f0
716	fmr f13, f0
717	fmr f14, f0
718	fmr f15, f0
719	fmr f16, f0
720	fmr f17, f0
721	fmr f18, f0
722	fmr f19, f0
723	fmr f20, f0
724	fmr f21, f0
725	fmr f22, f0
726	fmr f23, f0
727	fmr f24, f0
728	fmr f25, f0
729	fmr f26, f0
730	fmr f27, f0
731	fmr f28, f0
732	fmr f29, f0
733	fmr f30, f0
734	fmr f31, f0
735
736
737	mtfsfi 0, 0 /* initialize bit positons in FPSCR */
738	mtfsfi 1, 0
739	mtfsfi 2, 0
740	mtfsfi 3, 0
741	mtfsfi 4, 0
742	mtfsfi 5, 0
743	mtfsfi 6, 0
744	mtfsfi 7, 0
745
746	blr
747
748	SPRG_init: /* initialize registers */
749	xor r30, r30, r30
750
751	mtspr PPC_XER, r30
752	mtspr PPC_CTR, r30
753	mtspr DSISR, r30
754	mtspr PPC_DAR, r30
755	mtspr PPC_DEC, r30
756	mtspr SDR1, r30
757	mtspr SRR0, r30
758	mtspr SRR1, r30
759	mtspr CSSR0, r30
760	mtspr CSSR1, r30
761	mtspr SPRG0, r30
762	mtspr SPRG1, r30
763	mtspr SPRG2, r30
764	mtspr SPRG3, r30
765	mtspr SPRG4, r30
766	mtspr SPRG5, r30
767	mtspr SPRG6, r30
768	mtspr SPRG7, r30
769	mtspr PPC_EAR, r30
770	mtspr TBWU, r30
771	mtspr TBWL, r30
772	mtspr IBAT0U, r30
773	mtspr IBAT0L, r30
774	mtspr IBAT1U, r30
775	mtspr IBAT1L, r30
776	mtspr IBAT2U, r30
777	mtspr IBAT2L, r30
778	mtspr IBAT3U, r30
779	mtspr IBAT3L, r30
780	mtspr IBAT4U, r30
781	mtspr IBAT4L, r30
782	mtspr IBAT5U, r30
783	mtspr IBAT5L, r30
784	mtspr IBAT6U, r30
785	mtspr IBAT6L, r30
786	mtspr IBAT7U, r30
787	mtspr IBAT7L, r30
788	mtspr DBAT0U, r30
789	mtspr DBAT0L, r30
790	mtspr DBAT1U, r30
791	mtspr DBAT1L, r30
792	mtspr DBAT2U, r30
793	mtspr DBAT2L, r30
794	mtspr DBAT3U, r30
795	mtspr DBAT3L, r30
796	mtspr DBAT4U, r30
797	mtspr DBAT4L, r30
798	mtspr DBAT5U, r30
799	mtspr DBAT5L, r30
800	mtspr DBAT6U, r30
801	mtspr DBAT6L, r30
802	mtspr DBAT7U, r30
803	mtspr DBAT7L, r30
804	mtspr DMISS, r30
805	mtspr DCMP, r30
806	mtspr HASH1, r30
807	mtspr HASH2, r30
808	mtspr IMISS, r30
809	mtspr ICMP, r30
810	mtspr PPC_RPA, r30
811	mtsr PPC_SR0, r30
812	mtsr PPC_SR1, r30
813	mtsr PPC_SR2, r30
814	mtsr PPC_SR3, r30
815	mtsr PPC_SR4, r30
816	mtsr PPC_SR5, r30
817	mtsr PPC_SR6, r30
818	mtsr PPC_SR7, r30
819	mtsr PPC_SR8, r30
820	mtsr PPC_SR9, r30
821	mtsr PPC_SR10, r30
822	mtsr PPC_SR12, r30
823	mtsr PPC_SR13, r30
824	mtsr PPC_SR14, r30
825	mtsr PPC_SR15, r30
826
827
828
829
830
831	blr
832
833	PPC_HID0_rd: /* get HID0 content to r30 */
834
835
836	mfspr r30, HID0
837
838	blr
839
840
841	PPC_HID0_wr: /* put r30 content to HID0 */
842
843
844	mtspr HID0, r30
845
846	blr
847
848	clr_mem:
849	mr r28, r29
850	srwi r29, r29, 2
851	mtctr r29 /* set ctr reg */
852
853
854	slwi r29, r29, 2
855	sub r28, r28, r29 /* maybe some residual bytes */
856	xor r29, r29, r29
857
858
859	clr_mem_word:
860	stswi r29, r30, 0x04 /* store r29 (word) to r30 memory location */
861	addi r30, r30, 0x04 /* increment r30 */
862
863	bdnz clr_mem_word /* dec counter and loop */
864
865
866	cmpwi r28, 0x00 /* clear mem. finished ? */
867	beq clr_mem_end;
868	mtctr r28 /* reload counter for residual bytes */
869	clr_mem_byte:
870	stswi r29, r30, 0x01 /* store r29 (byte) to r30 memory location */
871	addi r30, r30, 0x01 /* update r30 */
872
873	bdnz clr_mem_byte /* dec counter and loop */
874
875	clr_mem_end:
876	blr /* return */
877
878	XLB_init:
879	/* init arbiter and stuff... */
880	LWI r30, 0x8000a06e
881	stw r30, ARBCFG(r31) /* Set ARBCFG */
882
883	LWI r30, 0x000000ff
884	stw r30, ARBMPREN(r31) /* Set ARBMPREN */
885
886	LWI r30, 0x00001234
887	stw r30, ARBMPRIO(r31) /* Set ARBPRIO */
888
889	LWI r30, 0x0000001e
890	stw r30, ARBSNOOP(r31) /* Set ARBSNOOP */
891
892	LWI r30, 4096
893	stw r30, ARBADRTO(r31) /* Set ARBADRTO */
894	stw r30, ARBDATTO(r31) /* Set ARBDATTO */
895
896	blr

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