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start.S @ 5e920ceb

4.115

Last change on this file since 5e920ceb was 5e920ceb, checked in by Sebastian Huber <sebastian.huber@…>, on 04/19/13 at 10:50:10
bsp/mpc5200: Do not initialize debug registers
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File size: 24.0 KB

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1	/===============================================================\
2	\| Project: RTEMS generic MPC5200 BSP \|
3	+-----------------------------------------------------------------+
4	\| Partially based on the code references which are named below. \|
5	\| Adaptions, modifications, enhancements and any recent parts of \|
6	\| the code are: \|
7	\| Copyright (c) 2005 \|
8	\| Embedded Brains GmbH \|
9	\| Obere Lagerstr. 30 \|
10	\| D-82178 Puchheim \|
11	\| Germany \|
12	\| rtems@embedded-brains.de \|
13	+-----------------------------------------------------------------+
14	\| The license and distribution terms for this file may be \|
15	\| found in the file LICENSE in this distribution or at \|
16	\| \|
17	\| http://www.rtems.com/license/LICENSE. \|
18	\| \|
19	+-----------------------------------------------------------------+
20	\| this file contains the startup assembly code \|
21	\===============================================================/
22	/***********************************************************************/
23	/* */
24	/* Module: start.S */
25	/* Date: 07/17/2003 */
26	/* Purpose: RTEMS MPC5x00 CPU assembly startup */
27	/* */
28	/---------------------------------------------------------------------/
29	/* */
30	/* Description: This file contains the assembler portion of MPC5x00 */
31	/* startup code */
32	/* */
33	/---------------------------------------------------------------------/
34	/* */
35	/* Code */
36	/* References: startup code for Motorola PQII ADS board */
37	/* Module: start.S */
38	/* Project: RTEMS 4.6.0pre1 / MCF8260ads BSP */
39	/* Version 1.2 */
40	/* Date: 04/18/2002 */
41	/* */
42	/* Author(s) / Copyright(s): */
43	/* */
44	/* Modified for the Motorola PQII ADS board by */
45	/* Andy Dachs <a.dachs@sstl.co.uk> 23-11-00. */
46	/* Surrey Satellite Technology Limited */
47	/* */
48	/* I have a proprietary bootloader programmed into the flash */
49	/* on the board which initialises the SDRAM prior to calling */
50	/* this function. */
51	/* */
52	/* This file is based on the one by Jay Monkman (jmonkman@fracsa.com)*/
53	/* which in turn was based on the dlentry.s file for the Papyrus BSP,*/
54	/* written by: */
55	/* */
56	/* Author: Andrew Bray <andy@i-cubed.co.uk> */
57	/* */
58	/* COPYRIGHT (c) 1995 by i-cubed ltd. */
59	/* */
60	/* To anyone who acknowledges that this file is provided "AS IS" */
61	/* without any express or implied warranty: */
62	/* permission to use, copy, modify, and distribute this file */
63	/* for any purpose is hereby granted without fee, provided that */
64	/* the above copyright notice and this notice appears in all */
65	/* copies, and that the name of i-cubed limited not be used in */
66	/* advertising or publicity pertaining to distribution of the */
67	/* software without specific, written prior permission. */
68	/* i-cubed limited makes no representations about the suitability */
69	/* of this software for any purpose. */
70	/* */
71	/---------------------------------------------------------------------/
72	/* */
73	/* Partially based on the code references which are named above. */
74	/* Adaptions, modifications, enhancements and any recent parts of */
75	/* the code are under the right of */
76	/* */
77	/* IPR Engineering, Dachauer StraÃe 38, D-80335 MÃŒnchen */
78	/* Copyright(C) 2003 */
79	/* */
80	/---------------------------------------------------------------------/
81	/* */
82	/* IPR Engineering makes no representation or warranties with */
83	/* respect to the performance of this computer program, and */
84	/* specifically disclaims any responsibility for any damages, */
85	/* special or consequential, connected with the use of this program. */
86	/* */
87	/---------------------------------------------------------------------/
88	/* */
89	/* Version history: 1.0 */
90	/* */
91	/***********************************************************************/
92
93	#include <rtems/powerpc/cache.h>
94
95	#include <bsp.h>
96	#include <bsp/mpc5200.h>
97
98	/* Some register offsets of MPC5x00 memory map registers */
99	.set CS0STR, 0x04
100	.set CS0STP, 0x08
101	.set CS1STR, 0x0C
102	.set CS1STP, 0x10
103	.set SDRAMCS0, 0x34
104	.set SDRAMCS1, 0x38
105	.set BOOTSTR, 0x4C
106	.set BOOTSTP, 0x50
107	.set ADREN, 0x54
108	.set CSSR0, 0x58 /* Critical Interrupt SSR0 (603le only) */
109	.set CSSR1, 0x59 /* Critical Interrupt SSR1 (603le only) */
110	.set CFG, 0x20C
111	.set CSBOOTROM, 0x300
112	.set CSCONTROL, 0x318
113	.set CS1CONF, 0x304
114
115
116	/* Register offsets of MPC5x00 SDRAM memory controller registers */
117	.set MOD, 0x100
118	.set CTRL, 0x104
119	.set CFG1, 0x108
120	.set CFG2, 0x10C
121	.set ADRSEL, 0x110
122
123	/* Register offsets of MPC5x00 GPIO registers needed */
124	.set GPIOPCR, 0xb00
125	.set GPIOWE, 0xc00
126	.set GPIOWOD, 0xc04
127	.set GPIOWDD, 0xc08
128	.set GPIOWDO, 0xc0c
129
130	.set GPIOSEN, 0xb04
131	.set GPIOSDD, 0xb0c
132	.set GPIOSDO, 0xb10
133
134	/* Register offsets of MPC5x00 Arbiter registers */
135	.set ARBCFG, 0x1f40
136	.set ARBMPREN, 0x1f64
137	.set ARBMPRIO, 0x1f68
138	.set ARBSNOOP, 0x1f70
139
140	/* Some bit encodings for MGT5100 registers */
141	.set ADREN_SDRAM_EN, (1<<22)
142	.set ADREN_BOOT_EN, (1<<25)
143	.set ADREN_CS0_EN, (1<<16)
144	.set ADREN_CS1_EN, (1<<17)
145
146	.set CTRL_PRECHARGE, (1<<1)
147	.set CTRL_REFRESH, (1<<2)
148	.set CTRL_BA1, (1<<31)
149
150	.set CSCONF_CE, (1<<12)
151
152	/* Some fixed values for MPC5x00 registers */
153	.set CSBOOTROM_VAL, 0x0101D910
154	.set CSCONTROL_VAL, 0x91000000
155	.set CFG_VAL, 0x00000100
156
157	.extern boot_card
158
159	.section ".vectors", "ax"
160	bl start
161	.rep 63
162	.long 0x04000400
163	.endr
164	__vec2: b __vec2
165	.rep 63
166	.long 0x04000400
167	.endr
168	__vec3: b __vec3
169	.rep 63
170	.long 0x04000400
171	.endr
172	__vec4: b __vec4
173	.rep 63
174	.long 0x04000400
175	.endr
176	__vec5: b __vec5
177	.rep 63
178	.long 0x04000400
179	.endr
180	__vec6: b __vec6
181	.rep 63
182	.long 0x04000400
183	.endr
184	__vec7: b __vec7
185	.rep 63
186	.long 0x04000400
187	.endr
188	__vec8: b __vec8
189	.rep 63
190	.long 0x04000400
191	.endr
192	__vec9: b __vec9
193	.rep 63
194	.long 0x04000400
195	.endr
196	__veca: b __veca
197	.rep 63
198	.long 0x04000400
199	.endr
200	__vecb: b __vecb
201	.rep 63
202	.long 0x04000400
203	.endr
204	__vecc: b __vecc
205	.rep 63
206	.long 0x04000400
207	.endr
208	__vecd: b __vecd
209	.rep 63
210	.long 0x04000400
211	.endr
212	__vece: b __vece
213	.rep 63
214	.long 0x04000400
215	.endr
216	__vecf: b __vecf
217	.rep 63+1024
218	.long 0x04000400
219	.endr
220
221	.section ".entry"
222	PUBLIC_VAR (start)
223	start:
224	/* 1st: initialization work (common for RAM/ROM startup) */
225	mfmsr r30
226	SETBITS r30, r29, MSR_ME\|MSR_RI
227	CLRBITS r30, r29, MSR_EE
228	mtmsr r30 /* Set RI/ME, Clr EE in MSR */
229
230	#ifdef HAS_UBOOT
231	mr r14, r3
232	#endif /* HAS_UBOOT */
233
234	#if defined(NEED_LOW_LEVEL_INIT)
235	/* initialize the MBAR (common RAM/ROM startup) */
236	LWI r31, MBAR_RESET
237	LWI r29, MBAR
238	rlwinm r30, r29,16,16,31
239	stw r30, 0(r31) /* Set the MBAR */
240	#endif
241
242	LWI r31, MBAR /* set r31 to current MBAR */
243	/* init GPIOPCR */
244	lwz r29,GPIOPCR(r31)
245	LWI r30, BSP_GPIOPCR_INITMASK
246	not r30,r30
247	and r29,r29,r30
248	LWI r30, BSP_GPIOPCR_INITVAL
249	or r29,r29,r30
250	stw r29, GPIOPCR(r31)
251
252	/* further initialization work (common RAM/ROM startup) */
253	bl TLB_init /* Initialize TLBs */
254
255
256	bl FID_DCache /* Flush, inhibit and disable data cache */
257
258
259	bl IDUL_ICache /* Inhibit, disable and unlock instruction cache */
260
261
262	bl FPU_init /* Initialize FPU */
263
264
265	#if defined(NEED_LOW_LEVEL_INIT)
266	bl SPRG_init /* Initialize special purpose registers */
267	#endif
268
269	#if defined(NEED_LOW_LEVEL_INIT)
270	/* detect RAM/ROM startup (common for RAM/ROM startup) */
271	LWI r20, bsp_rom_start /* set the relocation offset */
272
273
274	LWI r30, CFG_VAL /* get CFG register content */
275	lwz r30, CFG(r31) /* set SDRAM single data rate / XLB_CLK=FVCO/4 / IPB_CLK=XLB_CLK/2 / PCICLK=IPB_CLK */
276
277
278
279	lwz r30, ADREN(r31) /* get content of ADREN */
280
281
282
283	TSTBITS r30, r29, ADREN_BOOT_EN
284	bne skip_ROM_start /* If BOOT_ROM is not enabled, skip further initialization */
285
286	/* do some board dependent configuration (unique for ROM startup) */
287	LWI r30, CSCONTROL_VAL /* get CSCONTROL register content */
288	stw r30, CSCONTROL(r31) /* enable internal/external bus error and master for CS */
289
290
291
292	#ifdef MPC5200_BOARD_BRS5L
293	LWI r30, CSBOOTROM_VAL
294	stw r30, CSBOOTROM(r31) /* Set CSBOOTROM */
295
296
297	#endif /* MPC5200_BOARD_BRS5L */
298
299
300	/* FIXME: map BOOT ROM into final location with CS0 registers */
301	LWI r30, bsp_rom_start
302	rlwinm r30, r30,17,15,31
303	stw r30, CS0STR(r31) /* Set CS0STR */
304
305	LWI r30, bsp_rom_end - 1
306
307	rlwinm r30, r30,17,15,31
308	stw r30, CS0STP(r31) /* Set CS0STP */
309
310	lwz r30, ADREN(r31) /* get content of ADREN */
311	SETBITS r30, r29, ADREN_CS0_EN
312	stw r30, ADREN(r31) /* enable CS0 mapping */
313	isync
314	/* jump to same code in final BOOT ROM location */
315	LWI r30, reloc_in_CS0
316	LWI r29, bsp_ram_start
317	sub r30,r30,r29
318	LWI r29, bsp_rom_start
319	add r30,r30,r29
320	mtctr r30
321	bctr
322
323	reloc_in_CS0:
324	/* disable CSBOOT (or map it to CS0 range) */
325	lwz r30, ADREN(r31) /* get content of ADREN */
326	CLRBITS r30, r29, ADREN_BOOT_EN
327	stw r30, ADREN(r31) /* disable BOOT mapping */
328
329	/* init SDRAM */
330	LWI r30, bsp_ram_start
331	ori r30, r30, 0x1a /* size code: bank is 128MByte */
332	stw r30, SDRAMCS0(r31) /* Set SDRAMCS0 */
333
334	LWI r30, bsp_ram_size
335	srawi r30, r30, 1
336	ori r30, r30, 0x1a /* size code: bank is 128MByte */
337	stw r30, SDRAMCS1(r31) /* Set SDRAMCS1 */
338
339	bl SDRAM_init /* Initialize SDRAM controller */
340
341	bl XLB_init
342	/* copy .text section from ROM to RAM location (unique for ROM startup) */
343	LA r30, bsp_section_text_start /* get start address of text section in RAM */
344
345
346	add r30, r20, r30 /* get start address of text section in ROM (add reloc offset) */
347
348
349	LA r29, bsp_section_text_start /* get start address of text section in RAM */
350
351
352	LA r28, bsp_section_text_size /* get size of RAM image */
353
354
355	bl copy_image /* copy text section from ROM to RAM location */
356
357
358	/* copy .data section from ROM to RAM location (unique for ROM startup) */
359	LA r30, bsp_section_data_start /* get start address of data section in RAM */
360
361
362	add r30, r20, r30 /* get start address of data section in ROM (add reloc offset) */
363
364
365	LA r29, bsp_section_data_start /* get start address of data section in RAM */
366
367
368	LA r28, bsp_section_data_size /* get size of RAM image */
369
370
371	bl copy_image /* copy initialized data section from ROM to RAM location */
372
373
374	LA r29, remap_rom /* get compile time address of label */
375	mtlr r29
376
377	blrl /* now further execution RAM */
378
379	remap_rom:
380	/* remap BOOT ROM to CS0 (common for RAM/ROM startup) */
381	lwz r30, CSBOOTROM(r31) /* get content of CSBOOTROM */
382
383
384
385	CLRBITS r30, r29, CSCONF_CE
386	stw r30, CSBOOTROM(r31) /* disable BOOT CS */
387
388
389
390	lwz r30, ADREN(r31) /* get content of ADREN */
391
392
393
394	mr r29, r30 /* move content of r30 to r29 */
395
396
397	LWI r30, ADREN_BOOT_EN /* mask ADREN_BOOT_EN */
398	andc r29,r29,r30
399
400
401	LWI r30, ADREN_CS0_EN /* unmask ADREN_CS0_EN */
402	or r29,r29,r30
403
404
405	stw r29,ADREN(r31) /* Simultaneous enable CS0 and disable BOOT address space */
406
407
408
409	lwz r30, CSBOOTROM(r31) /* get content of CSBOOTROM */
410
411
412
413	SETBITS r30, r29, CSCONF_CE
414	stw r30, CSBOOTROM(r31) /* disable BOOT CS */
415
416
417
418	skip_ROM_start:
419	/* configure external DPRAM CS1 */
420	LWI r30, 0xFFFFFB10
421	stw r30, CS1CONF(r31)
422
423	/* map external DPRAM (CS1) */
424	LWI r30, bsp_dpram_start
425	srawi r30, r30, 16
426	stw r30, CS1STR(r31)
427
428	LWI r30, bsp_dpram_end
429	srawi r30, r30, 16
430	stw r30, CS1STP(r31)
431
432	lwz r30, ADREN(r31) /* get content of ADREN */
433
434	LWI r29, ADREN_CS1_EN /* unmask ADREN_CS1_EN */
435	or r30, r30,r29
436
437	stw r30, ADREN(r31) /* enable CS1 */
438
439	/* clear entire on chip SRAM (unique for ROM startup) */
440	lis r30, (MBAR+ONCHIP_SRAM_OFFSET)@h /* get start address of onchip SRAM */
441	ori r30, r30,(MBAR+ONCHIP_SRAM_OFFSET)@l
442	LWI r29, ONCHIP_SRAM_SIZE /* get size of onchip SRAM */
443
444	bl clr_mem /* Clear onchip SRAM */
445
446	#else /* defined(NEED_LOW_LEVEL_INIT) */
447	bl XLB_init
448	#endif /* defined(NEED_LOW_LEVEL_INIT) */
449	/* clear .bss section (unique for ROM startup) */
450	LWI r30, bsp_section_bss_start /* get start address of bss section */
451	LWI r29, bsp_section_bss_size /* get size of bss section */
452
453
454	bl clr_mem /* Clear the bss section */
455
456	#ifdef HAS_UBOOT
457	mr r3, r14
458	bl bsp_uboot_copy_board_info
459	#endif /* HAS_UBOOT */
460
461	/* set stack pointer (common for RAM/ROM startup) */
462	LA r1, bsp_section_text_start
463	addi r1, r1, -0x10 /* Set up stack pointer = beginning of text section - 0x10 */
464	/* tag TOS with a NULL pointer (termination mark for stack dump) */
465	li r0, 0
466	stw r0, 0(r1)
467
468	bl __eabi /* Set up EABI and SYSV environment */
469
470	/* enable dynamic power management(common for RAM/ROM startup) */
471	bl PPC_HID0_rd /* Get the content of HID0 */
472
473	SETBITS r30, r29, HID0_DPM
474	bl PPC_HID0_wr /* Set DPM in HID0 */
475
476	/* clear arguments and do further init. in C (common for RAM/ROM startup) */
477
478	/* Clear cmdline */
479	xor r3, r3, r3
480
481	bl SYM (boot_card) /* Call the first C routine */
482
483	twiddle:
484	b twiddle /* We don't expect to return from boot_card but if we do */
485	/* wait here for watchdog to kick us into hard reset */
486
487	#if defined(NEED_LOW_LEVEL_INIT)
488	SDRAM_init:
489	#if defined(MPC5200_BOARD_BRS5L)
490	/* set GPIO_WKUP7 pin low for 66MHz buffering */
491	/* or high for 133MHz registered buffering */
492	LWI r30, 0x80000000
493
494	lwz r29, GPIOWE(r31)
495	or r29,r29,r30 /* set bit 0 in r29/GPIOWE */
496	stw r29,GPIOWE(r31)
497
498	lwz r29, GPIOWOD(r31)
499	andc r29,r29,r30 /* clear bit 0 in r29/GPIOWOD */
500	stw r29,GPIOWOD(r31)
501
502	lwz r29, GPIOWDO(r31)
503	andc r29,r29,r30 /* clear bit 0 in r29/GPIOWDO */
504	stw r29,GPIOWDO(r31)
505
506	lwz r29, GPIOWDD(r31)
507	or r29,r29,r30 /* set bit 0 in r29/GPIOWDD */
508	stw r29,GPIOWDD(r31)
509
510	/* activate MEM_CS1 output */
511	lwz r29, GPIOPCR(r31)
512	or r29,r29,r30 /* set bit 0 in r29/GPIOPCR */
513	stw r29,GPIOPCR(r31)
514
515	#endif
516	/* See Erratum 342/339 in MPC5200_Errata_L25R_3_June.pdf: */
517	/* set 5 delays to their maximum to support two banks */
518	#if 0
519	LWI r30, 0xCC222600 /* Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x2 */
520	#else
521	/* EB 04.12.08:
522	* on MPC5200B, Erratum342 is no longer applicable.
523	* on MPC5200_, Single Write2Read/Prec is only 3 bits,
524	* therefore the MSB of the set value (1100) was ignored
525	* in the MPC5200B, this bit is implemented in results in
526	* SSSLLLOOOWWW access to SDRAM. To make the mem ctrl settings compatible with the MPC5200_,
527	* we use a 4 for now.
528	*/
529	LWI r30, 0xC4222600 /* Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x4 */
530	#endif
531	stw r30, CFG1(r31) /* Read CAS latency=0x2, Active2Read delay=0x2, Prec.2active delay=0x2 */
532	/* Refr.2No-Read delay=0x06, Write latency=0x0 */
533
534	LWI r30, 0xCCC70004 /* Burst2Read Prec.delay=0x8, Burst Write delay=0x8 */
535	stw r30, CFG2(r31) /* Burst Read2Write delay=0xB, Burst length=0x7, Read Tap=0x4 */
536
537	#ifdef MPC5200_BOARD_BRS5L
538	LWI r30, 0xD1470000 /* Mode Set enabled, Clock enabled, Auto refresh enabled, Mem. data drv */
539	stw r30, CTRL(r31) /* Refresh counter=0xFFFF */
540
541
542	#else
543	LWI r30, 0xD04F0000 /* Mode Set enabled, Clock enabled, Auto refresh enabled, Mem. data drv */
544	stw r30, CTRL(r31) /* Refresh counter=0xFFFF */
545
546
547	#endif
548	lwz r30, CTRL(r31)
549
550
551	SETBITS r30, r29, CTRL_PRECHARGE /* send two times precharge */
552	stw r30, CTRL(r31)
553
554
555	stw r30, CTRL(r31)
556
557
558
559	lwz r30, CTRL(r31)
560
561
562	SETBITS r30, r29, CTRL_REFRESH /* send two times refresh */
563	stw r30, CTRL(r31)
564
565
566	stw r30, CTRL(r31)
567
568
569
570	LWI r30, 0x008D0000 /* Op.Mode=0x0, Read CAS latency=0x2, Burst length=0x3, Write strobe puls */
571	stw r30, MOD(r31)
572
573
574
575	lwz r30, CTRL(r31) /* Clock enabled, Auto refresh enabled, Mem. data drv. Refresh counter=0xFFFF */
576
577
578	CLRBITS r30, r29, CTRL_BA1
579	stw r30, CTRL(r31)
580
581
582
583	blr
584
585
586	copy_image:
587	mr r27, r28
588	srwi r28, r28, 2
589	mtctr r28
590
591
592	slwi r28, r28, 2
593	sub r27, r27, r28 /* maybe some residual bytes */
594
595
596	copy_image_word:
597	lswi r28, r30, 0x04
598
599	stswi r28, r29, 0x04 /* do word copy ROM -> RAM */
600
601
602	addi r30, r30, 0x04 /* increment source pointer */
603	addi r29, r29, 0x04 /* increment destination pointer */
604
605	bdnz copy_image_word /* decrement ctr and branch if not 0 */
606
607	cmpwi r27, 0x00 /* copy image finished ? */
608	beq copy_image_end;
609	mtctr r27 /* reload counter for residual bytes */
610	copy_image_byte:
611	lswi r28, r30, 0x01
612
613	stswi r28, r29, 0x01 /* do byte copy ROM -> RAM */
614
615
616	addi r30, r30, 0x01 /* increment source pointer */
617	addi r29, r29, 0x01 /* increment destination pointer */
618
619	bdnz copy_image_byte /* decrement ctr and branch if not 0 */
620
621	copy_image_end:
622	blr
623	#endif /* defined(NEED_LOW_LEVEL_INIT) */
624
625	FID_DCache:
626	mflr r26
627
628	bl PPC_HID0_rd
629	TSTBITS r30, r29, HID0_DCE
630	bne FID_DCache_exit /* If data cache is switched of, skip further actions */
631
632	li r29, PPC_D_CACHE /* 16 Kb data cache on 603e */
633	LWI r28, bsp_section_text_start /* Load base address (begin of RAM) */
634
635	FID_DCache_loop_1:
636	lwz r27, 0(r28) /* Load data at address */
637
638	addi r28, r28, PPC_CACHE_ALIGNMENT /* increment cache line address */
639	subi r29, r29, PPC_CACHE_ALIGNMENT /* increment loop counter */
640	cmpwi r29, 0x0
641	bne FID_DCache_loop_1 /* Loop until cache size is reached */
642
643	li r29, PPC_D_CACHE /* 16 Kb data cache on 603e */
644	LWI r28, bsp_section_text_start /* Reload base address (begin of RAM) */
645	xor r27, r27, r27
646	FID_DCache_loop_2:
647
648	dcbf r27, r28 /* Flush and invalidate cache */
649
650	addi r28, r28, PPC_CACHE_ALIGNMENT /* increment cache line address */
651	subi r29, r29, PPC_CACHE_ALIGNMENT /* increment loop counter */
652	cmpwi r29, 0x0
653	bne FID_DCache_loop_2 /* Loop around until cache size is reached */
654
655	bl PPC_HID0_rd /* Read HID0 */
656	CLRBITS r30, r29, HID0_DCE
657	bl PPC_HID0_wr /* Clear DCE */
658
659	FID_DCache_exit:
660	mtlr r26
661	blr
662
663	IDUL_ICache:
664	mflr r26
665
666	bl PPC_HID0_rd
667	TSTBITS r30, r29, HID0_ICE
668	bne IDUL_ICache_exit /* If instruction cache is switched of, skip further actions */
669
670	CLRBITS r30, r29, HID0_ICE
671	bl PPC_HID0_wr /* Disable ICE bit */
672
673	SETBITS r30, r29, HID0_ICFI
674	bl PPC_HID0_wr /* Invalidate instruction cache */
675
676	CLRBITS r30, r29, HID0_ICFI
677	bl PPC_HID0_wr /* Disable cache invalidate */
678
679	CLRBITS r30, r29, HID0_ILOCK
680	bl PPC_HID0_wr /* Disable instruction cache lock */
681
682	IDUL_ICache_exit:
683	mtlr r26
684	blr
685
686
687	TLB_init: /* Initialize translation lookaside buffers (TLBs) */
688	xor r30, r30, r30
689	xor r29, r29, r29
690
691	TLB_init_loop:
692	tlbie r29
693	tlbsync
694	addi r29, r29, 0x1000
695	addi r30, r30, 0x01
696	cmpli 0, 0, r30, 0x0080
697	bne TLB_init_loop
698	blr
699
700	FPU_init:
701	mfmsr r30 /* get content of MSR */
702
703
704	SETBITS r30, r29, MSR_FP
705	mtmsr r30 /* enable FPU and FPU exceptions */
706	sync
707
708	lfd f0, 0(r29)
709	fmr f1, f0
710	fmr f2, f0
711	fmr f3, f0
712	fmr f4, f0
713	fmr f5, f0
714	fmr f6, f0
715	fmr f7, f0
716	fmr f8, f0
717	fmr f9, f0
718	fmr f10, f0
719	fmr f11, f0
720	fmr f12, f0
721	fmr f13, f0
722	fmr f14, f0
723	fmr f15, f0
724	fmr f16, f0
725	fmr f17, f0
726	fmr f18, f0
727	fmr f19, f0
728	fmr f20, f0
729	fmr f21, f0
730	fmr f22, f0
731	fmr f23, f0
732	fmr f24, f0
733	fmr f25, f0
734	fmr f26, f0
735	fmr f27, f0
736	fmr f28, f0
737	fmr f29, f0
738	fmr f30, f0
739	fmr f31, f0
740
741
742	mtfsfi 0, 0 /* initialize bit positons in FPSCR */
743	mtfsfi 1, 0
744	mtfsfi 2, 0
745	mtfsfi 3, 0
746	mtfsfi 4, 0
747	mtfsfi 5, 0
748	mtfsfi 6, 0
749	mtfsfi 7, 0
750
751	blr
752
753	SPRG_init: /* initialize registers */
754	xor r30, r30, r30
755
756	mtspr PPC_XER, r30
757	mtspr PPC_CTR, r30
758	mtspr DSISR, r30
759	mtspr PPC_DAR, r30
760	mtspr PPC_DEC, r30
761	mtspr SDR1, r30
762	mtspr SRR0, r30
763	mtspr SRR1, r30
764	mtspr CSSR0, r30
765	mtspr CSSR1, r30
766	mtspr SPRG0, r30
767	mtspr SPRG1, r30
768	mtspr SPRG2, r30
769	mtspr SPRG3, r30
770	mtspr SPRG4, r30
771	mtspr SPRG5, r30
772	mtspr SPRG6, r30
773	mtspr SPRG7, r30
774	mtspr PPC_EAR, r30
775	mtspr TBWU, r30
776	mtspr TBWL, r30
777	mtspr IBAT0U, r30
778	mtspr IBAT0L, r30
779	mtspr IBAT1U, r30
780	mtspr IBAT1L, r30
781	mtspr IBAT2U, r30
782	mtspr IBAT2L, r30
783	mtspr IBAT3U, r30
784	mtspr IBAT3L, r30
785	mtspr IBAT4U, r30
786	mtspr IBAT4L, r30
787	mtspr IBAT5U, r30
788	mtspr IBAT5L, r30
789	mtspr IBAT6U, r30
790	mtspr IBAT6L, r30
791	mtspr IBAT7U, r30
792	mtspr IBAT7L, r30
793	mtspr DBAT0U, r30
794	mtspr DBAT0L, r30
795	mtspr DBAT1U, r30
796	mtspr DBAT1L, r30
797	mtspr DBAT2U, r30
798	mtspr DBAT2L, r30
799	mtspr DBAT3U, r30
800	mtspr DBAT3L, r30
801	mtspr DBAT4U, r30
802	mtspr DBAT4L, r30
803	mtspr DBAT5U, r30
804	mtspr DBAT5L, r30
805	mtspr DBAT6U, r30
806	mtspr DBAT6L, r30
807	mtspr DBAT7U, r30
808	mtspr DBAT7L, r30
809	mtspr DMISS, r30
810	mtspr DCMP, r30
811	mtspr HASH1, r30
812	mtspr HASH2, r30
813	mtspr IMISS, r30
814	mtspr ICMP, r30
815	mtspr PPC_RPA, r30
816	mtsr PPC_SR0, r30
817	mtsr PPC_SR1, r30
818	mtsr PPC_SR2, r30
819	mtsr PPC_SR3, r30
820	mtsr PPC_SR4, r30
821	mtsr PPC_SR5, r30
822	mtsr PPC_SR6, r30
823	mtsr PPC_SR7, r30
824	mtsr PPC_SR8, r30
825	mtsr PPC_SR9, r30
826	mtsr PPC_SR10, r30
827	mtsr PPC_SR12, r30
828	mtsr PPC_SR13, r30
829	mtsr PPC_SR14, r30
830	mtsr PPC_SR15, r30
831
832
833
834
835
836	blr
837
838	PPC_HID0_rd: /* get HID0 content to r30 */
839
840
841	mfspr r30, HID0
842
843	blr
844
845
846	PPC_HID0_wr: /* put r30 content to HID0 */
847
848
849	mtspr HID0, r30
850
851	blr
852
853	clr_mem:
854	mr r28, r29
855	srwi r29, r29, 2
856	mtctr r29 /* set ctr reg */
857
858
859	slwi r29, r29, 2
860	sub r28, r28, r29 /* maybe some residual bytes */
861	xor r29, r29, r29
862
863
864	clr_mem_word:
865	stswi r29, r30, 0x04 /* store r29 (word) to r30 memory location */
866	addi r30, r30, 0x04 /* increment r30 */
867
868	bdnz clr_mem_word /* dec counter and loop */
869
870
871	cmpwi r28, 0x00 /* clear mem. finished ? */
872	beq clr_mem_end;
873	mtctr r28 /* reload counter for residual bytes */
874	clr_mem_byte:
875	stswi r29, r30, 0x01 /* store r29 (byte) to r30 memory location */
876	addi r30, r30, 0x01 /* update r30 */
877
878	bdnz clr_mem_byte /* dec counter and loop */
879
880	clr_mem_end:
881	blr /* return */
882
883	XLB_init:
884	/* init arbiter and stuff... */
885	LWI r30, 0x8000a06e
886	stw r30, ARBCFG(r31) /* Set ARBCFG */
887
888	LWI r30, 0x000000ff
889	stw r30, ARBMPREN(r31) /* Set ARBMPREN */
890
891	LWI r30, 0x00001234
892	stw r30, ARBMPRIO(r31) /* Set ARBPRIO */
893
894	LWI r30, 0x0000001e
895	stw r30, ARBSNOOP(r31) /* Set ARBSNOOP */
896
897	blr

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