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start.S @ 3d58766

4.104.114.95

Last change on this file since 3d58766 was aa058378, checked in by Joel Sherrill <joel.sherrill@…>, on 08/05/08 at 13:33:02

2008-08-01 Sebastian Huber <sebastian.huber@…>

start/start.S: Clear environment pointer for bootcard.

Property mode set to 100644

File size: 24.9 KB

Line
1	/===============================================================\
2	\| Project: RTEMS generic MPC5200 BSP \|
3	+-----------------------------------------------------------------+
4	\| Partially based on the code references which are named below. \|
5	\| Adaptions, modifications, enhancements and any recent parts of \|
6	\| the code are: \|
7	\| Copyright (c) 2005 \|
8	\| Embedded Brains GmbH \|
9	\| Obere Lagerstr. 30 \|
10	\| D-82178 Puchheim \|
11	\| Germany \|
12	\| rtems@embedded-brains.de \|
13	+-----------------------------------------------------------------+
14	\| The license and distribution terms for this file may be \|
15	\| found in the file LICENSE in this distribution or at \|
16	\| \|
17	\| http://www.rtems.com/license/LICENSE. \|
18	\| \|
19	+-----------------------------------------------------------------+
20	\| this file contains the startup assembly code \|
21	\===============================================================/
22	/***********************************************************************/
23	/* */
24	/* Module: start.S */
25	/* Date: 07/17/2003 */
26	/* Purpose: RTEMS MPC5x00 CPU assembly startup */
27	/* */
28	/---------------------------------------------------------------------/
29	/* */
30	/* Description: This file contains the assembler portion of MPC5x00 */
31	/* startup code */
32	/* */
33	/---------------------------------------------------------------------/
34	/* */
35	/* Code */
36	/* References: startup code for Motorola PQII ADS board */
37	/* Module: start.S */
38	/* Project: RTEMS 4.6.0pre1 / MCF8260ads BSP */
39	/* Version 1.2 */
40	/* Date: 04/18/2002 */
41	/* */
42	/* Author(s) / Copyright(s): */
43	/* */
44	/* Modified for the Motorola PQII ADS board by */
45	/* Andy Dachs <a.dachs@sstl.co.uk> 23-11-00. */
46	/* Surrey Satellite Technology Limited */
47	/* */
48	/* I have a proprietary bootloader programmed into the flash */
49	/* on the board which initialises the SDRAM prior to calling */
50	/* this function. */
51	/* */
52	/* This file is based on the one by Jay Monkman (jmonkman@fracsa.com)*/
53	/* which in turn was based on the dlentry.s file for the Papyrus BSP,*/
54	/* written by: */
55	/* */
56	/* Author: Andrew Bray <andy@i-cubed.co.uk> */
57	/* */
58	/* COPYRIGHT (c) 1995 by i-cubed ltd. */
59	/* */
60	/* To anyone who acknowledges that this file is provided "AS IS" */
61	/* without any express or implied warranty: */
62	/* permission to use, copy, modify, and distribute this file */
63	/* for any purpose is hereby granted without fee, provided that */
64	/* the above copyright notice and this notice appears in all */
65	/* copies, and that the name of i-cubed limited not be used in */
66	/* advertising or publicity pertaining to distribution of the */
67	/* software without specific, written prior permission. */
68	/* i-cubed limited makes no representations about the suitability */
69	/* of this software for any purpose. */
70	/* */
71	/---------------------------------------------------------------------/
72	/* */
73	/* Partially based on the code references which are named above. */
74	/* Adaptions, modifications, enhancements and any recent parts of */
75	/* the code are under the right of */
76	/* */
77	/* IPR Engineering, Dachauer StraÃe 38, D-80335 MÃŒnchen */
78	/* Copyright(C) 2003 */
79	/* */
80	/---------------------------------------------------------------------/
81	/* */
82	/* IPR Engineering makes no representation or warranties with */
83	/* respect to the performance of this computer program, and */
84	/* specifically disclaims any responsibility for any damages, */
85	/* special or consequential, connected with the use of this program. */
86	/* */
87	/---------------------------------------------------------------------/
88	/* */
89	/* Version history: 1.0 */
90	/* */
91	/***********************************************************************/
92
93	#include <rtems/asm.h>
94	#include <rtems/powerpc/cache.h>
95	#include <rtems/powerpc/registers.h>
96	#include "../include/mpc5200.h"
97	#include "../include/bsp.h"
98
99	/* Macro definitions to load a register with a 32-bit address.
100	Both functions identically. Sometimes one mnemonic is more
101	appropriate than the other.
102	reg -> register to load
103	value -> value to be loaded
104	LA reg,value ("Load Address")
105	LWI reg,value ("Load Word Immediate") */
106
107	.macro LA reg, value
108	lis \reg , \value@h
109	ori \reg , \reg, \value@l
110	sync
111	.endm
112
113	.macro LWI reg, value
114	lis \reg , (\value)@h
115	ori \reg , \reg, (\value)@l
116	sync
117	.endm
118
119	/* Macro definitions to test, set or clear a single
120	bit or bit pattern in a given 32bit GPR.
121	reg1 -> register content to be tested
122	reg2 -> 2nd register only needed for computation
123	mask -> any bit pattern */
124
125	.macro TSTBITS reg1, reg2, mask /* Match is indicated by EQ=0 (CR) */
126	LWI \reg2, \mask /* Unmatch is indicated by EQ=1 (CR) */
127	and \reg1, \reg1, \reg2
128	cmplw \reg1, \reg2
129	sync
130	.endm
131
132	.macro SETBITS reg1, reg2, mask
133	LWI \reg2, \mask
134	or \reg1, \reg1, \reg2
135	sync
136	.endm
137
138	.macro CLRBITS reg1, reg2, mask
139	LWI \reg2, \mask
140	andc \reg1, \reg1, \reg2
141	sync
142	.endm
143
144	/* Some register offsets of MPC5x00 memory map registers */
145	.set CS0STR, 0x04
146	.set CS0STP, 0x08
147	.set CS1STR, 0x0C
148	.set CS1STP, 0x10
149	.set SDRAMCS0, 0x34
150	.set SDRAMCS1, 0x38
151	.set BOOTSTR, 0x4C
152	.set BOOTSTP, 0x50
153	.set ADREN, 0x54
154	.set CSSR0, 0x58 /* Critical Interrupt SSR0 (603le only) */
155	.set CSSR1, 0x59 /* Critical Interrupt SSR1 (603le only) */
156	.set CFG, 0x20C
157	.set CSBOOTROM, 0x300
158	.set CSCONTROL, 0x318
159	.set CS1CONF, 0x304
160
161
162	/* Register offsets of MPC5x00 SDRAM memory controller registers */
163	.set MOD, 0x100
164	.set CTRL, 0x104
165	.set CFG1, 0x108
166	.set CFG2, 0x10C
167	.set ADRSEL, 0x110
168
169	/* Register offsets of MPC5x00 GPIO registers needed */
170	.set GPIOPCR, 0xb00
171	.set GPIOWE, 0xc00
172	.set GPIOWOD, 0xc04
173	.set GPIOWDD, 0xc08
174	.set GPIOWDO, 0xc0c
175
176	.set GPIOSEN, 0xb04
177	.set GPIOSDD, 0xb0c
178	.set GPIOSDO, 0xb10
179
180	/* Register offsets of MPC5x00 Arbiter registers */
181	.set ARBCFG, 0x1f40
182	.set ARBMPREN, 0x1f64
183	.set ARBMPRIO, 0x1f68
184	.set ARBSNOOP, 0x1f70
185
186	/* Some bit encodings for MGT5100 registers */
187	.set ADREN_SDRAM_EN, (1<<22)
188	.set ADREN_BOOT_EN, (1<<25)
189	.set ADREN_CS0_EN, (1<<16)
190	.set ADREN_CS1_EN, (1<<17)
191
192	.set CTRL_PRECHARGE, (1<<1)
193	.set CTRL_REFRESH, (1<<2)
194	.set CTRL_BA1, (1<<31)
195
196	.set CSCONF_CE, (1<<12)
197
198	/* Some fixed values for MPC5x00 registers */
199	.set CSBOOTROM_VAL, 0x0101D910
200	.set CSCONTROL_VAL, 0x91000000
201	.set CFG_VAL, 0x00000100
202
203	.extern _bss_start
204	.extern _bss_size
205	.extern _data_start
206	.extern _data_size
207	.extern _text_start
208	.extern _text_size
209	/.extern _s_got/
210	.extern boot_card
211	.extern MBAR
212
213	.section ".entry"
214	PUBLIC_VAR (start)
215	start:
216	/* 1st: initialization work (common for RAM/ROM startup) */
217	mfmsr r30
218	SETBITS r30, r29, MSR_ME\|MSR_RI
219	CLRBITS r30, r29, MSR_EE
220	mtmsr r30 /* Set RI/ME, Clr EE in MSR */
221
222	#if defined(HAS_UBOOT)
223	/* store pointer to UBoot bd_info board info structure */
224	LWI r31,uboot_bdinfo_ptr
225	stw r3,0(r31)
226	#endif /* defined(HAS_UBOOT) */
227
228	#if defined(NEED_LOW_LEVEL_INIT)
229	/* initialize the MBAR (common RAM/ROM startup) */
230	LWI r31, MBAR_RESET
231	LWI r29, MBAR
232	rlwinm r30, r29,16,16,31
233	stw r30, 0(r31) /* Set the MBAR */
234	#endif
235
236	LWI r31, MBAR /* set r31 to current MBAR */
237	/* init GPIOPCR */
238	lwz r29,GPIOPCR(r31)
239	LWI r30, GPIOPCR_INITMASK
240	not r30,r30
241	and r29,r29,r30
242	LWI r30, GPIOPCR_INITVAL
243	or r29,r29,r30
244	stw r29, GPIOPCR(r31)
245
246	/* further initialization work (common RAM/ROM startup) */
247	bl TLB_init /* Initialize TLBs */
248
249
250	bl FID_DCache /* Flush, inhibit and disable data cache */
251
252
253	bl IDUL_ICache /* Inhibit, disable and unlock instruction cache */
254
255
256	bl FPU_init /* Initialize FPU */
257
258
259	#if defined(NEED_LOW_LEVEL_INIT)
260	bl SPRG_init /* Initialize special purpose registers */
261	#endif
262
263	#if defined(NEED_LOW_LEVEL_INIT)
264	/* detect RAM/ROM startup (common for RAM/ROM startup) */
265	LWI r20, ROM_START /* set the relocation offset */
266
267
268	LWI r30, CFG_VAL /* get CFG register content */
269	lwz r30, CFG(r31) /* set SDRAM single data rate / XLB_CLK=FVCO/4 / IPB_CLK=XLB_CLK/2 / PCICLK=IPB_CLK */
270
271
272
273	lwz r30, ADREN(r31) /* get content of ADREN */
274
275
276
277	TSTBITS r30, r29, ADREN_BOOT_EN
278	bne skip_ROM_start /* If BOOT_ROM is not enabled, skip further initialization */
279
280	/* do some board dependent configuration (unique for ROM startup) */
281	bl SPRG_brk_init /* Initialize special purpose onchip breakpoint registers */
282
283
284	LWI r30, CSCONTROL_VAL /* get CSCONTROL register content */
285	stw r30, CSCONTROL(r31) /* enable internal/external bus error and master for CS */
286
287
288
289	#ifdef BRS5L
290	LWI r30, CSBOOTROM_VAL
291	stw r30, CSBOOTROM(r31) /* Set CSBOOTROM */
292
293
294	#endif
295
296
297	/* FIXME: map BOOT ROM into final location with CS0 registers */
298	LWI r30, ROM_START
299	rlwinm r30, r30,17,15,31
300	stw r30, CS0STR(r31) /* Set CS0STR */
301
302	lis r30, ROM_END@h
303	ori r30, r30, ROM_END@l
304
305	rlwinm r30, r30,17,15,31
306	stw r30, CS0STP(r31) /* Set CS0STP */
307
308	lwz r30, ADREN(r31) /* get content of ADREN */
309	SETBITS r30, r29, ADREN_CS0_EN
310	stw r30, ADREN(r31) /* enable CS0 mapping */
311	isync
312	/* jump to same code in final BOOT ROM location */
313	LWI r30, reloc_in_CS0
314	LWI r29, RAM_START
315	sub r30,r30,r29
316	LWI r29, ROM_START
317	add r30,r30,r29
318	mtctr r30
319	bctr
320
321	reloc_in_CS0:
322	/* disable CSBOOT (or map it to CS0 range) */
323	lwz r30, ADREN(r31) /* get content of ADREN */
324	CLRBITS r30, r29, ADREN_BOOT_EN
325	stw r30, ADREN(r31) /* disable BOOT mapping */
326
327	/* init SDRAM */
328	LWI r30, RAM_START
329	ori r30,r30,0x1a /* size code: bank is 128MByte */
330	stw r30,SDRAMCS0(r31) /* Set SDRAMCS0 */
331
332	LWI r30,(RAM_SIZE)>>1
333	ori r30,r30,0x1a /* size code: bank is 128MByte */
334	stw r30, SDRAMCS1(r31) /* Set SDRAMCS1 */
335
336	bl SDRAM_init /* Initialize SDRAM controller */
337
338	/* init arbiter and stuff... */
339	LWI r30, 0x8000a06e
340	stw r30, ARBCFG(r31) /* Set ARBCFG */
341
342	LWI r30, 0x000000ff
343	stw r30, ARBMPREN(r31) /* Set ARBMPREN */
344
345	LWI r30, 0x00001234
346	stw r30, ARBMPRIO(r31) /* Set ARBPRIO */
347
348	LWI r30, 0x0000001e
349	stw r30, ARBSNOOP(r31) /* Set ARBSNOOP */
350	/* copy .text section from ROM to RAM location (unique for ROM startup) */
351	LA r30, _text_start /* get start address of text section in RAM */
352
353
354	add r30, r20, r30 /* get start address of text section in ROM (add reloc offset) */
355
356
357	LA r29, _text_start /* get start address of text section in RAM */
358
359
360	LA r28, _text_size /* get size of RAM image */
361
362
363	bl copy_image /* copy text section from ROM to RAM location */
364
365
366	/* copy .data section from ROM to RAM location (unique for ROM startup) */
367	LA r30, _data_start /* get start address of data section in RAM */
368
369
370	add r30, r20, r30 /* get start address of data section in ROM (add reloc offset) */
371
372
373	LA r29, _data_start /* get start address of data section in RAM */
374
375
376	LA r28, _data_size /* get size of RAM image */
377
378
379	bl copy_image /* copy initialized data section from ROM to RAM location */
380
381
382	LA r29, remap_rom /* get compile time address of label */
383	mtlr r29
384
385	blrl /* now further execution RAM */
386
387	remap_rom:
388	/* remap BOOT ROM to CS0 (common for RAM/ROM startup) */
389	lwz r30, CSBOOTROM(r31) /* get content of CSBOOTROM */
390
391
392
393	CLRBITS r30, r29, CSCONF_CE
394	stw r30, CSBOOTROM(r31) /* disable BOOT CS */
395
396
397
398	lwz r30, ADREN(r31) /* get content of ADREN */
399
400
401
402	mr r29, r30 /* move content of r30 to r29 */
403
404
405	LWI r30, ADREN_BOOT_EN /* mask ADREN_BOOT_EN */
406	andc r29,r29,r30
407
408
409	LWI r30, ADREN_CS0_EN /* unmask ADREN_CS0_EN */
410	or r29,r29,r30
411
412
413	stw r29,ADREN(r31) /* Simultaneous enable CS0 and disable BOOT address space */
414
415
416
417	lwz r30, CSBOOTROM(r31) /* get content of CSBOOTROM */
418
419
420
421	SETBITS r30, r29, CSCONF_CE
422	stw r30, CSBOOTROM(r31) /* disable BOOT CS */
423
424
425
426	skip_ROM_start:
427	/* configure external DPRAM CS1 */
428	LWI r30,0xFFFFFB10
429	stw r30,CS1CONF(r31)
430
431	/* map external DPRAM (CS1) */
432	LWI r30,(DPRAM_START>>16)
433	stw r30,CS1STR(r31)
434
435	LWI r30,((DPRAM_END)>>16)
436	stw r30,CS1STP(r31)
437
438	lwz r30, ADREN(r31) /* get content of ADREN */
439
440	LWI r29, ADREN_CS1_EN /* unmask ADREN_CS1_EN */
441	or r30,r30,r29
442
443	stw r30,ADREN(r31) /* enable CS1 */
444
445	/* clear entire on chip SRAM (unique for ROM startup) */
446	lis r30, (MBAR+ONCHIP_SRAM_OFFSET)@h /* get start address of onchip SRAM */
447	ori r30,r30,(MBAR+ONCHIP_SRAM_OFFSET)@l
448	LWI r29, ONCHIP_SRAM_SIZE /* get size of onchip SRAM */
449
450	bl clr_mem /* Clear onchip SRAM */
451
452	#endif /* defined(BRS5L) */
453	/* clear .bss section (unique for ROM startup) */
454	LWI r30, _bss_start /* get start address of bss section */
455	LWI r29, _bss_size /* get size of bss section */
456
457
458	bl clr_mem /* Clear the bss section */
459
460
461	/* set stack pointer (common for RAM/ROM startup) */
462	LA r1, _text_start
463	addi r1, r1, -0x10 /* Set up stack pointer = beginning of text section - 0x10 */
464
465
466	/* enable dynamic power management(common for RAM/ROM startup) */
467	bl PPC_HID0_rd /* Get the content of HID0 */
468
469	SETBITS r30, r29, HID0_DPM
470	bl PPC_HID0_wr /* Set DPM in HID0 */
471
472	/* clear arguments and do further init. in C (common for RAM/ROM startup) */
473
474	/* Clear argc, argv and envp */
475	xor r3, r3, r3
476	xor r4, r4, r4
477	xor r5, r5, r5
478
479	bl SYM (boot_card) /* Call the first C routine */
480
481	#if defined(BRS5L)
482	twiddle:
483	b twiddle /* We don't expect to return from boot_card but if we do */
484	/* wait here for watchdog to kick us into hard reset */
485
486	SDRAM_init:
487	#if defined (BRS5L)
488	/* set GPIO_WKUP7 pin low for 66MHz buffering */
489	/* or high for 133MHz registered buffering */
490	LWI r30, 0x80000000
491
492	lwz r29, GPIOWE(r31)
493	or r29,r29,r30 /* set bit 0 in r29/GPIOWE */
494	stw r29,GPIOWE(r31)
495
496	lwz r29, GPIOWOD(r31)
497	andc r29,r29,r30 /* clear bit 0 in r29/GPIOWOD */
498	stw r29,GPIOWOD(r31)
499
500	lwz r29, GPIOWDO(r31)
501	andc r29,r29,r30 /* clear bit 0 in r29/GPIOWDO */
502	stw r29,GPIOWDO(r31)
503
504	lwz r29, GPIOWDD(r31)
505	or r29,r29,r30 /* set bit 0 in r29/GPIOWDD */
506	stw r29,GPIOWDD(r31)
507
508	/* activate MEM_CS1 output */
509	lwz r29, GPIOPCR(r31)
510	or r29,r29,r30 /* set bit 0 in r29/GPIOPCR */
511	stw r29,GPIOPCR(r31)
512
513	#endif
514	#if 0
515	LWI r30, 0xC2222600 /* Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x2 */
516	stw r30, CFG1(r31) /* Read CAS latency=0x2, Active2Read delay=0x2, Prec.2active delay=0x2 */
517	/* Refr.2No-Read delay=0x06, Write latency=0x0 */
518	#else
519	/* See Erratum 342/339 in MPC5200_Errata_L25R_3_June.pdf: */
520	/* set 5 delays to their maximum to support two banks */
521	LWI r30, 0xCC222600 /* Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x2 */
522	stw r30, CFG1(r31) /* Read CAS latency=0x2, Active2Read delay=0x2, Prec.2active delay=0x2 */
523	/* Refr.2No-Read delay=0x06, Write latency=0x0 */
524	#endif
525
526	LWI r30, 0xCCC70004 /* Burst2Read Prec.delay=0x8, Burst Write delay=0x8 */
527	stw r30, CFG2(r31) /* Burst Read2Write delay=0xB, Burst length=0x7, Read Tap=0x4 */
528
529	#ifdef BRS5L
530	LWI r30, 0xD1470000 /* Mode Set enabled, Clock enabled, Auto refresh enabled, Mem. data drv */
531	stw r30, CTRL(r31) /* Refresh counter=0xFFFF */
532
533
534	#else
535	LWI r30, 0xD04F0000 /* Mode Set enabled, Clock enabled, Auto refresh enabled, Mem. data drv */
536	stw r30, CTRL(r31) /* Refresh counter=0xFFFF */
537
538
539	#endif
540	lwz r30, CTRL(r31)
541
542
543	SETBITS r30, r29, CTRL_PRECHARGE /* send two times precharge */
544	stw r30, CTRL(r31)
545
546
547	stw r30, CTRL(r31)
548
549
550
551	lwz r30, CTRL(r31)
552
553
554	SETBITS r30, r29, CTRL_REFRESH /* send two times refresh */
555	stw r30, CTRL(r31)
556
557
558	stw r30, CTRL(r31)
559
560
561
562	LWI r30, 0x008D0000 /* Op.Mode=0x0, Read CAS latency=0x2, Burst length=0x3, Write strobe puls */
563	stw r30, MOD(r31)
564
565
566
567	lwz r30, CTRL(r31) /* Clock enabled, Auto refresh enabled, Mem. data drv. Refresh counter=0xFFFF */
568
569
570	CLRBITS r30, r29, CTRL_BA1
571	stw r30, CTRL(r31)
572
573
574
575	blr
576
577
578	copy_image:
579	mr r27, r28
580	srwi r28, r28, 2
581	mtctr r28
582
583
584	slwi r28, r28, 2
585	sub r27, r27, r28 /* maybe some residual bytes */
586
587
588	copy_image_word:
589	lswi r28, r30, 0x04
590
591	stswi r28, r29, 0x04 /* do word copy ROM -> RAM */
592
593
594	addi r30, r30, 0x04 /* increment source pointer */
595	addi r29, r29, 0x04 /* increment destination pointer */
596
597	bdnz copy_image_word /* decrement ctr and branch if not 0 */
598
599	cmpwi r27, 0x00 /* copy image finished ? */
600	beq copy_image_end;
601	mtctr r27 /* reload counter for residual bytes */
602	copy_image_byte:
603	lswi r28, r30, 0x01
604
605	stswi r28, r29, 0x01 /* do byte copy ROM -> RAM */
606
607
608	addi r30, r30, 0x01 /* increment source pointer */
609	addi r29, r29, 0x01 /* increment destination pointer */
610
611	bdnz copy_image_byte /* decrement ctr and branch if not 0 */
612
613	copy_image_end:
614	blr
615	#endif /* defined(BRS5L) */
616
617	FID_DCache:
618	mflr r26
619
620	bl PPC_HID0_rd
621	TSTBITS r30, r29, HID0_DCE
622	bne FID_DCache_exit /* If data cache is switched of, skip further actions */
623
624	li r29, PPC_D_CACHE /* 16 Kb data cache on 603e */
625	LWI r28, _text_start /* Load base address (begin of RAM) */
626
627	FID_DCache_loop_1:
628	lwz r27, 0(r28) /* Load data at address */
629
630	addi r28, r28, PPC_CACHE_ALIGNMENT /* increment cache line address */
631	subi r29, r29, PPC_CACHE_ALIGNMENT /* increment loop counter */
632	cmpwi r29, 0x0
633	bne FID_DCache_loop_1 /* Loop until cache size is reached */
634
635	li r29, PPC_D_CACHE /* 16 Kb data cache on 603e */
636	LWI r28, _text_start /* Reload base address (begin of RAM) */
637	xor r27, r27, r27
638	FID_DCache_loop_2:
639
640	dcbf r27, r28 /* Flush and invalidate cache */
641
642	addi r28, r28, PPC_CACHE_ALIGNMENT /* increment cache line address */
643	subi r29, r29, PPC_CACHE_ALIGNMENT /* increment loop counter */
644	cmpwi r29, 0x0
645	bne FID_DCache_loop_2 /* Loop around until cache size is reached */
646
647	bl PPC_HID0_rd /* Read HID0 */
648	CLRBITS r30, r29, HID0_DCE
649	bl PPC_HID0_wr /* Clear DCE */
650
651	FID_DCache_exit:
652	mtlr r26
653	blr
654
655	IDUL_ICache:
656	mflr r26
657
658	bl PPC_HID0_rd
659	TSTBITS r30, r29, HID0_ICE
660	bne IDUL_ICache_exit /* If instruction cache is switched of, skip further actions */
661
662	CLRBITS r30, r29, HID0_ICE
663	bl PPC_HID0_wr /* Disable ICE bit */
664
665	SETBITS r30, r29, HID0_ICFI
666	bl PPC_HID0_wr /* Invalidate instruction cache */
667
668	CLRBITS r30, r29, HID0_ICFI
669	bl PPC_HID0_wr /* Disable cache invalidate */
670
671	CLRBITS r30, r29, HID0_ILOCK
672	bl PPC_HID0_wr /* Disable instruction cache lock */
673
674	IDUL_ICache_exit:
675	mtlr r26
676	blr
677
678
679	TLB_init: /* Initialize translation lookaside buffers (TLBs) */
680	xor r30, r30, r30
681	xor r29, r29, r29
682
683	TLB_init_loop:
684	tlbie r29
685	tlbsync
686	addi r29, r29, 0x1000
687	addi r30, r30, 0x01
688	cmpli 0, 0, r30, 0x0080
689	bne TLB_init_loop
690	blr
691
692	FPU_init:
693	mfmsr r30 /* get content of MSR */
694
695
696	SETBITS r30, r29, MSR_FP
697	mtmsr r30 /* enable FPU and FPU exceptions */
698
699	#if 0
700	LA r29, RAM_START
701	stw r29, 0x0(r29)
702	#endif
703
704	lfd f0, 0(r29)
705	fmr f1, f0
706	fmr f2, f0
707	fmr f3, f0
708	fmr f4, f0
709	fmr f5, f0
710	fmr f6, f0
711	fmr f7, f0
712	fmr f8, f0
713	fmr f9, f0
714	fmr f10, f0
715	fmr f11, f0
716	fmr f12, f0
717	fmr f13, f0
718	fmr f14, f0
719	fmr f15, f0
720	fmr f16, f0
721	fmr f17, f0
722	fmr f18, f0
723	fmr f19, f0
724	fmr f20, f0
725	fmr f21, f0
726	fmr f22, f0
727	fmr f23, f0
728	fmr f24, f0
729	fmr f25, f0
730	fmr f26, f0
731	fmr f27, f0
732	fmr f28, f0
733	fmr f29, f0
734	fmr f30, f0
735	fmr f31, f0
736
737
738	mtfsfi 0, 0 /* initialize bit positons in FPSCR */
739	mtfsfi 1, 0
740	mtfsfi 2, 0
741	mtfsfi 3, 0
742	mtfsfi 4, 0
743	mtfsfi 5, 0
744	mtfsfi 6, 0
745	mtfsfi 7, 0
746
747	blr
748
749	SPRG_init: /* initialize registers */
750	xor r30, r30, r30
751
752	mtspr XER, r30
753	mtspr CTR, r30
754	mtspr DSISR, r30
755	mtspr DAR, r30
756	mtspr DEC, r30
757	mtspr SDR1, r30
758	mtspr SRR0, r30
759	mtspr SRR1, r30
760	mtspr CSSR0, r30
761	mtspr CSSR1, r30
762	mtspr SPRG0, r30
763	mtspr SPRG1, r30
764	mtspr SPRG2, r30
765	mtspr SPRG3, r30
766	mtspr SPRG4, r30
767	mtspr SPRG5, r30
768	mtspr SPRG6, r30
769	mtspr SPRG7, r30
770	mtspr EAR, r30
771	mtspr TBWU, r30
772	mtspr TBWL, r30
773	mtspr IBAT0U, r30
774	mtspr IBAT0L, r30
775	mtspr IBAT1U, r30
776	mtspr IBAT1L, r30
777	mtspr IBAT2U, r30
778	mtspr IBAT2L, r30
779	mtspr IBAT3U, r30
780	mtspr IBAT3L, r30
781	mtspr IBAT4U, r30
782	mtspr IBAT4L, r30
783	mtspr IBAT5U, r30
784	mtspr IBAT5L, r30
785	mtspr IBAT6U, r30
786	mtspr IBAT6L, r30
787	mtspr IBAT7U, r30
788	mtspr IBAT7L, r30
789	mtspr DBAT0U, r30
790	mtspr DBAT0L, r30
791	mtspr DBAT1U, r30
792	mtspr DBAT1L, r30
793	mtspr DBAT2U, r30
794	mtspr DBAT2L, r30
795	mtspr DBAT3U, r30
796	mtspr DBAT3L, r30
797	mtspr DBAT4U, r30
798	mtspr DBAT4L, r30
799	mtspr DBAT5U, r30
800	mtspr DBAT5L, r30
801	mtspr DBAT6U, r30
802	mtspr DBAT6L, r30
803	mtspr DBAT7U, r30
804	mtspr DBAT7L, r30
805	mtspr DMISS, r30
806	mtspr DCMP, r30
807	mtspr HASH1, r30
808	mtspr HASH2, r30
809	mtspr IMISS, r30
810	mtspr ICMP, r30
811	mtspr RPA, r30
812	mtsr SR0, r30
813	mtsr SR1, r30
814	mtsr SR2, r30
815	mtsr SR3, r30
816	mtsr SR4, r30
817	mtsr SR5, r30
818	mtsr SR6, r30
819	mtsr SR7, r30
820	mtsr SR8, r30
821	mtsr SR9, r30
822	mtsr SR10, r30
823	mtsr SR12, r30
824	mtsr SR13, r30
825	mtsr SR14, r30
826	mtsr SR15, r30
827
828
829
830
831
832	blr
833
834	SPRG_brk_init:
835	xor r30, r30, r30
836
837	mtspr DABR2, r30
838	mtspr DBCR, r30
839	mtspr IBCR, r30
840	mtspr IABR, r30
841	mtspr HID2, r30
842	mtspr DABR, r30
843	mtspr IABR2, r30
844
845
846
847
848	blr
849
850
851	PPC_HID0_rd: /* get HID0 content to r30 */
852
853
854	mfspr r30, HID0
855
856	blr
857
858
859	PPC_HID0_wr: /* put r30 content to HID0 */
860
861
862	mtspr HID0, r30
863
864	blr
865
866	clr_mem:
867	mr r28, r29
868	srwi r29, r29, 2
869	mtctr r29 /* set ctr reg */
870
871
872	slwi r29, r29, 2
873	sub r28, r28, r29 /* maybe some residual bytes */
874	xor r29, r29, r29
875
876
877	clr_mem_word:
878	stswi r29, r30, 0x04 /* store r29 (word) to r30 memory location */
879	addi r30, r30, 0x04 /* increment r30 */
880
881	bdnz clr_mem_word /* dec counter and loop */
882
883
884	cmpwi r28, 0x00 /* clear mem. finished ? */
885	beq clr_mem_end;
886	mtctr r28 /* reload counter for residual bytes */
887	clr_mem_byte:
888	stswi r29, r30, 0x01 /* store r29 (byte) to r30 memory location */
889	addi r30, r30, 0x01 /* update r30 */
890
891	bdnz clr_mem_byte /* dec counter and loop */
892
893	clr_mem_end:
894	blr /* return */
895
896
897

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