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start.S @ 2793778

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Last change on this file since 2793778 was 2793778, checked in by Sebastian Huber <sebastian.huber@…>, on 04/19/13 at 11:00:14
bsp/mpc5200: Remove Erratum 342/339 comment
Property mode set to `100644`
File size: 23.5 KB

Line
1	/===============================================================\
2	\| Project: RTEMS generic MPC5200 BSP \|
3	+-----------------------------------------------------------------+
4	\| Partially based on the code references which are named below. \|
5	\| Adaptions, modifications, enhancements and any recent parts of \|
6	\| the code are: \|
7	\| Copyright (c) 2005 \|
8	\| Embedded Brains GmbH \|
9	\| Obere Lagerstr. 30 \|
10	\| D-82178 Puchheim \|
11	\| Germany \|
12	\| rtems@embedded-brains.de \|
13	+-----------------------------------------------------------------+
14	\| The license and distribution terms for this file may be \|
15	\| found in the file LICENSE in this distribution or at \|
16	\| \|
17	\| http://www.rtems.com/license/LICENSE. \|
18	\| \|
19	+-----------------------------------------------------------------+
20	\| this file contains the startup assembly code \|
21	\===============================================================/
22	/***********************************************************************/
23	/* */
24	/* Module: start.S */
25	/* Date: 07/17/2003 */
26	/* Purpose: RTEMS MPC5x00 CPU assembly startup */
27	/* */
28	/---------------------------------------------------------------------/
29	/* */
30	/* Description: This file contains the assembler portion of MPC5x00 */
31	/* startup code */
32	/* */
33	/---------------------------------------------------------------------/
34	/* */
35	/* Code */
36	/* References: startup code for Motorola PQII ADS board */
37	/* Module: start.S */
38	/* Project: RTEMS 4.6.0pre1 / MCF8260ads BSP */
39	/* Version 1.2 */
40	/* Date: 04/18/2002 */
41	/* */
42	/* Author(s) / Copyright(s): */
43	/* */
44	/* Modified for the Motorola PQII ADS board by */
45	/* Andy Dachs <a.dachs@sstl.co.uk> 23-11-00. */
46	/* Surrey Satellite Technology Limited */
47	/* */
48	/* I have a proprietary bootloader programmed into the flash */
49	/* on the board which initialises the SDRAM prior to calling */
50	/* this function. */
51	/* */
52	/* This file is based on the one by Jay Monkman (jmonkman@fracsa.com)*/
53	/* which in turn was based on the dlentry.s file for the Papyrus BSP,*/
54	/* written by: */
55	/* */
56	/* Author: Andrew Bray <andy@i-cubed.co.uk> */
57	/* */
58	/* COPYRIGHT (c) 1995 by i-cubed ltd. */
59	/* */
60	/* To anyone who acknowledges that this file is provided "AS IS" */
61	/* without any express or implied warranty: */
62	/* permission to use, copy, modify, and distribute this file */
63	/* for any purpose is hereby granted without fee, provided that */
64	/* the above copyright notice and this notice appears in all */
65	/* copies, and that the name of i-cubed limited not be used in */
66	/* advertising or publicity pertaining to distribution of the */
67	/* software without specific, written prior permission. */
68	/* i-cubed limited makes no representations about the suitability */
69	/* of this software for any purpose. */
70	/* */
71	/---------------------------------------------------------------------/
72	/* */
73	/* Partially based on the code references which are named above. */
74	/* Adaptions, modifications, enhancements and any recent parts of */
75	/* the code are under the right of */
76	/* */
77	/* IPR Engineering, Dachauer StraÃe 38, D-80335 MÃŒnchen */
78	/* Copyright(C) 2003 */
79	/* */
80	/---------------------------------------------------------------------/
81	/* */
82	/* IPR Engineering makes no representation or warranties with */
83	/* respect to the performance of this computer program, and */
84	/* specifically disclaims any responsibility for any damages, */
85	/* special or consequential, connected with the use of this program. */
86	/* */
87	/---------------------------------------------------------------------/
88	/* */
89	/* Version history: 1.0 */
90	/* */
91	/***********************************************************************/
92
93	#include <rtems/powerpc/cache.h>
94
95	#include <bsp.h>
96	#include <bsp/mpc5200.h>
97
98	/* Some register offsets of MPC5x00 memory map registers */
99	.set CS0STR, 0x04
100	.set CS0STP, 0x08
101	.set CS1STR, 0x0C
102	.set CS1STP, 0x10
103	.set SDRAMCS0, 0x34
104	.set SDRAMCS1, 0x38
105	.set BOOTSTR, 0x4C
106	.set BOOTSTP, 0x50
107	.set ADREN, 0x54
108	.set CSSR0, 0x58 /* Critical Interrupt SSR0 (603le only) */
109	.set CSSR1, 0x59 /* Critical Interrupt SSR1 (603le only) */
110	.set CFG, 0x20C
111	.set CSBOOTROM, 0x300
112	.set CSCONTROL, 0x318
113	.set CS1CONF, 0x304
114
115
116	/* Register offsets of MPC5x00 SDRAM memory controller registers */
117	.set MOD, 0x100
118	.set CTRL, 0x104
119	.set CFG1, 0x108
120	.set CFG2, 0x10C
121	.set ADRSEL, 0x110
122
123	/* Register offsets of MPC5x00 GPIO registers needed */
124	.set GPIOPCR, 0xb00
125	.set GPIOWE, 0xc00
126	.set GPIOWOD, 0xc04
127	.set GPIOWDD, 0xc08
128	.set GPIOWDO, 0xc0c
129
130	.set GPIOSEN, 0xb04
131	.set GPIOSDD, 0xb0c
132	.set GPIOSDO, 0xb10
133
134	/* Register offsets of MPC5x00 Arbiter registers */
135	.set ARBCFG, 0x1f40
136	.set ARBADRTO, 0x1f58
137	.set ARBDATTO, 0x1f5c
138	.set ARBMPREN, 0x1f64
139	.set ARBMPRIO, 0x1f68
140	.set ARBSNOOP, 0x1f70
141
142	/* Some bit encodings for MGT5100 registers */
143	.set ADREN_SDRAM_EN, (1<<22)
144	.set ADREN_BOOT_EN, (1<<25)
145	.set ADREN_CS0_EN, (1<<16)
146	.set ADREN_CS1_EN, (1<<17)
147
148	.set CTRL_PRECHARGE, (1<<1)
149	.set CTRL_REFRESH, (1<<2)
150	.set CTRL_BA1, (1<<31)
151
152	.set CSCONF_CE, (1<<12)
153
154	/* Some fixed values for MPC5x00 registers */
155	.set CSBOOTROM_VAL, 0x0101D910
156	.set CSCONTROL_VAL, 0x91000000
157	.set CFG_VAL, 0x00000100
158
159	.extern boot_card
160
161	.section ".vectors", "ax"
162	bl start
163	.rep 63
164	.long 0x04000400
165	.endr
166	__vec2: b __vec2
167	.rep 63
168	.long 0x04000400
169	.endr
170	__vec3: b __vec3
171	.rep 63
172	.long 0x04000400
173	.endr
174	__vec4: b __vec4
175	.rep 63
176	.long 0x04000400
177	.endr
178	__vec5: b __vec5
179	.rep 63
180	.long 0x04000400
181	.endr
182	__vec6: b __vec6
183	.rep 63
184	.long 0x04000400
185	.endr
186	__vec7: b __vec7
187	.rep 63
188	.long 0x04000400
189	.endr
190	__vec8: b __vec8
191	.rep 63
192	.long 0x04000400
193	.endr
194	__vec9: b __vec9
195	.rep 63
196	.long 0x04000400
197	.endr
198	__veca: b __veca
199	.rep 63
200	.long 0x04000400
201	.endr
202	__vecb: b __vecb
203	.rep 63
204	.long 0x04000400
205	.endr
206	__vecc: b __vecc
207	.rep 63
208	.long 0x04000400
209	.endr
210	__vecd: b __vecd
211	.rep 63
212	.long 0x04000400
213	.endr
214	__vece: b __vece
215	.rep 63
216	.long 0x04000400
217	.endr
218	__vecf: b __vecf
219	.rep 63+1024
220	.long 0x04000400
221	.endr
222
223	.section ".entry"
224	PUBLIC_VAR (start)
225	start:
226	/* 1st: initialization work (common for RAM/ROM startup) */
227	mfmsr r30
228	SETBITS r30, r29, MSR_ME\|MSR_RI
229	CLRBITS r30, r29, MSR_EE
230	mtmsr r30 /* Set RI/ME, Clr EE in MSR */
231
232	#ifdef HAS_UBOOT
233	mr r14, r3
234	#endif /* HAS_UBOOT */
235
236	#if defined(NEED_LOW_LEVEL_INIT)
237	/* initialize the MBAR (common RAM/ROM startup) */
238	LWI r31, MBAR_RESET
239	LWI r29, MBAR
240	rlwinm r30, r29,16,16,31
241	stw r30, 0(r31) /* Set the MBAR */
242	#endif
243
244	LWI r31, MBAR /* set r31 to current MBAR */
245	/* init GPIOPCR */
246	lwz r29,GPIOPCR(r31)
247	LWI r30, BSP_GPIOPCR_INITMASK
248	not r30,r30
249	and r29,r29,r30
250	LWI r30, BSP_GPIOPCR_INITVAL
251	or r29,r29,r30
252	stw r29, GPIOPCR(r31)
253
254	/* further initialization work (common RAM/ROM startup) */
255	bl TLB_init /* Initialize TLBs */
256
257
258	bl FID_DCache /* Flush, inhibit and disable data cache */
259
260
261	bl IDUL_ICache /* Inhibit, disable and unlock instruction cache */
262
263
264	bl FPU_init /* Initialize FPU */
265
266
267	#if defined(NEED_LOW_LEVEL_INIT)
268	bl SPRG_init /* Initialize special purpose registers */
269	#endif
270
271	#if defined(NEED_LOW_LEVEL_INIT)
272	/* detect RAM/ROM startup (common for RAM/ROM startup) */
273	LWI r20, bsp_rom_start /* set the relocation offset */
274
275
276	LWI r30, CFG_VAL /* get CFG register content */
277	lwz r30, CFG(r31) /* set SDRAM single data rate / XLB_CLK=FVCO/4 / IPB_CLK=XLB_CLK/2 / PCICLK=IPB_CLK */
278
279
280
281	lwz r30, ADREN(r31) /* get content of ADREN */
282
283
284
285	TSTBITS r30, r29, ADREN_BOOT_EN
286	bne skip_ROM_start /* If BOOT_ROM is not enabled, skip further initialization */
287
288	/* do some board dependent configuration (unique for ROM startup) */
289	LWI r30, CSCONTROL_VAL /* get CSCONTROL register content */
290	stw r30, CSCONTROL(r31) /* enable internal/external bus error and master for CS */
291
292
293
294	#ifdef MPC5200_BOARD_BRS5L
295	LWI r30, CSBOOTROM_VAL
296	stw r30, CSBOOTROM(r31) /* Set CSBOOTROM */
297
298
299	#endif /* MPC5200_BOARD_BRS5L */
300
301
302	/* FIXME: map BOOT ROM into final location with CS0 registers */
303	LWI r30, bsp_rom_start
304	rlwinm r30, r30,17,15,31
305	stw r30, CS0STR(r31) /* Set CS0STR */
306
307	LWI r30, bsp_rom_end - 1
308
309	rlwinm r30, r30,17,15,31
310	stw r30, CS0STP(r31) /* Set CS0STP */
311
312	lwz r30, ADREN(r31) /* get content of ADREN */
313	SETBITS r30, r29, ADREN_CS0_EN
314	stw r30, ADREN(r31) /* enable CS0 mapping */
315	isync
316	/* jump to same code in final BOOT ROM location */
317	LWI r30, reloc_in_CS0
318	LWI r29, bsp_ram_start
319	sub r30,r30,r29
320	LWI r29, bsp_rom_start
321	add r30,r30,r29
322	mtctr r30
323	bctr
324
325	reloc_in_CS0:
326	/* disable CSBOOT (or map it to CS0 range) */
327	lwz r30, ADREN(r31) /* get content of ADREN */
328	CLRBITS r30, r29, ADREN_BOOT_EN
329	stw r30, ADREN(r31) /* disable BOOT mapping */
330
331	/* init SDRAM */
332	LWI r30, bsp_ram_start
333	ori r30, r30, 0x1a /* size code: bank is 128MByte */
334	stw r30, SDRAMCS0(r31) /* Set SDRAMCS0 */
335
336	LWI r30, bsp_ram_size
337	srawi r30, r30, 1
338	ori r30, r30, 0x1a /* size code: bank is 128MByte */
339	stw r30, SDRAMCS1(r31) /* Set SDRAMCS1 */
340
341	bl SDRAM_init /* Initialize SDRAM controller */
342
343	bl XLB_init
344	/* copy .text section from ROM to RAM location (unique for ROM startup) */
345	LA r30, bsp_section_text_start /* get start address of text section in RAM */
346
347
348	add r30, r20, r30 /* get start address of text section in ROM (add reloc offset) */
349
350
351	LA r29, bsp_section_text_start /* get start address of text section in RAM */
352
353
354	LA r28, bsp_section_text_size /* get size of RAM image */
355
356
357	bl copy_image /* copy text section from ROM to RAM location */
358
359
360	/* copy .data section from ROM to RAM location (unique for ROM startup) */
361	LA r30, bsp_section_data_start /* get start address of data section in RAM */
362
363
364	add r30, r20, r30 /* get start address of data section in ROM (add reloc offset) */
365
366
367	LA r29, bsp_section_data_start /* get start address of data section in RAM */
368
369
370	LA r28, bsp_section_data_size /* get size of RAM image */
371
372
373	bl copy_image /* copy initialized data section from ROM to RAM location */
374
375
376	LA r29, remap_rom /* get compile time address of label */
377	mtlr r29
378
379	blrl /* now further execution RAM */
380
381	remap_rom:
382	/* remap BOOT ROM to CS0 (common for RAM/ROM startup) */
383	lwz r30, CSBOOTROM(r31) /* get content of CSBOOTROM */
384
385
386
387	CLRBITS r30, r29, CSCONF_CE
388	stw r30, CSBOOTROM(r31) /* disable BOOT CS */
389
390
391
392	lwz r30, ADREN(r31) /* get content of ADREN */
393
394
395
396	mr r29, r30 /* move content of r30 to r29 */
397
398
399	LWI r30, ADREN_BOOT_EN /* mask ADREN_BOOT_EN */
400	andc r29,r29,r30
401
402
403	LWI r30, ADREN_CS0_EN /* unmask ADREN_CS0_EN */
404	or r29,r29,r30
405
406
407	stw r29,ADREN(r31) /* Simultaneous enable CS0 and disable BOOT address space */
408
409
410
411	lwz r30, CSBOOTROM(r31) /* get content of CSBOOTROM */
412
413
414
415	SETBITS r30, r29, CSCONF_CE
416	stw r30, CSBOOTROM(r31) /* disable BOOT CS */
417
418
419
420	skip_ROM_start:
421	/* configure external DPRAM CS1 */
422	LWI r30, 0xFFFFFB10
423	stw r30, CS1CONF(r31)
424
425	/* map external DPRAM (CS1) */
426	LWI r30, bsp_dpram_start
427	srawi r30, r30, 16
428	stw r30, CS1STR(r31)
429
430	LWI r30, bsp_dpram_end
431	srawi r30, r30, 16
432	stw r30, CS1STP(r31)
433
434	lwz r30, ADREN(r31) /* get content of ADREN */
435
436	LWI r29, ADREN_CS1_EN /* unmask ADREN_CS1_EN */
437	or r30, r30,r29
438
439	stw r30, ADREN(r31) /* enable CS1 */
440
441	/* clear entire on chip SRAM (unique for ROM startup) */
442	lis r30, (MBAR+ONCHIP_SRAM_OFFSET)@h /* get start address of onchip SRAM */
443	ori r30, r30,(MBAR+ONCHIP_SRAM_OFFSET)@l
444	LWI r29, ONCHIP_SRAM_SIZE /* get size of onchip SRAM */
445
446	bl clr_mem /* Clear onchip SRAM */
447
448	#else /* defined(NEED_LOW_LEVEL_INIT) */
449	bl XLB_init
450	#endif /* defined(NEED_LOW_LEVEL_INIT) */
451	/* clear .bss section (unique for ROM startup) */
452	LWI r30, bsp_section_bss_start /* get start address of bss section */
453	LWI r29, bsp_section_bss_size /* get size of bss section */
454
455
456	bl clr_mem /* Clear the bss section */
457
458	#ifdef HAS_UBOOT
459	mr r3, r14
460	bl bsp_uboot_copy_board_info
461	#endif /* HAS_UBOOT */
462
463	/* set stack pointer (common for RAM/ROM startup) */
464	LA r1, bsp_section_text_start
465	addi r1, r1, -0x10 /* Set up stack pointer = beginning of text section - 0x10 */
466	/* tag TOS with a NULL pointer (termination mark for stack dump) */
467	li r0, 0
468	stw r0, 0(r1)
469
470	bl __eabi /* Set up EABI and SYSV environment */
471
472	/* enable dynamic power management(common for RAM/ROM startup) */
473	bl PPC_HID0_rd /* Get the content of HID0 */
474
475	SETBITS r30, r29, HID0_DPM
476	bl PPC_HID0_wr /* Set DPM in HID0 */
477
478	/* clear arguments and do further init. in C (common for RAM/ROM startup) */
479
480	/* Clear cmdline */
481	xor r3, r3, r3
482
483	bl SYM (boot_card) /* Call the first C routine */
484
485	twiddle:
486	b twiddle /* We don't expect to return from boot_card but if we do */
487	/* wait here for watchdog to kick us into hard reset */
488
489	#if defined(NEED_LOW_LEVEL_INIT)
490	SDRAM_init:
491	#if defined(MPC5200_BOARD_BRS5L)
492	/* set GPIO_WKUP7 pin low for 66MHz buffering */
493	/* or high for 133MHz registered buffering */
494	LWI r30, 0x80000000
495
496	lwz r29, GPIOWE(r31)
497	or r29,r29,r30 /* set bit 0 in r29/GPIOWE */
498	stw r29,GPIOWE(r31)
499
500	lwz r29, GPIOWOD(r31)
501	andc r29,r29,r30 /* clear bit 0 in r29/GPIOWOD */
502	stw r29,GPIOWOD(r31)
503
504	lwz r29, GPIOWDO(r31)
505	andc r29,r29,r30 /* clear bit 0 in r29/GPIOWDO */
506	stw r29,GPIOWDO(r31)
507
508	lwz r29, GPIOWDD(r31)
509	or r29,r29,r30 /* set bit 0 in r29/GPIOWDD */
510	stw r29,GPIOWDD(r31)
511
512	/* activate MEM_CS1 output */
513	lwz r29, GPIOPCR(r31)
514	or r29,r29,r30 /* set bit 0 in r29/GPIOPCR */
515	stw r29,GPIOPCR(r31)
516
517	#endif
518	LWI r30, 0xC4222600 /* Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x4 */
519	stw r30, CFG1(r31) /* Read CAS latency=0x2, Active2Read delay=0x2, Prec.2active delay=0x2 */
520	/* Refr.2No-Read delay=0x06, Write latency=0x0 */
521
522	LWI r30, 0xCCC70004 /* Burst2Read Prec.delay=0x8, Burst Write delay=0x8 */
523	stw r30, CFG2(r31) /* Burst Read2Write delay=0xB, Burst length=0x7, Read Tap=0x4 */
524
525	#ifdef MPC5200_BOARD_BRS5L
526	LWI r30, 0xD1470000 /* Mode Set enabled, Clock enabled, Auto refresh enabled, Mem. data drv */
527	stw r30, CTRL(r31) /* Refresh counter=0xFFFF */
528
529
530	#else
531	LWI r30, 0xD04F0000 /* Mode Set enabled, Clock enabled, Auto refresh enabled, Mem. data drv */
532	stw r30, CTRL(r31) /* Refresh counter=0xFFFF */
533
534
535	#endif
536	lwz r30, CTRL(r31)
537
538
539	SETBITS r30, r29, CTRL_PRECHARGE /* send two times precharge */
540	stw r30, CTRL(r31)
541
542
543	stw r30, CTRL(r31)
544
545
546
547	lwz r30, CTRL(r31)
548
549
550	SETBITS r30, r29, CTRL_REFRESH /* send two times refresh */
551	stw r30, CTRL(r31)
552
553
554	stw r30, CTRL(r31)
555
556
557
558	LWI r30, 0x008D0000 /* Op.Mode=0x0, Read CAS latency=0x2, Burst length=0x3, Write strobe puls */
559	stw r30, MOD(r31)
560
561
562
563	lwz r30, CTRL(r31) /* Clock enabled, Auto refresh enabled, Mem. data drv. Refresh counter=0xFFFF */
564
565
566	CLRBITS r30, r29, CTRL_BA1
567	stw r30, CTRL(r31)
568
569
570
571	blr
572
573
574	copy_image:
575	mr r27, r28
576	srwi r28, r28, 2
577	mtctr r28
578
579
580	slwi r28, r28, 2
581	sub r27, r27, r28 /* maybe some residual bytes */
582
583
584	copy_image_word:
585	lswi r28, r30, 0x04
586
587	stswi r28, r29, 0x04 /* do word copy ROM -> RAM */
588
589
590	addi r30, r30, 0x04 /* increment source pointer */
591	addi r29, r29, 0x04 /* increment destination pointer */
592
593	bdnz copy_image_word /* decrement ctr and branch if not 0 */
594
595	cmpwi r27, 0x00 /* copy image finished ? */
596	beq copy_image_end;
597	mtctr r27 /* reload counter for residual bytes */
598	copy_image_byte:
599	lswi r28, r30, 0x01
600
601	stswi r28, r29, 0x01 /* do byte copy ROM -> RAM */
602
603
604	addi r30, r30, 0x01 /* increment source pointer */
605	addi r29, r29, 0x01 /* increment destination pointer */
606
607	bdnz copy_image_byte /* decrement ctr and branch if not 0 */
608
609	copy_image_end:
610	blr
611	#endif /* defined(NEED_LOW_LEVEL_INIT) */
612
613	FID_DCache:
614	mflr r26
615
616	bl PPC_HID0_rd
617	TSTBITS r30, r29, HID0_DCE
618	bne FID_DCache_exit /* If data cache is switched of, skip further actions */
619
620	li r29, PPC_D_CACHE /* 16 Kb data cache on 603e */
621	LWI r28, bsp_section_text_start /* Load base address (begin of RAM) */
622
623	FID_DCache_loop_1:
624	lwz r27, 0(r28) /* Load data at address */
625
626	addi r28, r28, PPC_CACHE_ALIGNMENT /* increment cache line address */
627	subi r29, r29, PPC_CACHE_ALIGNMENT /* increment loop counter */
628	cmpwi r29, 0x0
629	bne FID_DCache_loop_1 /* Loop until cache size is reached */
630
631	li r29, PPC_D_CACHE /* 16 Kb data cache on 603e */
632	LWI r28, bsp_section_text_start /* Reload base address (begin of RAM) */
633	xor r27, r27, r27
634	FID_DCache_loop_2:
635
636	dcbf r27, r28 /* Flush and invalidate cache */
637
638	addi r28, r28, PPC_CACHE_ALIGNMENT /* increment cache line address */
639	subi r29, r29, PPC_CACHE_ALIGNMENT /* increment loop counter */
640	cmpwi r29, 0x0
641	bne FID_DCache_loop_2 /* Loop around until cache size is reached */
642
643	bl PPC_HID0_rd /* Read HID0 */
644	CLRBITS r30, r29, HID0_DCE
645	bl PPC_HID0_wr /* Clear DCE */
646
647	FID_DCache_exit:
648	mtlr r26
649	blr
650
651	IDUL_ICache:
652	mflr r26
653
654	bl PPC_HID0_rd
655	TSTBITS r30, r29, HID0_ICE
656	bne IDUL_ICache_exit /* If instruction cache is switched of, skip further actions */
657
658	CLRBITS r30, r29, HID0_ICE
659	bl PPC_HID0_wr /* Disable ICE bit */
660
661	SETBITS r30, r29, HID0_ICFI
662	bl PPC_HID0_wr /* Invalidate instruction cache */
663
664	CLRBITS r30, r29, HID0_ICFI
665	bl PPC_HID0_wr /* Disable cache invalidate */
666
667	CLRBITS r30, r29, HID0_ILOCK
668	bl PPC_HID0_wr /* Disable instruction cache lock */
669
670	IDUL_ICache_exit:
671	mtlr r26
672	blr
673
674
675	TLB_init: /* Initialize translation lookaside buffers (TLBs) */
676	xor r30, r30, r30
677	xor r29, r29, r29
678
679	TLB_init_loop:
680	tlbie r29
681	tlbsync
682	addi r29, r29, 0x1000
683	addi r30, r30, 0x01
684	cmpli 0, 0, r30, 0x0080
685	bne TLB_init_loop
686	blr
687
688	FPU_init:
689	mfmsr r30 /* get content of MSR */
690
691
692	SETBITS r30, r29, MSR_FP
693	mtmsr r30 /* enable FPU and FPU exceptions */
694	sync
695
696	lfd f0, 0(r29)
697	fmr f1, f0
698	fmr f2, f0
699	fmr f3, f0
700	fmr f4, f0
701	fmr f5, f0
702	fmr f6, f0
703	fmr f7, f0
704	fmr f8, f0
705	fmr f9, f0
706	fmr f10, f0
707	fmr f11, f0
708	fmr f12, f0
709	fmr f13, f0
710	fmr f14, f0
711	fmr f15, f0
712	fmr f16, f0
713	fmr f17, f0
714	fmr f18, f0
715	fmr f19, f0
716	fmr f20, f0
717	fmr f21, f0
718	fmr f22, f0
719	fmr f23, f0
720	fmr f24, f0
721	fmr f25, f0
722	fmr f26, f0
723	fmr f27, f0
724	fmr f28, f0
725	fmr f29, f0
726	fmr f30, f0
727	fmr f31, f0
728
729
730	mtfsfi 0, 0 /* initialize bit positons in FPSCR */
731	mtfsfi 1, 0
732	mtfsfi 2, 0
733	mtfsfi 3, 0
734	mtfsfi 4, 0
735	mtfsfi 5, 0
736	mtfsfi 6, 0
737	mtfsfi 7, 0
738
739	blr
740
741	SPRG_init: /* initialize registers */
742	xor r30, r30, r30
743
744	mtspr PPC_XER, r30
745	mtspr PPC_CTR, r30
746	mtspr DSISR, r30
747	mtspr PPC_DAR, r30
748	mtspr PPC_DEC, r30
749	mtspr SDR1, r30
750	mtspr SRR0, r30
751	mtspr SRR1, r30
752	mtspr CSSR0, r30
753	mtspr CSSR1, r30
754	mtspr SPRG0, r30
755	mtspr SPRG1, r30
756	mtspr SPRG2, r30
757	mtspr SPRG3, r30
758	mtspr SPRG4, r30
759	mtspr SPRG5, r30
760	mtspr SPRG6, r30
761	mtspr SPRG7, r30
762	mtspr PPC_EAR, r30
763	mtspr TBWU, r30
764	mtspr TBWL, r30
765	mtspr IBAT0U, r30
766	mtspr IBAT0L, r30
767	mtspr IBAT1U, r30
768	mtspr IBAT1L, r30
769	mtspr IBAT2U, r30
770	mtspr IBAT2L, r30
771	mtspr IBAT3U, r30
772	mtspr IBAT3L, r30
773	mtspr IBAT4U, r30
774	mtspr IBAT4L, r30
775	mtspr IBAT5U, r30
776	mtspr IBAT5L, r30
777	mtspr IBAT6U, r30
778	mtspr IBAT6L, r30
779	mtspr IBAT7U, r30
780	mtspr IBAT7L, r30
781	mtspr DBAT0U, r30
782	mtspr DBAT0L, r30
783	mtspr DBAT1U, r30
784	mtspr DBAT1L, r30
785	mtspr DBAT2U, r30
786	mtspr DBAT2L, r30
787	mtspr DBAT3U, r30
788	mtspr DBAT3L, r30
789	mtspr DBAT4U, r30
790	mtspr DBAT4L, r30
791	mtspr DBAT5U, r30
792	mtspr DBAT5L, r30
793	mtspr DBAT6U, r30
794	mtspr DBAT6L, r30
795	mtspr DBAT7U, r30
796	mtspr DBAT7L, r30
797	mtspr DMISS, r30
798	mtspr DCMP, r30
799	mtspr HASH1, r30
800	mtspr HASH2, r30
801	mtspr IMISS, r30
802	mtspr ICMP, r30
803	mtspr PPC_RPA, r30
804	mtsr PPC_SR0, r30
805	mtsr PPC_SR1, r30
806	mtsr PPC_SR2, r30
807	mtsr PPC_SR3, r30
808	mtsr PPC_SR4, r30
809	mtsr PPC_SR5, r30
810	mtsr PPC_SR6, r30
811	mtsr PPC_SR7, r30
812	mtsr PPC_SR8, r30
813	mtsr PPC_SR9, r30
814	mtsr PPC_SR10, r30
815	mtsr PPC_SR12, r30
816	mtsr PPC_SR13, r30
817	mtsr PPC_SR14, r30
818	mtsr PPC_SR15, r30
819
820
821
822
823
824	blr
825
826	PPC_HID0_rd: /* get HID0 content to r30 */
827
828
829	mfspr r30, HID0
830
831	blr
832
833
834	PPC_HID0_wr: /* put r30 content to HID0 */
835
836
837	mtspr HID0, r30
838
839	blr
840
841	clr_mem:
842	mr r28, r29
843	srwi r29, r29, 2
844	mtctr r29 /* set ctr reg */
845
846
847	slwi r29, r29, 2
848	sub r28, r28, r29 /* maybe some residual bytes */
849	xor r29, r29, r29
850
851
852	clr_mem_word:
853	stswi r29, r30, 0x04 /* store r29 (word) to r30 memory location */
854	addi r30, r30, 0x04 /* increment r30 */
855
856	bdnz clr_mem_word /* dec counter and loop */
857
858
859	cmpwi r28, 0x00 /* clear mem. finished ? */
860	beq clr_mem_end;
861	mtctr r28 /* reload counter for residual bytes */
862	clr_mem_byte:
863	stswi r29, r30, 0x01 /* store r29 (byte) to r30 memory location */
864	addi r30, r30, 0x01 /* update r30 */
865
866	bdnz clr_mem_byte /* dec counter and loop */
867
868	clr_mem_end:
869	blr /* return */
870
871	XLB_init:
872	/* init arbiter and stuff... */
873	LWI r30, 0x8000a06e
874	stw r30, ARBCFG(r31) /* Set ARBCFG */
875
876	LWI r30, 0x000000ff
877	stw r30, ARBMPREN(r31) /* Set ARBMPREN */
878
879	LWI r30, 0x00001234
880	stw r30, ARBMPRIO(r31) /* Set ARBPRIO */
881
882	LWI r30, 0x0000001e
883	stw r30, ARBSNOOP(r31) /* Set ARBSNOOP */
884
885	LWI r30, 4096
886	stw r30, ARBADRTO(r31) /* Set ARBADRTO */
887	stw r30, ARBDATTO(r31) /* Set ARBDATTO */
888
889	blr

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