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start.S @ d4a4811

4.115

Last change on this file since d4a4811 was d4a4811, checked in by Sebastian Huber <sebastian.huber@…>, on 04/19/13 at 12:01:47
bsp/mpc5200: Set SDELAY register
Property mode set to `100644`
File size: 23.7 KB

Rev	Line
[ca680bc5]	1	/===============================================================\
	2	\| Project: RTEMS generic MPC5200 BSP \|
	3	+-----------------------------------------------------------------+
	4	\| Partially based on the code references which are named below. \|
	5	\| Adaptions, modifications, enhancements and any recent parts of \|
	6	\| the code are: \|
	7	\| Copyright (c) 2005 \|
	8	\| Embedded Brains GmbH \|
	9	\| Obere Lagerstr. 30 \|
	10	\| D-82178 Puchheim \|
	11	\| Germany \|
	12	\| rtems@embedded-brains.de \|
	13	+-----------------------------------------------------------------+
	14	\| The license and distribution terms for this file may be \|
	15	\| found in the file LICENSE in this distribution or at \|
	16	\| \|
	17	\| http://www.rtems.com/license/LICENSE. \|
	18	\| \|
	19	+-----------------------------------------------------------------+
	20	\| this file contains the startup assembly code \|
	21	\===============================================================/
	22	/***********************************************************************/
	23	/* */
	24	/* Module: start.S */
	25	/* Date: 07/17/2003 */
	26	/* Purpose: RTEMS MPC5x00 CPU assembly startup */
	27	/* */
	28	/---------------------------------------------------------------------/
	29	/* */
	30	/* Description: This file contains the assembler portion of MPC5x00 */
	31	/* startup code */
	32	/* */
	33	/---------------------------------------------------------------------/
	34	/* */
	35	/* Code */
	36	/* References: startup code for Motorola PQII ADS board */
	37	/* Module: start.S */
	38	/* Project: RTEMS 4.6.0pre1 / MCF8260ads BSP */
	39	/* Version 1.2 */
	40	/* Date: 04/18/2002 */
	41	/* */
	42	/* Author(s) / Copyright(s): */
	43	/* */
	44	/* Modified for the Motorola PQII ADS board by */
	45	/* Andy Dachs <a.dachs@sstl.co.uk> 23-11-00. */
	46	/* Surrey Satellite Technology Limited */
	47	/* */
	48	/* I have a proprietary bootloader programmed into the flash */
	49	/* on the board which initialises the SDRAM prior to calling */
	50	/* this function. */
	51	/* */
	52	/* This file is based on the one by Jay Monkman (jmonkman@fracsa.com)*/
	53	/* which in turn was based on the dlentry.s file for the Papyrus BSP,*/
	54	/* written by: */
	55	/* */
	56	/* Author: Andrew Bray <andy@i-cubed.co.uk> */
	57	/* */
	58	/* COPYRIGHT (c) 1995 by i-cubed ltd. */
	59	/* */
	60	/* To anyone who acknowledges that this file is provided "AS IS" */
	61	/* without any express or implied warranty: */
	62	/* permission to use, copy, modify, and distribute this file */
	63	/* for any purpose is hereby granted without fee, provided that */
	64	/* the above copyright notice and this notice appears in all */
	65	/* copies, and that the name of i-cubed limited not be used in */
	66	/* advertising or publicity pertaining to distribution of the */
	67	/* software without specific, written prior permission. */
	68	/* i-cubed limited makes no representations about the suitability */
	69	/* of this software for any purpose. */
	70	/* */
	71	/---------------------------------------------------------------------/
	72	/* */
	73	/* Partially based on the code references which are named above. */
	74	/* Adaptions, modifications, enhancements and any recent parts of */
	75	/* the code are under the right of */
	76	/* */
[1af911b8]	77	/* IPR Engineering, Dachauer StraÃe 38, D-80335 MÃŒnchen */
[ca680bc5]	78	/* Copyright(C) 2003 */
	79	/* */
	80	/---------------------------------------------------------------------/
	81	/* */
	82	/* IPR Engineering makes no representation or warranties with */
	83	/* respect to the performance of this computer program, and */
	84	/* specifically disclaims any responsibility for any damages, */
	85	/* special or consequential, connected with the use of this program. */
	86	/* */
	87	/---------------------------------------------------------------------/
	88	/* */
	89	/* Version history: 1.0 */
	90	/* */
	91	/***********************************************************************/
[820d1ab0]	92
[ca680bc5]	93	#include <rtems/powerpc/cache.h>
[82bd8d9d]	94
	95	#include <bsp.h>
	96	#include <bsp/mpc5200.h>
[ca680bc5]	97
	98	/* Some register offsets of MPC5x00 memory map registers */
	99	.set CS0STR, 0x04
	100	.set CS0STP, 0x08
	101	.set CS1STR, 0x0C
	102	.set CS1STP, 0x10
	103	.set SDRAMCS0, 0x34
	104	.set SDRAMCS1, 0x38
	105	.set BOOTSTR, 0x4C
	106	.set BOOTSTP, 0x50
[efdfd48]	107	.set ADREN, 0x54
[ca680bc5]	108	.set CSSR0, 0x58 /* Critical Interrupt SSR0 (603le only) */
	109	.set CSSR1, 0x59 /* Critical Interrupt SSR1 (603le only) */
	110	.set CFG, 0x20C
	111	.set CSBOOTROM, 0x300
	112	.set CSCONTROL, 0x318
	113	.set CS1CONF, 0x304
	114
	115
	116	/* Register offsets of MPC5x00 SDRAM memory controller registers */
	117	.set MOD, 0x100
	118	.set CTRL, 0x104
	119	.set CFG1, 0x108
	120	.set CFG2, 0x10C
	121	.set ADRSEL, 0x110
[d4a4811]	122	.set SDELAY, 0x190
[ca680bc5]	123
	124	/* Register offsets of MPC5x00 GPIO registers needed */
	125	.set GPIOPCR, 0xb00
[efdfd48]	126	.set GPIOWE, 0xc00
[ca680bc5]	127	.set GPIOWOD, 0xc04
	128	.set GPIOWDD, 0xc08
	129	.set GPIOWDO, 0xc0c
	130
	131	.set GPIOSEN, 0xb04
	132	.set GPIOSDD, 0xb0c
	133	.set GPIOSDO, 0xb10
	134
	135	/* Register offsets of MPC5x00 Arbiter registers */
	136	.set ARBCFG, 0x1f40
[be04e62]	137	.set ARBADRTO, 0x1f58
	138	.set ARBDATTO, 0x1f5c
[ca680bc5]	139	.set ARBMPREN, 0x1f64
	140	.set ARBMPRIO, 0x1f68
	141	.set ARBSNOOP, 0x1f70
	142
	143	/* Some bit encodings for MGT5100 registers */
[6c094da]	144	.set ADREN_BOOT_EN, (1 << (31 - 6))
	145	.set ADREN_CS0_EN, (1 << (31 - 15))
	146	.set ADREN_CS1_EN, (1 << (31 - 14))
	147	.set ADREN_WSE, (1 << (31 - 31))
[ca680bc5]	148
	149	.set CTRL_PRECHARGE, (1<<1)
	150	.set CTRL_REFRESH, (1<<2)
	151	.set CTRL_BA1, (1<<31)
	152
	153	.set CSCONF_CE, (1<<12)
	154
	155	/* Some fixed values for MPC5x00 registers */
	156	.set CSCONTROL_VAL, 0x91000000
[e79e904]	157
	158	/*
	159	* The DDR_MODE bit is a read-only status and should be written as 0.
	160	*
	161	* XLB_CLK = FVCO / 4
	162	* IPB_CLK = XLB_CLK / 2
	163	* PCI_CLK = IPB_CLK
	164	*/
[ca680bc5]	165	.set CFG_VAL, 0x00000100
	166
	167	.extern boot_card
	168
[25ed11d0]	169	.section ".vectors", "ax"
	170	bl start
	171	.rep 63
	172	.long 0x04000400
	173	.endr
	174	__vec2: b __vec2
	175	.rep 63
	176	.long 0x04000400
	177	.endr
	178	__vec3: b __vec3
	179	.rep 63
	180	.long 0x04000400
	181	.endr
	182	__vec4: b __vec4
	183	.rep 63
	184	.long 0x04000400
	185	.endr
	186	__vec5: b __vec5
	187	.rep 63
	188	.long 0x04000400
	189	.endr
	190	__vec6: b __vec6
	191	.rep 63
	192	.long 0x04000400
	193	.endr
	194	__vec7: b __vec7
	195	.rep 63
	196	.long 0x04000400
	197	.endr
	198	__vec8: b __vec8
	199	.rep 63
	200	.long 0x04000400
	201	.endr
	202	__vec9: b __vec9
	203	.rep 63
	204	.long 0x04000400
	205	.endr
	206	__veca: b __veca
	207	.rep 63
	208	.long 0x04000400
	209	.endr
	210	__vecb: b __vecb
	211	.rep 63
	212	.long 0x04000400
	213	.endr
	214	__vecc: b __vecc
	215	.rep 63
	216	.long 0x04000400
	217	.endr
	218	__vecd: b __vecd
	219	.rep 63
	220	.long 0x04000400
	221	.endr
	222	__vece: b __vece
	223	.rep 63
	224	.long 0x04000400
	225	.endr
	226	__vecf: b __vecf
	227	.rep 63+1024
	228	.long 0x04000400
	229	.endr
	230
[efdfd48]	231	.section ".entry"
[ca680bc5]	232	PUBLIC_VAR (start)
	233	start:
	234	/* 1st: initialization work (common for RAM/ROM startup) */
[b4fdfc6]	235	mfmsr r30
[ca680bc5]	236	SETBITS r30, r29, MSR_ME\|MSR_RI
	237	CLRBITS r30, r29, MSR_EE
	238	mtmsr r30 /* Set RI/ME, Clr EE in MSR */
[efdfd48]	239
[5cace18]	240	#ifdef HAS_UBOOT
	241	mr r14, r3
	242	#endif /* HAS_UBOOT */
[ca680bc5]	243
	244	#if defined(NEED_LOW_LEVEL_INIT)
	245	/* initialize the MBAR (common RAM/ROM startup) */
	246	LWI r31, MBAR_RESET
	247	LWI r29, MBAR
	248	rlwinm r30, r29,16,16,31
[efdfd48]	249	stw r30, 0(r31) /* Set the MBAR */
	250	#endif
[ca680bc5]	251
	252	LWI r31, MBAR /* set r31 to current MBAR */
	253	/* init GPIOPCR */
	254	lwz r29,GPIOPCR(r31)
[1f4db180]	255	LWI r30, BSP_GPIOPCR_INITMASK
[ca680bc5]	256	not r30,r30
	257	and r29,r29,r30
[1f4db180]	258	LWI r30, BSP_GPIOPCR_INITVAL
[ca680bc5]	259	or r29,r29,r30
	260	stw r29, GPIOPCR(r31)
[efdfd48]	261
	262	/* further initialization work (common RAM/ROM startup) */
	263	bl TLB_init /* Initialize TLBs */
	264
	265
[ca680bc5]	266	bl FID_DCache /* Flush, inhibit and disable data cache */
[efdfd48]	267
	268
[ca680bc5]	269	bl IDUL_ICache /* Inhibit, disable and unlock instruction cache */
[efdfd48]	270
	271
	272	bl FPU_init /* Initialize FPU */
	273
	274
[ca680bc5]	275	#if defined(NEED_LOW_LEVEL_INIT)
[efdfd48]	276	bl SPRG_init /* Initialize special purpose registers */
	277	#endif
	278
[ca680bc5]	279	#if defined(NEED_LOW_LEVEL_INIT)
	280	/* detect RAM/ROM startup (common for RAM/ROM startup) */
[82bd8d9d]	281	LWI r20, bsp_rom_start /* set the relocation offset */
[efdfd48]	282
	283
[ca680bc5]	284	LWI r30, CFG_VAL /* get CFG register content */
[e79e904]	285	lwz r30, CFG(r31) /* set CFG register */
[efdfd48]	286
	287
[ca680bc5]	288
	289	lwz r30, ADREN(r31) /* get content of ADREN */
[efdfd48]	290
	291
	292
[ca680bc5]	293	TSTBITS r30, r29, ADREN_BOOT_EN
	294	bne skip_ROM_start /* If BOOT_ROM is not enabled, skip further initialization */
	295
[efdfd48]	296	/* do some board dependent configuration (unique for ROM startup) */
[ca680bc5]	297	LWI r30, CSCONTROL_VAL /* get CSCONTROL register content */
	298	stw r30, CSCONTROL(r31) /* enable internal/external bus error and master for CS */
[efdfd48]	299
	300
[dbe6aae7]	301	#if defined(MPC5200_BOARD_BRS5L)
	302	#define CSBOOTROM_VAL 0x0101D910
	303	#endif
[ca680bc5]	304
[dbe6aae7]	305	#ifdef CSBOOTROM_VAL
[ca680bc5]	306	LWI r30, CSBOOTROM_VAL
	307	stw r30, CSBOOTROM(r31) /* Set CSBOOTROM */
[dbe6aae7]	308	#endif
[ca680bc5]	309
	310	/* FIXME: map BOOT ROM into final location with CS0 registers */
[82bd8d9d]	311	LWI r30, bsp_rom_start
[ca680bc5]	312	rlwinm r30, r30,17,15,31
[efdfd48]	313	stw r30, CS0STR(r31) /* Set CS0STR */
	314
[25ed11d0]	315	LWI r30, bsp_rom_end - 1
[efdfd48]	316
[ca680bc5]	317	rlwinm r30, r30,17,15,31
	318	stw r30, CS0STP(r31) /* Set CS0STP */
[efdfd48]	319
[ca680bc5]	320	lwz r30, ADREN(r31) /* get content of ADREN */
[efdfd48]	321	SETBITS r30, r29, ADREN_CS0_EN
[ca680bc5]	322	stw r30, ADREN(r31) /* enable CS0 mapping */
	323	isync
	324	/* jump to same code in final BOOT ROM location */
	325	LWI r30, reloc_in_CS0
[82bd8d9d]	326	LWI r29, bsp_ram_start
[ca680bc5]	327	sub r30,r30,r29
[82bd8d9d]	328	LWI r29, bsp_rom_start
[ca680bc5]	329	add r30,r30,r29
	330	mtctr r30
	331	bctr
[efdfd48]	332
	333	reloc_in_CS0:
[ca680bc5]	334	/* disable CSBOOT (or map it to CS0 range) */
	335	lwz r30, ADREN(r31) /* get content of ADREN */
[efdfd48]	336	CLRBITS r30, r29, ADREN_BOOT_EN
[ca680bc5]	337	stw r30, ADREN(r31) /* disable BOOT mapping */
[efdfd48]	338
[ca680bc5]	339	/* init SDRAM */
[82bd8d9d]	340	LWI r30, bsp_ram_start
	341	ori r30, r30, 0x1a /* size code: bank is 128MByte */
	342	stw r30, SDRAMCS0(r31) /* Set SDRAMCS0 */
[ca680bc5]	343
[82bd8d9d]	344	LWI r30, bsp_ram_size
	345	srawi r30, r30, 1
	346	ori r30, r30, 0x1a /* size code: bank is 128MByte */
[ca680bc5]	347	stw r30, SDRAMCS1(r31) /* Set SDRAMCS1 */
[efdfd48]	348
[ca680bc5]	349	bl SDRAM_init /* Initialize SDRAM controller */
	350
[25ed11d0]	351	bl XLB_init
[ca680bc5]	352	/* copy .text section from ROM to RAM location (unique for ROM startup) */
[82bd8d9d]	353	LA r30, bsp_section_text_start /* get start address of text section in RAM */
[efdfd48]	354
	355
[ca680bc5]	356	add r30, r20, r30 /* get start address of text section in ROM (add reloc offset) */
[efdfd48]	357
	358
[82bd8d9d]	359	LA r29, bsp_section_text_start /* get start address of text section in RAM */
[efdfd48]	360
[ca680bc5]	361
[82bd8d9d]	362	LA r28, bsp_section_text_size /* get size of RAM image */
[efdfd48]	363
	364
[ca680bc5]	365	bl copy_image /* copy text section from ROM to RAM location */
[efdfd48]	366
[ca680bc5]	367
	368	/* copy .data section from ROM to RAM location (unique for ROM startup) */
[82bd8d9d]	369	LA r30, bsp_section_data_start /* get start address of data section in RAM */
[efdfd48]	370
	371
[ca680bc5]	372	add r30, r20, r30 /* get start address of data section in ROM (add reloc offset) */
[efdfd48]	373
	374
[82bd8d9d]	375	LA r29, bsp_section_data_start /* get start address of data section in RAM */
[efdfd48]	376
	377
[82bd8d9d]	378	LA r28, bsp_section_data_size /* get size of RAM image */
[efdfd48]	379
	380
[ca680bc5]	381	bl copy_image /* copy initialized data section from ROM to RAM location */
[efdfd48]	382
[ca680bc5]	383
	384	LA r29, remap_rom /* get compile time address of label */
	385	mtlr r29
[efdfd48]	386
[ca680bc5]	387	blrl /* now further execution RAM */
	388
[efdfd48]	389	remap_rom:
[ca680bc5]	390	/* remap BOOT ROM to CS0 (common for RAM/ROM startup) */
	391	lwz r30, CSBOOTROM(r31) /* get content of CSBOOTROM */
[efdfd48]	392
	393
	394
	395	CLRBITS r30, r29, CSCONF_CE
	396	stw r30, CSBOOTROM(r31) /* disable BOOT CS */
	397
	398
[ca680bc5]	399
	400	lwz r30, ADREN(r31) /* get content of ADREN */
[efdfd48]	401
	402
[ca680bc5]	403
	404	mr r29, r30 /* move content of r30 to r29 */
[efdfd48]	405
	406
[ca680bc5]	407	LWI r30, ADREN_BOOT_EN /* mask ADREN_BOOT_EN */
[efdfd48]	408	andc r29,r29,r30
	409
	410
[ca680bc5]	411	LWI r30, ADREN_CS0_EN /* unmask ADREN_CS0_EN */
[efdfd48]	412	or r29,r29,r30
	413
	414
[ca680bc5]	415	stw r29,ADREN(r31) /* Simultaneous enable CS0 and disable BOOT address space */
[efdfd48]	416
	417
	418
[ca680bc5]	419	lwz r30, CSBOOTROM(r31) /* get content of CSBOOTROM */
[efdfd48]	420
	421
	422
	423	SETBITS r30, r29, CSCONF_CE
	424	stw r30, CSBOOTROM(r31) /* disable BOOT CS */
	425
	426
[ca680bc5]	427
	428	skip_ROM_start:
	429	/* configure external DPRAM CS1 */
[82bd8d9d]	430	LWI r30, 0xFFFFFB10
	431	stw r30, CS1CONF(r31)
[ca680bc5]	432
	433	/* map external DPRAM (CS1) */
[82bd8d9d]	434	LWI r30, bsp_dpram_start
	435	srawi r30, r30, 16
	436	stw r30, CS1STR(r31)
[ca680bc5]	437
[82bd8d9d]	438	LWI r30, bsp_dpram_end
	439	srawi r30, r30, 16
	440	stw r30, CS1STP(r31)
[ca680bc5]	441
	442	lwz r30, ADREN(r31) /* get content of ADREN */
[efdfd48]	443
[ca680bc5]	444	LWI r29, ADREN_CS1_EN /* unmask ADREN_CS1_EN */
[efdfd48]	445	or r30, r30,r29
	446
[82bd8d9d]	447	stw r30, ADREN(r31) /* enable CS1 */
[ca680bc5]	448
	449	/* clear entire on chip SRAM (unique for ROM startup) */
[c9b005a9]	450	lis r30, (MBAR+ONCHIP_SRAM_OFFSET)@h /* get start address of onchip SRAM */
[82bd8d9d]	451	ori r30, r30,(MBAR+ONCHIP_SRAM_OFFSET)@l
[b4fdfc6]	452	LWI r29, ONCHIP_SRAM_SIZE /* get size of onchip SRAM */
[efdfd48]	453
[b4fdfc6]	454	bl clr_mem /* Clear onchip SRAM */
[efdfd48]	455
[25ed11d0]	456	#else /* defined(NEED_LOW_LEVEL_INIT) */
	457	bl XLB_init
[1f4db180]	458	#endif /* defined(NEED_LOW_LEVEL_INIT) */
[ca680bc5]	459	/* clear .bss section (unique for ROM startup) */
[82bd8d9d]	460	LWI r30, bsp_section_bss_start /* get start address of bss section */
[b4fdfc6]	461	LWI r29, bsp_section_bss_size /* get size of bss section */
[efdfd48]	462
[ca680bc5]	463
[b4fdfc6]	464	bl clr_mem /* Clear the bss section */
[efdfd48]	465
[5cace18]	466	#ifdef HAS_UBOOT
	467	mr r3, r14
	468	bl bsp_uboot_copy_board_info
	469	#endif /* HAS_UBOOT */
[ca680bc5]	470
	471	/* set stack pointer (common for RAM/ROM startup) */
[efdfd48]	472	LA r1, bsp_section_text_start
[b4fdfc6]	473	addi r1, r1, -0x10 /* Set up stack pointer = beginning of text section - 0x10 */
	474	/* tag TOS with a NULL pointer (termination mark for stack dump) */
	475	li r0, 0
	476	stw r0, 0(r1)
[82bd8d9d]	477
	478	bl __eabi /* Set up EABI and SYSV environment */
[efdfd48]	479
[ca680bc5]	480	/* enable dynamic power management(common for RAM/ROM startup) */
	481	bl PPC_HID0_rd /* Get the content of HID0 */
[efdfd48]	482
	483	SETBITS r30, r29, HID0_DPM
[ca680bc5]	484	bl PPC_HID0_wr /* Set DPM in HID0 */
	485
	486	/* clear arguments and do further init. in C (common for RAM/ROM startup) */
[aa058378]	487
[b4fdfc6]	488	/* Clear cmdline */
	489	xor r3, r3, r3
[efdfd48]	490
[b4fdfc6]	491	bl SYM (boot_card) /* Call the first C routine */
[0a029a5]	492
[efdfd48]	493	twiddle:
[ca680bc5]	494	b twiddle /* We don't expect to return from boot_card but if we do */
	495	/* wait here for watchdog to kick us into hard reset */
	496
[1f4db180]	497	#if defined(NEED_LOW_LEVEL_INIT)
[efdfd48]	498	SDRAM_init:
[47fb2fe]	499	#if defined(MPC5200_BOARD_BRS5L)
[ca680bc5]	500	/* set GPIO_WKUP7 pin low for 66MHz buffering */
	501	/* or high for 133MHz registered buffering */
	502	LWI r30, 0x80000000
[efdfd48]	503
[ca680bc5]	504	lwz r29, GPIOWE(r31)
	505	or r29,r29,r30 /* set bit 0 in r29/GPIOWE */
	506	stw r29,GPIOWE(r31)
[efdfd48]	507
[ca680bc5]	508	lwz r29, GPIOWOD(r31)
	509	andc r29,r29,r30 /* clear bit 0 in r29/GPIOWOD */
	510	stw r29,GPIOWOD(r31)
	511
	512	lwz r29, GPIOWDO(r31)
	513	andc r29,r29,r30 /* clear bit 0 in r29/GPIOWDO */
	514	stw r29,GPIOWDO(r31)
[efdfd48]	515
[ca680bc5]	516	lwz r29, GPIOWDD(r31)
	517	or r29,r29,r30 /* set bit 0 in r29/GPIOWDD */
	518	stw r29,GPIOWDD(r31)
	519
[b4fdfc6]	520	/* activate MEM_CS1 output */
[ca680bc5]	521	lwz r29, GPIOPCR(r31)
	522	or r29,r29,r30 /* set bit 0 in r29/GPIOPCR */
	523	stw r29,GPIOPCR(r31)
	524
	525	#endif
[d4a4811]	526
	527	#define SDELAY_VAL 0x00000004
	528
	529	LWI r3, SDELAY_VAL
	530	stw r3, SDELAY(r31)
	531
[456d9b2]	532	LWI r30, 0xC4222600 /* Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x4 */
	533	stw r30, CFG1(r31) /* Read CAS latency=0x2, Active2Read delay=0x2, Prec.2active delay=0x2 */
[ca680bc5]	534	/* Refr.2No-Read delay=0x06, Write latency=0x0 */
[456d9b2]	535
	536	LWI r30, 0xCCC70004 /* Burst2Read Prec.delay=0x8, Burst Write delay=0x8 */
[ca680bc5]	537	stw r30, CFG2(r31) /* Burst Read2Write delay=0xB, Burst length=0x7, Read Tap=0x4 */
[efdfd48]	538
[47fb2fe]	539	#ifdef MPC5200_BOARD_BRS5L
[ca680bc5]	540	LWI r30, 0xD1470000 /* Mode Set enabled, Clock enabled, Auto refresh enabled, Mem. data drv */
	541	stw r30, CTRL(r31) /* Refresh counter=0xFFFF */
[efdfd48]	542
	543
[ca680bc5]	544	#else
	545	LWI r30, 0xD04F0000 /* Mode Set enabled, Clock enabled, Auto refresh enabled, Mem. data drv */
	546	stw r30, CTRL(r31) /* Refresh counter=0xFFFF */
[efdfd48]	547
	548
	549	#endif
	550	lwz r30, CTRL(r31)
	551
[ca680bc5]	552
	553	SETBITS r30, r29, CTRL_PRECHARGE /* send two times precharge */
	554	stw r30, CTRL(r31)
[efdfd48]	555
	556
[ca680bc5]	557	stw r30, CTRL(r31)
[efdfd48]	558
	559
	560
[ca680bc5]	561	lwz r30, CTRL(r31)
[efdfd48]	562
	563
[ca680bc5]	564	SETBITS r30, r29, CTRL_REFRESH /* send two times refresh */
	565	stw r30, CTRL(r31)
[efdfd48]	566
	567
[ca680bc5]	568	stw r30, CTRL(r31)
[efdfd48]	569
	570
	571
[ca680bc5]	572	LWI r30, 0x008D0000 /* Op.Mode=0x0, Read CAS latency=0x2, Burst length=0x3, Write strobe puls */
[efdfd48]	573	stw r30, MOD(r31)
	574
	575
	576
	577	lwz r30, CTRL(r31) /* Clock enabled, Auto refresh enabled, Mem. data drv. Refresh counter=0xFFFF */
	578
[ca680bc5]	579
	580	CLRBITS r30, r29, CTRL_BA1
	581	stw r30, CTRL(r31)
[efdfd48]	582
	583
	584
[ca680bc5]	585	blr
	586
	587
	588	copy_image:
	589	mr r27, r28
	590	srwi r28, r28, 2
	591	mtctr r28
[efdfd48]	592
	593
[ca680bc5]	594	slwi r28, r28, 2
	595	sub r27, r27, r28 /* maybe some residual bytes */
[efdfd48]	596
	597
[ca680bc5]	598	copy_image_word:
	599	lswi r28, r30, 0x04
[efdfd48]	600
[ca680bc5]	601	stswi r28, r29, 0x04 /* do word copy ROM -> RAM */
[efdfd48]	602
[ca680bc5]	603
	604	addi r30, r30, 0x04 /* increment source pointer */
	605	addi r29, r29, 0x04 /* increment destination pointer */
[efdfd48]	606
[ca680bc5]	607	bdnz copy_image_word /* decrement ctr and branch if not 0 */
	608
	609	cmpwi r27, 0x00 /* copy image finished ? */
	610	beq copy_image_end;
	611	mtctr r27 /* reload counter for residual bytes */
	612	copy_image_byte:
	613	lswi r28, r30, 0x01
[efdfd48]	614
[ca680bc5]	615	stswi r28, r29, 0x01 /* do byte copy ROM -> RAM */
[efdfd48]	616
	617
[ca680bc5]	618	addi r30, r30, 0x01 /* increment source pointer */
	619	addi r29, r29, 0x01 /* increment destination pointer */
[efdfd48]	620
[ca680bc5]	621	bdnz copy_image_byte /* decrement ctr and branch if not 0 */
[efdfd48]	622
[ca680bc5]	623	copy_image_end:
	624	blr
[1f4db180]	625	#endif /* defined(NEED_LOW_LEVEL_INIT) */
[ca680bc5]	626
	627	FID_DCache:
[efdfd48]	628	mflr r26
	629
[b4fdfc6]	630	bl PPC_HID0_rd
	631	TSTBITS r30, r29, HID0_DCE
	632	bne FID_DCache_exit /* If data cache is switched of, skip further actions */
[ca680bc5]	633
	634	li r29, PPC_D_CACHE /* 16 Kb data cache on 603e */
[82bd8d9d]	635	LWI r28, bsp_section_text_start /* Load base address (begin of RAM) */
[ca680bc5]	636
	637	FID_DCache_loop_1:
[b4fdfc6]	638	lwz r27, 0(r28) /* Load data at address */
[efdfd48]	639
[b4fdfc6]	640	addi r28, r28, PPC_CACHE_ALIGNMENT /* increment cache line address */
	641	subi r29, r29, PPC_CACHE_ALIGNMENT /* increment loop counter */
	642	cmpwi r29, 0x0
	643	bne FID_DCache_loop_1 /* Loop until cache size is reached */
[ca680bc5]	644
	645	li r29, PPC_D_CACHE /* 16 Kb data cache on 603e */
[82bd8d9d]	646	LWI r28, bsp_section_text_start /* Reload base address (begin of RAM) */
[ca680bc5]	647	xor r27, r27, r27
	648	FID_DCache_loop_2:
[efdfd48]	649
[ca680bc5]	650	dcbf r27, r28 /* Flush and invalidate cache */
[efdfd48]	651
[b4fdfc6]	652	addi r28, r28, PPC_CACHE_ALIGNMENT /* increment cache line address */
[efdfd48]	653	subi r29, r29, PPC_CACHE_ALIGNMENT /* increment loop counter */
[ca680bc5]	654	cmpwi r29, 0x0
[b4fdfc6]	655	bne FID_DCache_loop_2 /* Loop around until cache size is reached */
[ca680bc5]	656
[b4fdfc6]	657	bl PPC_HID0_rd /* Read HID0 */
	658	CLRBITS r30, r29, HID0_DCE
	659	bl PPC_HID0_wr /* Clear DCE */
[ca680bc5]	660
	661	FID_DCache_exit:
	662	mtlr r26
	663	blr
	664
	665	IDUL_ICache:
	666	mflr r26
[efdfd48]	667
[b4fdfc6]	668	bl PPC_HID0_rd
	669	TSTBITS r30, r29, HID0_ICE
	670	bne IDUL_ICache_exit /* If instruction cache is switched of, skip further actions */
[ca680bc5]	671
[efdfd48]	672	CLRBITS r30, r29, HID0_ICE
[b4fdfc6]	673	bl PPC_HID0_wr /* Disable ICE bit */
[ca680bc5]	674
[efdfd48]	675	SETBITS r30, r29, HID0_ICFI
[b4fdfc6]	676	bl PPC_HID0_wr /* Invalidate instruction cache */
[efdfd48]	677
[b4fdfc6]	678	CLRBITS r30, r29, HID0_ICFI
	679	bl PPC_HID0_wr /* Disable cache invalidate */
[efdfd48]	680
[b4fdfc6]	681	CLRBITS r30, r29, HID0_ILOCK
	682	bl PPC_HID0_wr /* Disable instruction cache lock */
[ca680bc5]	683
	684	IDUL_ICache_exit:
	685	mtlr r26
	686	blr
[efdfd48]	687
	688
[ca680bc5]	689	TLB_init: /* Initialize translation lookaside buffers (TLBs) */
	690	xor r30, r30, r30
[efdfd48]	691	xor r29, r29, r29
	692
	693	TLB_init_loop:
[ca680bc5]	694	tlbie r29
	695	tlbsync
	696	addi r29, r29, 0x1000
	697	addi r30, r30, 0x01
	698	cmpli 0, 0, r30, 0x0080
	699	bne TLB_init_loop
	700	blr
	701
	702	FPU_init:
	703	mfmsr r30 /* get content of MSR */
[efdfd48]	704
	705
[ca680bc5]	706	SETBITS r30, r29, MSR_FP
	707	mtmsr r30 /* enable FPU and FPU exceptions */
[c5a6e617]	708	sync
[efdfd48]	709
[ca680bc5]	710	lfd f0, 0(r29)
	711	fmr f1, f0
	712	fmr f2, f0
	713	fmr f3, f0
	714	fmr f4, f0
	715	fmr f5, f0
	716	fmr f6, f0
	717	fmr f7, f0
	718	fmr f8, f0
	719	fmr f9, f0
	720	fmr f10, f0
	721	fmr f11, f0
	722	fmr f12, f0
	723	fmr f13, f0
	724	fmr f14, f0
	725	fmr f15, f0
	726	fmr f16, f0
	727	fmr f17, f0
	728	fmr f18, f0
	729	fmr f19, f0
	730	fmr f20, f0
	731	fmr f21, f0
	732	fmr f22, f0
	733	fmr f23, f0
	734	fmr f24, f0
	735	fmr f25, f0
	736	fmr f26, f0
	737	fmr f27, f0
	738	fmr f28, f0
	739	fmr f29, f0
	740	fmr f30, f0
	741	fmr f31, f0
[efdfd48]	742
	743
[ca680bc5]	744	mtfsfi 0, 0 /* initialize bit positons in FPSCR */
	745	mtfsfi 1, 0
	746	mtfsfi 2, 0
	747	mtfsfi 3, 0
	748	mtfsfi 4, 0
	749	mtfsfi 5, 0
	750	mtfsfi 6, 0
	751	mtfsfi 7, 0
[efdfd48]	752
[ca680bc5]	753	blr
	754
	755	SPRG_init: /* initialize registers */
	756	xor r30, r30, r30
[efdfd48]	757
[3143f31]	758	mtspr PPC_XER, r30
	759	mtspr PPC_CTR, r30
[ca680bc5]	760	mtspr DSISR, r30
[3143f31]	761	mtspr PPC_DAR, r30
	762	mtspr PPC_DEC, r30
[ca680bc5]	763	mtspr SDR1, r30
	764	mtspr SRR0, r30
	765	mtspr SRR1, r30
	766	mtspr CSSR0, r30
	767	mtspr CSSR1, r30
	768	mtspr SPRG0, r30
	769	mtspr SPRG1, r30
	770	mtspr SPRG2, r30
[efdfd48]	771	mtspr SPRG3, r30
[ca680bc5]	772	mtspr SPRG4, r30
	773	mtspr SPRG5, r30
	774	mtspr SPRG6, r30
	775	mtspr SPRG7, r30
[3143f31]	776	mtspr PPC_EAR, r30
[ca680bc5]	777	mtspr TBWU, r30
	778	mtspr TBWL, r30
	779	mtspr IBAT0U, r30
	780	mtspr IBAT0L, r30
	781	mtspr IBAT1U, r30
	782	mtspr IBAT1L, r30
	783	mtspr IBAT2U, r30
	784	mtspr IBAT2L, r30
	785	mtspr IBAT3U, r30
	786	mtspr IBAT3L, r30
	787	mtspr IBAT4U, r30
	788	mtspr IBAT4L, r30
	789	mtspr IBAT5U, r30
	790	mtspr IBAT5L, r30
	791	mtspr IBAT6U, r30
	792	mtspr IBAT6L, r30
	793	mtspr IBAT7U, r30
	794	mtspr IBAT7L, r30
	795	mtspr DBAT0U, r30
	796	mtspr DBAT0L, r30
	797	mtspr DBAT1U, r30
	798	mtspr DBAT1L, r30
	799	mtspr DBAT2U, r30
	800	mtspr DBAT2L, r30
	801	mtspr DBAT3U, r30
	802	mtspr DBAT3L, r30
	803	mtspr DBAT4U, r30
	804	mtspr DBAT4L, r30
	805	mtspr DBAT5U, r30
	806	mtspr DBAT5L, r30
	807	mtspr DBAT6U, r30
	808	mtspr DBAT6L, r30
	809	mtspr DBAT7U, r30
	810	mtspr DBAT7L, r30
	811	mtspr DMISS, r30
	812	mtspr DCMP, r30
	813	mtspr HASH1, r30
	814	mtspr HASH2, r30
	815	mtspr IMISS, r30
	816	mtspr ICMP, r30
[3143f31]	817	mtspr PPC_RPA, r30
[2d108f8]	818	mtsr PPC_SR0, r30
	819	mtsr PPC_SR1, r30
	820	mtsr PPC_SR2, r30
	821	mtsr PPC_SR3, r30
	822	mtsr PPC_SR4, r30
	823	mtsr PPC_SR5, r30
	824	mtsr PPC_SR6, r30
	825	mtsr PPC_SR7, r30
	826	mtsr PPC_SR8, r30
	827	mtsr PPC_SR9, r30
	828	mtsr PPC_SR10, r30
	829	mtsr PPC_SR12, r30
	830	mtsr PPC_SR13, r30
	831	mtsr PPC_SR14, r30
	832	mtsr PPC_SR15, r30
[efdfd48]	833
	834
	835
	836
	837
[ca680bc5]	838	blr
	839
	840	PPC_HID0_rd: /* get HID0 content to r30 */
[efdfd48]	841
	842
[b4fdfc6]	843	mfspr r30, HID0
[efdfd48]	844
[b4fdfc6]	845	blr
[ca680bc5]	846
	847
	848	PPC_HID0_wr: /* put r30 content to HID0 */
[efdfd48]	849
	850
[b4fdfc6]	851	mtspr HID0, r30
[efdfd48]	852
[b4fdfc6]	853	blr
[ca680bc5]	854
	855	clr_mem:
[efdfd48]	856	mr r28, r29
[ca680bc5]	857	srwi r29, r29, 2
[b4fdfc6]	858	mtctr r29 /* set ctr reg */
[efdfd48]	859
	860
[b4fdfc6]	861	slwi r29, r29, 2
	862	sub r28, r28, r29 /* maybe some residual bytes */
	863	xor r29, r29, r29
[efdfd48]	864
	865
[ca680bc5]	866	clr_mem_word:
[b4fdfc6]	867	stswi r29, r30, 0x04 /* store r29 (word) to r30 memory location */
	868	addi r30, r30, 0x04 /* increment r30 */
[efdfd48]	869
[b4fdfc6]	870	bdnz clr_mem_word /* dec counter and loop */
[efdfd48]	871
	872
[ca680bc5]	873	cmpwi r28, 0x00 /* clear mem. finished ? */
	874	beq clr_mem_end;
[b4fdfc6]	875	mtctr r28 /* reload counter for residual bytes */
[ca680bc5]	876	clr_mem_byte:
	877	stswi r29, r30, 0x01 /* store r29 (byte) to r30 memory location */
	878	addi r30, r30, 0x01 /* update r30 */
[efdfd48]	879
[b4fdfc6]	880	bdnz clr_mem_byte /* dec counter and loop */
[efdfd48]	881
[ca680bc5]	882	clr_mem_end:
[b4fdfc6]	883	blr /* return */
[ca680bc5]	884
[25ed11d0]	885	XLB_init:
	886	/* init arbiter and stuff... */
	887	LWI r30, 0x8000a06e
	888	stw r30, ARBCFG(r31) /* Set ARBCFG */
	889
	890	LWI r30, 0x000000ff
	891	stw r30, ARBMPREN(r31) /* Set ARBMPREN */
[efdfd48]	892
[25ed11d0]	893	LWI r30, 0x00001234
	894	stw r30, ARBMPRIO(r31) /* Set ARBPRIO */
	895
	896	LWI r30, 0x0000001e
	897	stw r30, ARBSNOOP(r31) /* Set ARBSNOOP */
[efdfd48]	898
[be04e62]	899	LWI r30, 4096
	900	stw r30, ARBADRTO(r31) /* Set ARBADRTO */
	901	stw r30, ARBDATTO(r31) /* Set ARBDATTO */
	902
[25ed11d0]	903	blr

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