[ca680bc5] | 1 | /*===============================================================*\ |
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| 2 | | Project: RTEMS generic MPC5200 BSP | |
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| 3 | +-----------------------------------------------------------------+ |
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| 4 | | Partially based on the code references which are named below. | |
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| 5 | | Adaptions, modifications, enhancements and any recent parts of | |
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| 6 | | the code are: | |
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| 7 | | Copyright (c) 2005 | |
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| 8 | | Embedded Brains GmbH | |
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| 9 | | Obere Lagerstr. 30 | |
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| 10 | | D-82178 Puchheim | |
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| 11 | | Germany | |
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| 12 | | rtems@embedded-brains.de | |
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| 13 | +-----------------------------------------------------------------+ |
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| 14 | | The license and distribution terms for this file may be | |
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| 15 | | found in the file LICENSE in this distribution or at | |
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| 16 | | | |
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| 17 | | http://www.rtems.com/license/LICENSE. | |
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| 18 | | | |
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| 19 | +-----------------------------------------------------------------+ |
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| 20 | | this file contains the startup assembly code | |
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| 21 | \*===============================================================*/ |
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| 22 | /***********************************************************************/ |
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| 23 | /* */ |
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| 24 | /* Module: start.S */ |
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| 25 | /* Date: 07/17/2003 */ |
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| 26 | /* Purpose: RTEMS MPC5x00 CPU assembly startup */ |
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| 27 | /* */ |
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| 28 | /*---------------------------------------------------------------------*/ |
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| 29 | /* */ |
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| 30 | /* Description: This file contains the assembler portion of MPC5x00 */ |
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| 31 | /* startup code */ |
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| 32 | /* */ |
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| 33 | /*---------------------------------------------------------------------*/ |
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| 34 | /* */ |
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| 35 | /* Code */ |
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| 36 | /* References: startup code for Motorola PQII ADS board */ |
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| 37 | /* Module: start.S */ |
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| 38 | /* Project: RTEMS 4.6.0pre1 / MCF8260ads BSP */ |
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| 39 | /* Version 1.2 */ |
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| 40 | /* Date: 04/18/2002 */ |
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| 41 | /* */ |
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| 42 | /* Author(s) / Copyright(s): */ |
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| 43 | /* */ |
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| 44 | /* Modified for the Motorola PQII ADS board by */ |
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| 45 | /* Andy Dachs <a.dachs@sstl.co.uk> 23-11-00. */ |
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| 46 | /* Surrey Satellite Technology Limited */ |
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| 47 | /* */ |
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| 48 | /* I have a proprietary bootloader programmed into the flash */ |
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| 49 | /* on the board which initialises the SDRAM prior to calling */ |
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| 50 | /* this function. */ |
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| 51 | /* */ |
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| 52 | /* This file is based on the one by Jay Monkman (jmonkman@fracsa.com)*/ |
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| 53 | /* which in turn was based on the dlentry.s file for the Papyrus BSP,*/ |
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| 54 | /* written by: */ |
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| 55 | /* */ |
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| 56 | /* Author: Andrew Bray <andy@i-cubed.co.uk> */ |
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| 57 | /* */ |
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| 58 | /* COPYRIGHT (c) 1995 by i-cubed ltd. */ |
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| 59 | /* */ |
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| 60 | /* To anyone who acknowledges that this file is provided "AS IS" */ |
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| 61 | /* without any express or implied warranty: */ |
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| 62 | /* permission to use, copy, modify, and distribute this file */ |
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| 63 | /* for any purpose is hereby granted without fee, provided that */ |
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| 64 | /* the above copyright notice and this notice appears in all */ |
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| 65 | /* copies, and that the name of i-cubed limited not be used in */ |
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| 66 | /* advertising or publicity pertaining to distribution of the */ |
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| 67 | /* software without specific, written prior permission. */ |
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| 68 | /* i-cubed limited makes no representations about the suitability */ |
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| 69 | /* of this software for any purpose. */ |
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| 70 | /* */ |
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| 71 | /*---------------------------------------------------------------------*/ |
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| 72 | /* */ |
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| 73 | /* Partially based on the code references which are named above. */ |
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| 74 | /* Adaptions, modifications, enhancements and any recent parts of */ |
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| 75 | /* the code are under the right of */ |
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| 76 | /* */ |
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[1af911b8] | 77 | /* IPR Engineering, Dachauer StraÃe 38, D-80335 MÃŒnchen */ |
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[ca680bc5] | 78 | /* Copyright(C) 2003 */ |
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| 79 | /* */ |
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| 80 | /*---------------------------------------------------------------------*/ |
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| 81 | /* */ |
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| 82 | /* IPR Engineering makes no representation or warranties with */ |
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| 83 | /* respect to the performance of this computer program, and */ |
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| 84 | /* specifically disclaims any responsibility for any damages, */ |
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| 85 | /* special or consequential, connected with the use of this program. */ |
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| 86 | /* */ |
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| 87 | /*---------------------------------------------------------------------*/ |
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| 88 | /* */ |
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| 89 | /* Version history: 1.0 */ |
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| 90 | /* */ |
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| 91 | /***********************************************************************/ |
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[820d1ab0] | 92 | |
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[ca680bc5] | 93 | #include <rtems/powerpc/cache.h> |
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[82bd8d9d] | 94 | |
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| 95 | #include <bsp.h> |
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| 96 | #include <bsp/mpc5200.h> |
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[ca680bc5] | 97 | |
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| 98 | /* Some register offsets of MPC5x00 memory map registers */ |
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| 99 | .set CS0STR, 0x04 |
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| 100 | .set CS0STP, 0x08 |
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| 101 | .set CS1STR, 0x0C |
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| 102 | .set CS1STP, 0x10 |
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| 103 | .set SDRAMCS0, 0x34 |
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| 104 | .set SDRAMCS1, 0x38 |
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| 105 | .set BOOTSTR, 0x4C |
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| 106 | .set BOOTSTP, 0x50 |
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[efdfd48] | 107 | .set ADREN, 0x54 |
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[ca680bc5] | 108 | .set CSSR0, 0x58 /* Critical Interrupt SSR0 (603le only) */ |
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| 109 | .set CSSR1, 0x59 /* Critical Interrupt SSR1 (603le only) */ |
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| 110 | .set CFG, 0x20C |
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| 111 | .set CSBOOTROM, 0x300 |
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| 112 | .set CSCONTROL, 0x318 |
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| 113 | .set CS1CONF, 0x304 |
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| 114 | |
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| 115 | |
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| 116 | /* Register offsets of MPC5x00 SDRAM memory controller registers */ |
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| 117 | .set MOD, 0x100 |
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| 118 | .set CTRL, 0x104 |
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| 119 | .set CFG1, 0x108 |
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| 120 | .set CFG2, 0x10C |
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| 121 | .set ADRSEL, 0x110 |
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| 122 | |
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| 123 | /* Register offsets of MPC5x00 GPIO registers needed */ |
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| 124 | .set GPIOPCR, 0xb00 |
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[efdfd48] | 125 | .set GPIOWE, 0xc00 |
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[ca680bc5] | 126 | .set GPIOWOD, 0xc04 |
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| 127 | .set GPIOWDD, 0xc08 |
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| 128 | .set GPIOWDO, 0xc0c |
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| 129 | |
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| 130 | .set GPIOSEN, 0xb04 |
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| 131 | .set GPIOSDD, 0xb0c |
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| 132 | .set GPIOSDO, 0xb10 |
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| 133 | |
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| 134 | /* Register offsets of MPC5x00 Arbiter registers */ |
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| 135 | .set ARBCFG, 0x1f40 |
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| 136 | .set ARBMPREN, 0x1f64 |
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| 137 | .set ARBMPRIO, 0x1f68 |
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| 138 | .set ARBSNOOP, 0x1f70 |
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| 139 | |
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| 140 | /* Some bit encodings for MGT5100 registers */ |
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| 141 | .set ADREN_SDRAM_EN, (1<<22) |
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| 142 | .set ADREN_BOOT_EN, (1<<25) |
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| 143 | .set ADREN_CS0_EN, (1<<16) |
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| 144 | .set ADREN_CS1_EN, (1<<17) |
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| 145 | |
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| 146 | .set CTRL_PRECHARGE, (1<<1) |
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| 147 | .set CTRL_REFRESH, (1<<2) |
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| 148 | .set CTRL_BA1, (1<<31) |
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| 149 | |
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| 150 | .set CSCONF_CE, (1<<12) |
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| 151 | |
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| 152 | /* Some fixed values for MPC5x00 registers */ |
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| 153 | .set CSBOOTROM_VAL, 0x0101D910 |
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| 154 | .set CSCONTROL_VAL, 0x91000000 |
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| 155 | .set CFG_VAL, 0x00000100 |
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| 156 | |
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| 157 | .extern boot_card |
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| 158 | |
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[efdfd48] | 159 | .section ".entry" |
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[ca680bc5] | 160 | PUBLIC_VAR (start) |
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| 161 | start: |
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| 162 | /* 1st: initialization work (common for RAM/ROM startup) */ |
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| 163 | mfmsr r30 |
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| 164 | SETBITS r30, r29, MSR_ME|MSR_RI |
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| 165 | CLRBITS r30, r29, MSR_EE |
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| 166 | mtmsr r30 /* Set RI/ME, Clr EE in MSR */ |
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[efdfd48] | 167 | |
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[ca680bc5] | 168 | #if defined(HAS_UBOOT) |
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[efdfd48] | 169 | /* store pointer to UBoot bd_info board info structure */ |
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[144ad33] | 170 | LWI r31,bsp_uboot_board_info_ptr |
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[ca680bc5] | 171 | stw r3,0(r31) |
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| 172 | #endif /* defined(HAS_UBOOT) */ |
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| 173 | |
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| 174 | #if defined(NEED_LOW_LEVEL_INIT) |
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| 175 | /* initialize the MBAR (common RAM/ROM startup) */ |
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| 176 | LWI r31, MBAR_RESET |
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| 177 | LWI r29, MBAR |
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| 178 | rlwinm r30, r29,16,16,31 |
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[efdfd48] | 179 | stw r30, 0(r31) /* Set the MBAR */ |
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| 180 | #endif |
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[ca680bc5] | 181 | |
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| 182 | LWI r31, MBAR /* set r31 to current MBAR */ |
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| 183 | /* init GPIOPCR */ |
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| 184 | lwz r29,GPIOPCR(r31) |
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[1f4db180] | 185 | LWI r30, BSP_GPIOPCR_INITMASK |
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[ca680bc5] | 186 | not r30,r30 |
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| 187 | and r29,r29,r30 |
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[1f4db180] | 188 | LWI r30, BSP_GPIOPCR_INITVAL |
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[ca680bc5] | 189 | or r29,r29,r30 |
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| 190 | stw r29, GPIOPCR(r31) |
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[efdfd48] | 191 | |
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| 192 | /* further initialization work (common RAM/ROM startup) */ |
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| 193 | bl TLB_init /* Initialize TLBs */ |
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| 194 | |
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| 195 | |
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[ca680bc5] | 196 | bl FID_DCache /* Flush, inhibit and disable data cache */ |
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[efdfd48] | 197 | |
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| 198 | |
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[ca680bc5] | 199 | bl IDUL_ICache /* Inhibit, disable and unlock instruction cache */ |
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[efdfd48] | 200 | |
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| 201 | |
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| 202 | bl FPU_init /* Initialize FPU */ |
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| 203 | |
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| 204 | |
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[ca680bc5] | 205 | #if defined(NEED_LOW_LEVEL_INIT) |
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[efdfd48] | 206 | bl SPRG_init /* Initialize special purpose registers */ |
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| 207 | #endif |
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| 208 | |
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[ca680bc5] | 209 | #if defined(NEED_LOW_LEVEL_INIT) |
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| 210 | /* detect RAM/ROM startup (common for RAM/ROM startup) */ |
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[82bd8d9d] | 211 | LWI r20, bsp_rom_start /* set the relocation offset */ |
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[efdfd48] | 212 | |
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| 213 | |
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[ca680bc5] | 214 | LWI r30, CFG_VAL /* get CFG register content */ |
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| 215 | lwz r30, CFG(r31) /* set SDRAM single data rate / XLB_CLK=FVCO/4 / IPB_CLK=XLB_CLK/2 / PCICLK=IPB_CLK */ |
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[efdfd48] | 216 | |
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| 217 | |
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[ca680bc5] | 218 | |
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| 219 | lwz r30, ADREN(r31) /* get content of ADREN */ |
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[efdfd48] | 220 | |
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| 221 | |
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| 222 | |
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[ca680bc5] | 223 | TSTBITS r30, r29, ADREN_BOOT_EN |
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| 224 | bne skip_ROM_start /* If BOOT_ROM is not enabled, skip further initialization */ |
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| 225 | |
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[efdfd48] | 226 | /* do some board dependent configuration (unique for ROM startup) */ |
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| 227 | bl SPRG_brk_init /* Initialize special purpose onchip breakpoint registers */ |
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| 228 | |
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| 229 | |
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[ca680bc5] | 230 | LWI r30, CSCONTROL_VAL /* get CSCONTROL register content */ |
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| 231 | stw r30, CSCONTROL(r31) /* enable internal/external bus error and master for CS */ |
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[efdfd48] | 232 | |
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| 233 | |
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[ca680bc5] | 234 | |
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[c9b005a9] | 235 | #ifdef BRS5L |
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[ca680bc5] | 236 | LWI r30, CSBOOTROM_VAL |
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| 237 | stw r30, CSBOOTROM(r31) /* Set CSBOOTROM */ |
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[efdfd48] | 238 | |
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| 239 | |
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[1f4db180] | 240 | #endif /* BRS5L */ |
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[efdfd48] | 241 | |
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[ca680bc5] | 242 | |
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| 243 | /* FIXME: map BOOT ROM into final location with CS0 registers */ |
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[82bd8d9d] | 244 | LWI r30, bsp_rom_start |
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[ca680bc5] | 245 | rlwinm r30, r30,17,15,31 |
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[efdfd48] | 246 | stw r30, CS0STR(r31) /* Set CS0STR */ |
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| 247 | |
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[82bd8d9d] | 248 | LWI r30, bsp_rom_end |
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[efdfd48] | 249 | |
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[ca680bc5] | 250 | rlwinm r30, r30,17,15,31 |
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| 251 | stw r30, CS0STP(r31) /* Set CS0STP */ |
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[efdfd48] | 252 | |
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[ca680bc5] | 253 | lwz r30, ADREN(r31) /* get content of ADREN */ |
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[efdfd48] | 254 | SETBITS r30, r29, ADREN_CS0_EN |
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[ca680bc5] | 255 | stw r30, ADREN(r31) /* enable CS0 mapping */ |
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| 256 | isync |
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| 257 | /* jump to same code in final BOOT ROM location */ |
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| 258 | LWI r30, reloc_in_CS0 |
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[82bd8d9d] | 259 | LWI r29, bsp_ram_start |
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[ca680bc5] | 260 | sub r30,r30,r29 |
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[82bd8d9d] | 261 | LWI r29, bsp_rom_start |
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[ca680bc5] | 262 | add r30,r30,r29 |
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| 263 | mtctr r30 |
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| 264 | bctr |
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[efdfd48] | 265 | |
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| 266 | reloc_in_CS0: |
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[ca680bc5] | 267 | /* disable CSBOOT (or map it to CS0 range) */ |
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| 268 | lwz r30, ADREN(r31) /* get content of ADREN */ |
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[efdfd48] | 269 | CLRBITS r30, r29, ADREN_BOOT_EN |
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[ca680bc5] | 270 | stw r30, ADREN(r31) /* disable BOOT mapping */ |
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[efdfd48] | 271 | |
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[ca680bc5] | 272 | /* init SDRAM */ |
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[82bd8d9d] | 273 | LWI r30, bsp_ram_start |
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| 274 | ori r30, r30, 0x1a /* size code: bank is 128MByte */ |
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| 275 | stw r30, SDRAMCS0(r31) /* Set SDRAMCS0 */ |
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[ca680bc5] | 276 | |
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[82bd8d9d] | 277 | LWI r30, bsp_ram_size |
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| 278 | srawi r30, r30, 1 |
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| 279 | ori r30, r30, 0x1a /* size code: bank is 128MByte */ |
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[ca680bc5] | 280 | stw r30, SDRAMCS1(r31) /* Set SDRAMCS1 */ |
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[efdfd48] | 281 | |
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[ca680bc5] | 282 | bl SDRAM_init /* Initialize SDRAM controller */ |
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| 283 | |
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| 284 | /* init arbiter and stuff... */ |
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| 285 | LWI r30, 0x8000a06e |
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| 286 | stw r30, ARBCFG(r31) /* Set ARBCFG */ |
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[efdfd48] | 287 | |
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[ca680bc5] | 288 | LWI r30, 0x000000ff |
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| 289 | stw r30, ARBMPREN(r31) /* Set ARBMPREN */ |
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[efdfd48] | 290 | |
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[ca680bc5] | 291 | LWI r30, 0x00001234 |
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[efdfd48] | 292 | stw r30, ARBMPRIO(r31) /* Set ARBPRIO */ |
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[ca680bc5] | 293 | |
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| 294 | LWI r30, 0x0000001e |
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[efdfd48] | 295 | stw r30, ARBSNOOP(r31) /* Set ARBSNOOP */ |
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[ca680bc5] | 296 | /* copy .text section from ROM to RAM location (unique for ROM startup) */ |
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[82bd8d9d] | 297 | LA r30, bsp_section_text_start /* get start address of text section in RAM */ |
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[efdfd48] | 298 | |
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| 299 | |
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[ca680bc5] | 300 | add r30, r20, r30 /* get start address of text section in ROM (add reloc offset) */ |
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[efdfd48] | 301 | |
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| 302 | |
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[82bd8d9d] | 303 | LA r29, bsp_section_text_start /* get start address of text section in RAM */ |
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[efdfd48] | 304 | |
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[ca680bc5] | 305 | |
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[82bd8d9d] | 306 | LA r28, bsp_section_text_size /* get size of RAM image */ |
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[efdfd48] | 307 | |
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| 308 | |
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[ca680bc5] | 309 | bl copy_image /* copy text section from ROM to RAM location */ |
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[efdfd48] | 310 | |
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[ca680bc5] | 311 | |
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| 312 | /* copy .data section from ROM to RAM location (unique for ROM startup) */ |
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[82bd8d9d] | 313 | LA r30, bsp_section_data_start /* get start address of data section in RAM */ |
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[efdfd48] | 314 | |
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| 315 | |
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[ca680bc5] | 316 | add r30, r20, r30 /* get start address of data section in ROM (add reloc offset) */ |
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[efdfd48] | 317 | |
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| 318 | |
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[82bd8d9d] | 319 | LA r29, bsp_section_data_start /* get start address of data section in RAM */ |
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[efdfd48] | 320 | |
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| 321 | |
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[82bd8d9d] | 322 | LA r28, bsp_section_data_size /* get size of RAM image */ |
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[efdfd48] | 323 | |
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| 324 | |
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[ca680bc5] | 325 | bl copy_image /* copy initialized data section from ROM to RAM location */ |
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[efdfd48] | 326 | |
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[ca680bc5] | 327 | |
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| 328 | LA r29, remap_rom /* get compile time address of label */ |
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| 329 | mtlr r29 |
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[efdfd48] | 330 | |
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[ca680bc5] | 331 | blrl /* now further execution RAM */ |
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| 332 | |
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[efdfd48] | 333 | remap_rom: |
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[ca680bc5] | 334 | /* remap BOOT ROM to CS0 (common for RAM/ROM startup) */ |
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| 335 | lwz r30, CSBOOTROM(r31) /* get content of CSBOOTROM */ |
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[efdfd48] | 336 | |
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| 337 | |
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| 338 | |
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| 339 | CLRBITS r30, r29, CSCONF_CE |
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| 340 | stw r30, CSBOOTROM(r31) /* disable BOOT CS */ |
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| 341 | |
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| 342 | |
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[ca680bc5] | 343 | |
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| 344 | lwz r30, ADREN(r31) /* get content of ADREN */ |
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[efdfd48] | 345 | |
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| 346 | |
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[ca680bc5] | 347 | |
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| 348 | mr r29, r30 /* move content of r30 to r29 */ |
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[efdfd48] | 349 | |
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| 350 | |
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[ca680bc5] | 351 | LWI r30, ADREN_BOOT_EN /* mask ADREN_BOOT_EN */ |
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[efdfd48] | 352 | andc r29,r29,r30 |
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| 353 | |
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| 354 | |
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[ca680bc5] | 355 | LWI r30, ADREN_CS0_EN /* unmask ADREN_CS0_EN */ |
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[efdfd48] | 356 | or r29,r29,r30 |
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| 357 | |
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| 358 | |
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[ca680bc5] | 359 | stw r29,ADREN(r31) /* Simultaneous enable CS0 and disable BOOT address space */ |
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[efdfd48] | 360 | |
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| 361 | |
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| 362 | |
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[ca680bc5] | 363 | lwz r30, CSBOOTROM(r31) /* get content of CSBOOTROM */ |
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[efdfd48] | 364 | |
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| 365 | |
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| 366 | |
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| 367 | SETBITS r30, r29, CSCONF_CE |
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| 368 | stw r30, CSBOOTROM(r31) /* disable BOOT CS */ |
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| 369 | |
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| 370 | |
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[ca680bc5] | 371 | |
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| 372 | skip_ROM_start: |
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| 373 | /* configure external DPRAM CS1 */ |
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[82bd8d9d] | 374 | LWI r30, 0xFFFFFB10 |
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| 375 | stw r30, CS1CONF(r31) |
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[ca680bc5] | 376 | |
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| 377 | /* map external DPRAM (CS1) */ |
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[82bd8d9d] | 378 | LWI r30, bsp_dpram_start |
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| 379 | srawi r30, r30, 16 |
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| 380 | stw r30, CS1STR(r31) |
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[ca680bc5] | 381 | |
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[82bd8d9d] | 382 | LWI r30, bsp_dpram_end |
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| 383 | srawi r30, r30, 16 |
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| 384 | stw r30, CS1STP(r31) |
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[ca680bc5] | 385 | |
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| 386 | lwz r30, ADREN(r31) /* get content of ADREN */ |
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[efdfd48] | 387 | |
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[ca680bc5] | 388 | LWI r29, ADREN_CS1_EN /* unmask ADREN_CS1_EN */ |
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[efdfd48] | 389 | or r30, r30,r29 |
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| 390 | |
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[82bd8d9d] | 391 | stw r30, ADREN(r31) /* enable CS1 */ |
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[ca680bc5] | 392 | |
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| 393 | /* clear entire on chip SRAM (unique for ROM startup) */ |
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[c9b005a9] | 394 | lis r30, (MBAR+ONCHIP_SRAM_OFFSET)@h /* get start address of onchip SRAM */ |
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[82bd8d9d] | 395 | ori r30, r30,(MBAR+ONCHIP_SRAM_OFFSET)@l |
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[ca680bc5] | 396 | LWI r29, ONCHIP_SRAM_SIZE /* get size of onchip SRAM */ |
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[efdfd48] | 397 | |
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[ca680bc5] | 398 | bl clr_mem /* Clear onchip SRAM */ |
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[efdfd48] | 399 | |
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[1f4db180] | 400 | #endif /* defined(NEED_LOW_LEVEL_INIT) */ |
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[ca680bc5] | 401 | /* clear .bss section (unique for ROM startup) */ |
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[82bd8d9d] | 402 | LWI r30, bsp_section_bss_start /* get start address of bss section */ |
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| 403 | LWI r29, bsp_section_bss_size /* get size of bss section */ |
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[efdfd48] | 404 | |
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[ca680bc5] | 405 | |
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| 406 | bl clr_mem /* Clear the bss section */ |
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[efdfd48] | 407 | |
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[ca680bc5] | 408 | |
---|
| 409 | /* set stack pointer (common for RAM/ROM startup) */ |
---|
[efdfd48] | 410 | LA r1, bsp_section_text_start |
---|
[ca680bc5] | 411 | addi r1, r1, -0x10 /* Set up stack pointer = beginning of text section - 0x10 */ |
---|
[82bd8d9d] | 412 | |
---|
| 413 | bl __eabi /* Set up EABI and SYSV environment */ |
---|
[efdfd48] | 414 | |
---|
[ca680bc5] | 415 | /* enable dynamic power management(common for RAM/ROM startup) */ |
---|
| 416 | bl PPC_HID0_rd /* Get the content of HID0 */ |
---|
[efdfd48] | 417 | |
---|
| 418 | SETBITS r30, r29, HID0_DPM |
---|
[ca680bc5] | 419 | bl PPC_HID0_wr /* Set DPM in HID0 */ |
---|
| 420 | |
---|
| 421 | /* clear arguments and do further init. in C (common for RAM/ROM startup) */ |
---|
[aa058378] | 422 | |
---|
[820d1ab0] | 423 | /* Clear cmdline */ |
---|
[aa058378] | 424 | xor r3, r3, r3 |
---|
[efdfd48] | 425 | |
---|
[ca680bc5] | 426 | bl SYM (boot_card) /* Call the first C routine */ |
---|
[0a029a5] | 427 | |
---|
[efdfd48] | 428 | twiddle: |
---|
[ca680bc5] | 429 | b twiddle /* We don't expect to return from boot_card but if we do */ |
---|
| 430 | /* wait here for watchdog to kick us into hard reset */ |
---|
| 431 | |
---|
[1f4db180] | 432 | #if defined(NEED_LOW_LEVEL_INIT) |
---|
[efdfd48] | 433 | SDRAM_init: |
---|
[1f4db180] | 434 | #if defined(BRS5L) |
---|
[ca680bc5] | 435 | /* set GPIO_WKUP7 pin low for 66MHz buffering */ |
---|
| 436 | /* or high for 133MHz registered buffering */ |
---|
| 437 | LWI r30, 0x80000000 |
---|
[efdfd48] | 438 | |
---|
[ca680bc5] | 439 | lwz r29, GPIOWE(r31) |
---|
| 440 | or r29,r29,r30 /* set bit 0 in r29/GPIOWE */ |
---|
| 441 | stw r29,GPIOWE(r31) |
---|
[efdfd48] | 442 | |
---|
[ca680bc5] | 443 | lwz r29, GPIOWOD(r31) |
---|
| 444 | andc r29,r29,r30 /* clear bit 0 in r29/GPIOWOD */ |
---|
| 445 | stw r29,GPIOWOD(r31) |
---|
| 446 | |
---|
| 447 | lwz r29, GPIOWDO(r31) |
---|
| 448 | andc r29,r29,r30 /* clear bit 0 in r29/GPIOWDO */ |
---|
| 449 | stw r29,GPIOWDO(r31) |
---|
[efdfd48] | 450 | |
---|
[ca680bc5] | 451 | lwz r29, GPIOWDD(r31) |
---|
| 452 | or r29,r29,r30 /* set bit 0 in r29/GPIOWDD */ |
---|
| 453 | stw r29,GPIOWDD(r31) |
---|
| 454 | |
---|
| 455 | /* activate MEM_CS1 output */ |
---|
| 456 | lwz r29, GPIOPCR(r31) |
---|
| 457 | or r29,r29,r30 /* set bit 0 in r29/GPIOPCR */ |
---|
| 458 | stw r29,GPIOPCR(r31) |
---|
| 459 | |
---|
| 460 | #endif |
---|
| 461 | /* See Erratum 342/339 in MPC5200_Errata_L25R_3_June.pdf: */ |
---|
| 462 | /* set 5 delays to their maximum to support two banks */ |
---|
[456d9b2] | 463 | #if 0 |
---|
| 464 | LWI r30, 0xCC222600 /* Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x2 */ |
---|
| 465 | #else |
---|
| 466 | /* EB 04.12.08: |
---|
| 467 | * on MPC5200B, Erratum342 is no longer applicable. |
---|
| 468 | * on MPC5200_, Single Write2Read/Prec is only 3 bits, |
---|
| 469 | * therefore the MSB of the set value (1100) was ignored |
---|
| 470 | * in the MPC5200B, this bit is implemented in results in |
---|
| 471 | * SSSLLLOOOWWW access to SDRAM. To make the mem ctrl settings compatible with the MPC5200_, |
---|
| 472 | * we use a 4 for now. |
---|
| 473 | */ |
---|
| 474 | LWI r30, 0xC4222600 /* Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x4 */ |
---|
| 475 | #endif |
---|
| 476 | stw r30, CFG1(r31) /* Read CAS latency=0x2, Active2Read delay=0x2, Prec.2active delay=0x2 */ |
---|
[ca680bc5] | 477 | /* Refr.2No-Read delay=0x06, Write latency=0x0 */ |
---|
[456d9b2] | 478 | |
---|
| 479 | LWI r30, 0xCCC70004 /* Burst2Read Prec.delay=0x8, Burst Write delay=0x8 */ |
---|
[ca680bc5] | 480 | stw r30, CFG2(r31) /* Burst Read2Write delay=0xB, Burst length=0x7, Read Tap=0x4 */ |
---|
[efdfd48] | 481 | |
---|
[c9b005a9] | 482 | #ifdef BRS5L |
---|
[ca680bc5] | 483 | LWI r30, 0xD1470000 /* Mode Set enabled, Clock enabled, Auto refresh enabled, Mem. data drv */ |
---|
| 484 | stw r30, CTRL(r31) /* Refresh counter=0xFFFF */ |
---|
[efdfd48] | 485 | |
---|
| 486 | |
---|
[ca680bc5] | 487 | #else |
---|
| 488 | LWI r30, 0xD04F0000 /* Mode Set enabled, Clock enabled, Auto refresh enabled, Mem. data drv */ |
---|
| 489 | stw r30, CTRL(r31) /* Refresh counter=0xFFFF */ |
---|
[efdfd48] | 490 | |
---|
| 491 | |
---|
| 492 | #endif |
---|
| 493 | lwz r30, CTRL(r31) |
---|
| 494 | |
---|
[ca680bc5] | 495 | |
---|
| 496 | SETBITS r30, r29, CTRL_PRECHARGE /* send two times precharge */ |
---|
| 497 | stw r30, CTRL(r31) |
---|
[efdfd48] | 498 | |
---|
| 499 | |
---|
[ca680bc5] | 500 | stw r30, CTRL(r31) |
---|
[efdfd48] | 501 | |
---|
| 502 | |
---|
| 503 | |
---|
[ca680bc5] | 504 | lwz r30, CTRL(r31) |
---|
[efdfd48] | 505 | |
---|
| 506 | |
---|
[ca680bc5] | 507 | SETBITS r30, r29, CTRL_REFRESH /* send two times refresh */ |
---|
| 508 | stw r30, CTRL(r31) |
---|
[efdfd48] | 509 | |
---|
| 510 | |
---|
[ca680bc5] | 511 | stw r30, CTRL(r31) |
---|
[efdfd48] | 512 | |
---|
| 513 | |
---|
| 514 | |
---|
[ca680bc5] | 515 | LWI r30, 0x008D0000 /* Op.Mode=0x0, Read CAS latency=0x2, Burst length=0x3, Write strobe puls */ |
---|
[efdfd48] | 516 | stw r30, MOD(r31) |
---|
| 517 | |
---|
| 518 | |
---|
| 519 | |
---|
| 520 | lwz r30, CTRL(r31) /* Clock enabled, Auto refresh enabled, Mem. data drv. Refresh counter=0xFFFF */ |
---|
| 521 | |
---|
[ca680bc5] | 522 | |
---|
| 523 | CLRBITS r30, r29, CTRL_BA1 |
---|
| 524 | stw r30, CTRL(r31) |
---|
[efdfd48] | 525 | |
---|
| 526 | |
---|
| 527 | |
---|
[ca680bc5] | 528 | blr |
---|
| 529 | |
---|
| 530 | |
---|
| 531 | copy_image: |
---|
| 532 | mr r27, r28 |
---|
| 533 | srwi r28, r28, 2 |
---|
| 534 | mtctr r28 |
---|
[efdfd48] | 535 | |
---|
| 536 | |
---|
[ca680bc5] | 537 | slwi r28, r28, 2 |
---|
| 538 | sub r27, r27, r28 /* maybe some residual bytes */ |
---|
[efdfd48] | 539 | |
---|
| 540 | |
---|
[ca680bc5] | 541 | copy_image_word: |
---|
| 542 | lswi r28, r30, 0x04 |
---|
[efdfd48] | 543 | |
---|
[ca680bc5] | 544 | stswi r28, r29, 0x04 /* do word copy ROM -> RAM */ |
---|
[efdfd48] | 545 | |
---|
[ca680bc5] | 546 | |
---|
| 547 | addi r30, r30, 0x04 /* increment source pointer */ |
---|
| 548 | addi r29, r29, 0x04 /* increment destination pointer */ |
---|
[efdfd48] | 549 | |
---|
[ca680bc5] | 550 | bdnz copy_image_word /* decrement ctr and branch if not 0 */ |
---|
| 551 | |
---|
| 552 | cmpwi r27, 0x00 /* copy image finished ? */ |
---|
| 553 | beq copy_image_end; |
---|
| 554 | mtctr r27 /* reload counter for residual bytes */ |
---|
| 555 | copy_image_byte: |
---|
| 556 | lswi r28, r30, 0x01 |
---|
[efdfd48] | 557 | |
---|
[ca680bc5] | 558 | stswi r28, r29, 0x01 /* do byte copy ROM -> RAM */ |
---|
[efdfd48] | 559 | |
---|
| 560 | |
---|
[ca680bc5] | 561 | addi r30, r30, 0x01 /* increment source pointer */ |
---|
| 562 | addi r29, r29, 0x01 /* increment destination pointer */ |
---|
[efdfd48] | 563 | |
---|
[ca680bc5] | 564 | bdnz copy_image_byte /* decrement ctr and branch if not 0 */ |
---|
[efdfd48] | 565 | |
---|
[ca680bc5] | 566 | copy_image_end: |
---|
| 567 | blr |
---|
[1f4db180] | 568 | #endif /* defined(NEED_LOW_LEVEL_INIT) */ |
---|
[ca680bc5] | 569 | |
---|
| 570 | FID_DCache: |
---|
[efdfd48] | 571 | mflr r26 |
---|
| 572 | |
---|
| 573 | bl PPC_HID0_rd |
---|
| 574 | TSTBITS r30, r29, HID0_DCE |
---|
[ca680bc5] | 575 | bne FID_DCache_exit /* If data cache is switched of, skip further actions */ |
---|
| 576 | |
---|
| 577 | li r29, PPC_D_CACHE /* 16 Kb data cache on 603e */ |
---|
[82bd8d9d] | 578 | LWI r28, bsp_section_text_start /* Load base address (begin of RAM) */ |
---|
[ca680bc5] | 579 | |
---|
| 580 | FID_DCache_loop_1: |
---|
| 581 | lwz r27, 0(r28) /* Load data at address */ |
---|
[efdfd48] | 582 | |
---|
[ca680bc5] | 583 | addi r28, r28, PPC_CACHE_ALIGNMENT /* increment cache line address */ |
---|
[efdfd48] | 584 | subi r29, r29, PPC_CACHE_ALIGNMENT /* increment loop counter */ |
---|
[ca680bc5] | 585 | cmpwi r29, 0x0 |
---|
| 586 | bne FID_DCache_loop_1 /* Loop until cache size is reached */ |
---|
| 587 | |
---|
| 588 | li r29, PPC_D_CACHE /* 16 Kb data cache on 603e */ |
---|
[82bd8d9d] | 589 | LWI r28, bsp_section_text_start /* Reload base address (begin of RAM) */ |
---|
[ca680bc5] | 590 | xor r27, r27, r27 |
---|
| 591 | FID_DCache_loop_2: |
---|
[efdfd48] | 592 | |
---|
[ca680bc5] | 593 | dcbf r27, r28 /* Flush and invalidate cache */ |
---|
[efdfd48] | 594 | |
---|
[ca680bc5] | 595 | addi r28, r28, PPC_CACHE_ALIGNMENT /* increment cache line address */ |
---|
[efdfd48] | 596 | subi r29, r29, PPC_CACHE_ALIGNMENT /* increment loop counter */ |
---|
[ca680bc5] | 597 | cmpwi r29, 0x0 |
---|
| 598 | bne FID_DCache_loop_2 /* Loop around until cache size is reached */ |
---|
| 599 | |
---|
[efdfd48] | 600 | bl PPC_HID0_rd /* Read HID0 */ |
---|
[ca680bc5] | 601 | CLRBITS r30, r29, HID0_DCE |
---|
[efdfd48] | 602 | bl PPC_HID0_wr /* Clear DCE */ |
---|
[ca680bc5] | 603 | |
---|
| 604 | FID_DCache_exit: |
---|
| 605 | mtlr r26 |
---|
| 606 | blr |
---|
| 607 | |
---|
| 608 | IDUL_ICache: |
---|
| 609 | mflr r26 |
---|
[efdfd48] | 610 | |
---|
| 611 | bl PPC_HID0_rd |
---|
[ca680bc5] | 612 | TSTBITS r30, r29, HID0_ICE |
---|
| 613 | bne IDUL_ICache_exit /* If instruction cache is switched of, skip further actions */ |
---|
| 614 | |
---|
[efdfd48] | 615 | CLRBITS r30, r29, HID0_ICE |
---|
[ca680bc5] | 616 | bl PPC_HID0_wr /* Disable ICE bit */ |
---|
| 617 | |
---|
[efdfd48] | 618 | SETBITS r30, r29, HID0_ICFI |
---|
[ca680bc5] | 619 | bl PPC_HID0_wr /* Invalidate instruction cache */ |
---|
[efdfd48] | 620 | |
---|
| 621 | CLRBITS r30, r29, HID0_ICFI |
---|
[ca680bc5] | 622 | bl PPC_HID0_wr /* Disable cache invalidate */ |
---|
[efdfd48] | 623 | |
---|
| 624 | CLRBITS r30, r29, HID0_ILOCK |
---|
| 625 | bl PPC_HID0_wr /* Disable instruction cache lock */ |
---|
[ca680bc5] | 626 | |
---|
| 627 | IDUL_ICache_exit: |
---|
| 628 | mtlr r26 |
---|
| 629 | blr |
---|
[efdfd48] | 630 | |
---|
| 631 | |
---|
[ca680bc5] | 632 | TLB_init: /* Initialize translation lookaside buffers (TLBs) */ |
---|
| 633 | xor r30, r30, r30 |
---|
[efdfd48] | 634 | xor r29, r29, r29 |
---|
| 635 | |
---|
| 636 | TLB_init_loop: |
---|
[ca680bc5] | 637 | tlbie r29 |
---|
| 638 | tlbsync |
---|
| 639 | addi r29, r29, 0x1000 |
---|
| 640 | addi r30, r30, 0x01 |
---|
| 641 | cmpli 0, 0, r30, 0x0080 |
---|
| 642 | bne TLB_init_loop |
---|
| 643 | blr |
---|
| 644 | |
---|
| 645 | FPU_init: |
---|
| 646 | mfmsr r30 /* get content of MSR */ |
---|
[efdfd48] | 647 | |
---|
| 648 | |
---|
[ca680bc5] | 649 | SETBITS r30, r29, MSR_FP |
---|
| 650 | mtmsr r30 /* enable FPU and FPU exceptions */ |
---|
[efdfd48] | 651 | |
---|
[ca680bc5] | 652 | lfd f0, 0(r29) |
---|
| 653 | fmr f1, f0 |
---|
| 654 | fmr f2, f0 |
---|
| 655 | fmr f3, f0 |
---|
| 656 | fmr f4, f0 |
---|
| 657 | fmr f5, f0 |
---|
| 658 | fmr f6, f0 |
---|
| 659 | fmr f7, f0 |
---|
| 660 | fmr f8, f0 |
---|
| 661 | fmr f9, f0 |
---|
| 662 | fmr f10, f0 |
---|
| 663 | fmr f11, f0 |
---|
| 664 | fmr f12, f0 |
---|
| 665 | fmr f13, f0 |
---|
| 666 | fmr f14, f0 |
---|
| 667 | fmr f15, f0 |
---|
| 668 | fmr f16, f0 |
---|
| 669 | fmr f17, f0 |
---|
| 670 | fmr f18, f0 |
---|
| 671 | fmr f19, f0 |
---|
| 672 | fmr f20, f0 |
---|
| 673 | fmr f21, f0 |
---|
| 674 | fmr f22, f0 |
---|
| 675 | fmr f23, f0 |
---|
| 676 | fmr f24, f0 |
---|
| 677 | fmr f25, f0 |
---|
| 678 | fmr f26, f0 |
---|
| 679 | fmr f27, f0 |
---|
| 680 | fmr f28, f0 |
---|
| 681 | fmr f29, f0 |
---|
| 682 | fmr f30, f0 |
---|
| 683 | fmr f31, f0 |
---|
[efdfd48] | 684 | |
---|
| 685 | |
---|
[ca680bc5] | 686 | mtfsfi 0, 0 /* initialize bit positons in FPSCR */ |
---|
| 687 | mtfsfi 1, 0 |
---|
| 688 | mtfsfi 2, 0 |
---|
| 689 | mtfsfi 3, 0 |
---|
| 690 | mtfsfi 4, 0 |
---|
| 691 | mtfsfi 5, 0 |
---|
| 692 | mtfsfi 6, 0 |
---|
| 693 | mtfsfi 7, 0 |
---|
[efdfd48] | 694 | |
---|
[ca680bc5] | 695 | blr |
---|
| 696 | |
---|
| 697 | SPRG_init: /* initialize registers */ |
---|
| 698 | xor r30, r30, r30 |
---|
[efdfd48] | 699 | |
---|
[ca680bc5] | 700 | mtspr XER, r30 |
---|
| 701 | mtspr CTR, r30 |
---|
| 702 | mtspr DSISR, r30 |
---|
| 703 | mtspr DAR, r30 |
---|
| 704 | mtspr DEC, r30 |
---|
| 705 | mtspr SDR1, r30 |
---|
| 706 | mtspr SRR0, r30 |
---|
| 707 | mtspr SRR1, r30 |
---|
| 708 | mtspr CSSR0, r30 |
---|
| 709 | mtspr CSSR1, r30 |
---|
| 710 | mtspr SPRG0, r30 |
---|
| 711 | mtspr SPRG1, r30 |
---|
| 712 | mtspr SPRG2, r30 |
---|
[efdfd48] | 713 | mtspr SPRG3, r30 |
---|
[ca680bc5] | 714 | mtspr SPRG4, r30 |
---|
| 715 | mtspr SPRG5, r30 |
---|
| 716 | mtspr SPRG6, r30 |
---|
| 717 | mtspr SPRG7, r30 |
---|
| 718 | mtspr EAR, r30 |
---|
| 719 | mtspr TBWU, r30 |
---|
| 720 | mtspr TBWL, r30 |
---|
| 721 | mtspr IBAT0U, r30 |
---|
| 722 | mtspr IBAT0L, r30 |
---|
| 723 | mtspr IBAT1U, r30 |
---|
| 724 | mtspr IBAT1L, r30 |
---|
| 725 | mtspr IBAT2U, r30 |
---|
| 726 | mtspr IBAT2L, r30 |
---|
| 727 | mtspr IBAT3U, r30 |
---|
| 728 | mtspr IBAT3L, r30 |
---|
| 729 | mtspr IBAT4U, r30 |
---|
| 730 | mtspr IBAT4L, r30 |
---|
| 731 | mtspr IBAT5U, r30 |
---|
| 732 | mtspr IBAT5L, r30 |
---|
| 733 | mtspr IBAT6U, r30 |
---|
| 734 | mtspr IBAT6L, r30 |
---|
| 735 | mtspr IBAT7U, r30 |
---|
| 736 | mtspr IBAT7L, r30 |
---|
| 737 | mtspr DBAT0U, r30 |
---|
| 738 | mtspr DBAT0L, r30 |
---|
| 739 | mtspr DBAT1U, r30 |
---|
| 740 | mtspr DBAT1L, r30 |
---|
| 741 | mtspr DBAT2U, r30 |
---|
| 742 | mtspr DBAT2L, r30 |
---|
| 743 | mtspr DBAT3U, r30 |
---|
| 744 | mtspr DBAT3L, r30 |
---|
| 745 | mtspr DBAT4U, r30 |
---|
| 746 | mtspr DBAT4L, r30 |
---|
| 747 | mtspr DBAT5U, r30 |
---|
| 748 | mtspr DBAT5L, r30 |
---|
| 749 | mtspr DBAT6U, r30 |
---|
| 750 | mtspr DBAT6L, r30 |
---|
| 751 | mtspr DBAT7U, r30 |
---|
| 752 | mtspr DBAT7L, r30 |
---|
| 753 | mtspr DMISS, r30 |
---|
| 754 | mtspr DCMP, r30 |
---|
| 755 | mtspr HASH1, r30 |
---|
| 756 | mtspr HASH2, r30 |
---|
| 757 | mtspr IMISS, r30 |
---|
| 758 | mtspr ICMP, r30 |
---|
| 759 | mtspr RPA, r30 |
---|
[2d108f8] | 760 | mtsr PPC_SR0, r30 |
---|
| 761 | mtsr PPC_SR1, r30 |
---|
| 762 | mtsr PPC_SR2, r30 |
---|
| 763 | mtsr PPC_SR3, r30 |
---|
| 764 | mtsr PPC_SR4, r30 |
---|
| 765 | mtsr PPC_SR5, r30 |
---|
| 766 | mtsr PPC_SR6, r30 |
---|
| 767 | mtsr PPC_SR7, r30 |
---|
| 768 | mtsr PPC_SR8, r30 |
---|
| 769 | mtsr PPC_SR9, r30 |
---|
| 770 | mtsr PPC_SR10, r30 |
---|
| 771 | mtsr PPC_SR12, r30 |
---|
| 772 | mtsr PPC_SR13, r30 |
---|
| 773 | mtsr PPC_SR14, r30 |
---|
| 774 | mtsr PPC_SR15, r30 |
---|
[efdfd48] | 775 | |
---|
| 776 | |
---|
| 777 | |
---|
| 778 | |
---|
| 779 | |
---|
[ca680bc5] | 780 | blr |
---|
| 781 | |
---|
| 782 | SPRG_brk_init: |
---|
| 783 | xor r30, r30, r30 |
---|
[efdfd48] | 784 | |
---|
[ca680bc5] | 785 | mtspr DABR2, r30 |
---|
| 786 | mtspr DBCR, r30 |
---|
| 787 | mtspr IBCR, r30 |
---|
| 788 | mtspr IABR, r30 |
---|
| 789 | mtspr HID2, r30 |
---|
| 790 | mtspr DABR, r30 |
---|
[efdfd48] | 791 | mtspr IABR2, r30 |
---|
| 792 | |
---|
| 793 | |
---|
| 794 | |
---|
[ca680bc5] | 795 | |
---|
| 796 | blr |
---|
| 797 | |
---|
[efdfd48] | 798 | |
---|
[ca680bc5] | 799 | PPC_HID0_rd: /* get HID0 content to r30 */ |
---|
[efdfd48] | 800 | |
---|
| 801 | |
---|
[ca680bc5] | 802 | mfspr r30, HID0 |
---|
[efdfd48] | 803 | |
---|
[ca680bc5] | 804 | blr |
---|
| 805 | |
---|
| 806 | |
---|
| 807 | PPC_HID0_wr: /* put r30 content to HID0 */ |
---|
[efdfd48] | 808 | |
---|
| 809 | |
---|
[ca680bc5] | 810 | mtspr HID0, r30 |
---|
[efdfd48] | 811 | |
---|
[ca680bc5] | 812 | blr |
---|
| 813 | |
---|
| 814 | clr_mem: |
---|
[efdfd48] | 815 | mr r28, r29 |
---|
[ca680bc5] | 816 | srwi r29, r29, 2 |
---|
| 817 | mtctr r29 /* set ctr reg */ |
---|
[efdfd48] | 818 | |
---|
| 819 | |
---|
[ca680bc5] | 820 | slwi r29, r29, 2 |
---|
| 821 | sub r28, r28, r29 /* maybe some residual bytes */ |
---|
[efdfd48] | 822 | xor r29, r29, r29 |
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| 823 | |
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| 824 | |
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[ca680bc5] | 825 | clr_mem_word: |
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| 826 | stswi r29, r30, 0x04 /* store r29 (word) to r30 memory location */ |
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| 827 | addi r30, r30, 0x04 /* increment r30 */ |
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[efdfd48] | 828 | |
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[ca680bc5] | 829 | bdnz clr_mem_word /* dec counter and loop */ |
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[efdfd48] | 830 | |
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| 831 | |
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[ca680bc5] | 832 | cmpwi r28, 0x00 /* clear mem. finished ? */ |
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| 833 | beq clr_mem_end; |
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| 834 | mtctr r28 /* reload counter for residual bytes */ |
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| 835 | clr_mem_byte: |
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| 836 | stswi r29, r30, 0x01 /* store r29 (byte) to r30 memory location */ |
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| 837 | addi r30, r30, 0x01 /* update r30 */ |
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[efdfd48] | 838 | |
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[ca680bc5] | 839 | bdnz clr_mem_byte /* dec counter and loop */ |
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[efdfd48] | 840 | |
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[ca680bc5] | 841 | clr_mem_end: |
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| 842 | blr /* return */ |
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| 843 | |
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[efdfd48] | 844 | |
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| 845 | |
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