[ca680bc5] | 1 | /*===============================================================*\ |
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| 2 | | Project: RTEMS generic MPC5200 BSP | |
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| 3 | +-----------------------------------------------------------------+ |
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| 4 | | Partially based on the code references which are named below. | |
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| 5 | | Adaptions, modifications, enhancements and any recent parts of | |
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| 6 | | the code are: | |
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| 7 | | Copyright (c) 2005 | |
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| 8 | | Embedded Brains GmbH | |
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| 9 | | Obere Lagerstr. 30 | |
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| 10 | | D-82178 Puchheim | |
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| 11 | | Germany | |
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| 12 | | rtems@embedded-brains.de | |
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| 13 | +-----------------------------------------------------------------+ |
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| 14 | | The license and distribution terms for this file may be | |
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| 15 | | found in the file LICENSE in this distribution or at | |
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| 16 | | | |
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| 17 | | http://www.rtems.com/license/LICENSE. | |
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| 18 | | | |
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| 19 | +-----------------------------------------------------------------+ |
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| 20 | | this file contains functions to implement a slice timer | |
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| 21 | \*===============================================================*/ |
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| 22 | /***********************************************************************/ |
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| 23 | /* */ |
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| 24 | /* Module: slicetimer.c */ |
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| 25 | /* Date: 07/17/2003 */ |
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| 26 | /* Purpose: RTEMS MPC5x00 slicetimer driver */ |
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| 27 | /* */ |
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| 28 | /*---------------------------------------------------------------------*/ |
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| 29 | /* */ |
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| 30 | /* Description: MPC5x00 slice timer routines for cyclic short time */ |
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| 31 | /* trigger */ |
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| 32 | /* */ |
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| 33 | /*---------------------------------------------------------------------*/ |
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| 34 | /* */ |
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| 35 | /* Code */ |
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| 36 | /* References: Clock driver for PPC403 */ |
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| 37 | /* Module: clock.c */ |
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| 38 | /* Project: RTEMS 4.6.0pre1 / PPC403 BSP */ |
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| 39 | /* Version 1.16 */ |
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| 40 | /* Date: 2002/11/01 */ |
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| 41 | /* Author(s) / Copyright(s): */ |
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| 42 | /* */ |
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| 43 | /* Author: Jay Monkman (jmonkman@frasca.com) */ |
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| 44 | /* Copyright (C) 1998 by Frasca International, Inc. */ |
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| 45 | /* */ |
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| 46 | /* Derived from c/src/lib/libcpu/ppc/ppc403/clock/clock.c: */ |
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| 47 | /* */ |
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| 48 | /* Author: Andrew Bray <andy@i-cubed.co.uk> */ |
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| 49 | /* */ |
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| 50 | /* COPYRIGHT (c) 1995 by i-cubed ltd. */ |
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| 51 | /* */ |
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| 52 | /* To anyone who acknowledges that this file is provided "AS IS" */ |
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| 53 | /* without any express or implied warranty: */ |
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| 54 | /* permission to use, copy, modify, and distribute this file */ |
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| 55 | /* for any purpose is hereby granted without fee, provided that */ |
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| 56 | /* the above copyright notice and this notice appears in all */ |
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| 57 | /* copies, and that the name of i-cubed limited not be used in */ |
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| 58 | /* advertising or publicity pertaining to distribution of the */ |
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| 59 | /* software without specific, written prior permission. */ |
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| 60 | /* i-cubed limited makes no representations about the suitability */ |
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| 61 | /* of this software for any purpose. */ |
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| 62 | /* */ |
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| 63 | /* Derived from c/src/lib/libcpu/hppa1.1/clock/clock.c: */ |
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| 64 | /* */ |
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| 65 | /* Modifications for deriving timer clock from cpu system clock by */ |
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| 66 | /* Thomas Doerfler <td@imd.m.isar.de> */ |
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| 67 | /* for these modifications: */ |
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| 68 | /* COPYRIGHT (c) 1997 by IMD, Puchheim, Germany. */ |
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| 69 | /* */ |
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| 70 | /* COPYRIGHT (c) 1989-1999. */ |
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| 71 | /* On-Line Applications Research Corporation (OAR). */ |
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| 72 | /* */ |
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| 73 | /* The license and distribution terms for this file may be */ |
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| 74 | /* found in the file LICENSE in this distribution or at */ |
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[0332481] | 75 | /* http://www.rtems.com/license/LICENSE. */ |
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[ca680bc5] | 76 | /* */ |
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| 77 | /* Modifications for PPC405GP by Dennis Ehlin */ |
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| 78 | /*---------------------------------------------------------------------*/ |
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| 79 | /* */ |
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| 80 | /* Partially based on the code references which are named above. */ |
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| 81 | /* Adaptions, modifications, enhancements and any recent parts of */ |
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| 82 | /* the code are under the right of */ |
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| 83 | /* */ |
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[a877cc8e] | 84 | /* IPR Engineering, Dachauer StraÃe 38, D-80335 MÃŒnchen */ |
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[ca680bc5] | 85 | /* Copyright(C) 2003 */ |
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| 86 | /* */ |
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| 87 | /*---------------------------------------------------------------------*/ |
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| 88 | /* */ |
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| 89 | /* IPR Engineering makes no representation or warranties with */ |
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| 90 | /* respect to the performance of this computer program, and */ |
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| 91 | /* specifically disclaims any responsibility for any damages, */ |
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| 92 | /* special or consequential, connected with the use of this program. */ |
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| 93 | /* */ |
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| 94 | /*---------------------------------------------------------------------*/ |
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| 95 | /* */ |
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| 96 | /* Version history: 1.0 */ |
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| 97 | /* */ |
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| 98 | /***********************************************************************/ |
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| 99 | |
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[da261595] | 100 | #include <bsp.h> |
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[ca680bc5] | 101 | #include <rtems/bspIo.h> |
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| 102 | #include "../irq/irq.h" |
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| 103 | |
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| 104 | #include <rtems.h> |
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| 105 | #include <rtems/clockdrv.h> |
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| 106 | #include <rtems/libio.h> |
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| 107 | |
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| 108 | #include "../irq/irq.h" |
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| 109 | #include "../include/mpc5200.h" |
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| 110 | #include "../slicetimer/slicetimer.h" |
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| 111 | #include <stdio.h> |
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| 112 | |
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| 113 | uint32_t value0 = 0; |
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| 114 | uint32_t value1 = 0; |
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| 115 | |
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| 116 | /* |
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| 117 | * ISR Handlers |
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| 118 | */ |
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| 119 | void mpc5200_slt_isr(uint32_t slt_no) |
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| 120 | { |
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| 121 | uint32_t status; |
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| 122 | struct mpc5200_slt *slt = (struct mpc5200_slt *)(&mpc5200.slt[slt_no]); |
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| 123 | |
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| 124 | status = slt->tsr; |
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| 125 | |
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| 126 | if(status & SLT_TSR_ST) |
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| 127 | { |
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| 128 | |
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| 129 | slt->tsr |= SLT_TSR_ST; |
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| 130 | |
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| 131 | /*if(slt_no == SLT0) |
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| 132 | slt0_user_defined_handler */ |
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| 133 | |
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| 134 | /*if(slt_no == SLT1) |
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| 135 | slt1_user_defined_handler */ |
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| 136 | |
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| 137 | } |
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| 138 | |
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| 139 | } |
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| 140 | |
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| 141 | |
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| 142 | rtems_isr mpc5200_slt0_isr(rtems_irq_hdl_param unused) |
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| 143 | { |
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| 144 | |
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| 145 | mpc5200_slt_isr(SLT0); |
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| 146 | |
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| 147 | } |
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| 148 | |
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| 149 | |
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| 150 | rtems_isr mpc5200_slt1_isr(rtems_irq_hdl_param unused) |
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| 151 | { |
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| 152 | |
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| 153 | mpc5200_slt_isr(SLT1); |
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| 154 | |
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| 155 | } |
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| 156 | |
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| 157 | |
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| 158 | /* |
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| 159 | * Initialize MPC5x00 slt |
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| 160 | */ |
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| 161 | void mpc5200_init_slt(uint32_t slt_no) |
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| 162 | { |
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| 163 | struct mpc5200_slt *slt = (struct mpc5200_slt *)(&mpc5200.slt[slt_no]); |
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| 164 | |
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| 165 | slt->tsr = SLT_TSR_ST; |
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| 166 | slt->cntrl = SLT_CNTRL_RW; |
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| 167 | |
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| 168 | } |
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| 169 | |
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| 170 | |
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| 171 | /* |
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| 172 | * Set MPC5x00 slt counter |
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| 173 | */ |
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| 174 | void mpc5200_set_slt_count(uint32_t slt_no) |
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| 175 | { |
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| 176 | struct mpc5200_slt *slt = (struct mpc5200_slt *)(&mpc5200.slt[slt_no]); |
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| 177 | |
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| 178 | if(slt_no == SLT0) |
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| 179 | /* Calculate counter value 24 bit (must be greater than 255) => IPB_Clock=33MHz -> Int. every 7,75us - 508ms */ |
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| 180 | if((SLT_TSR_COUNT(SLT0_INT_FREQUENCY) > 0xFF) && (SLT_TSR_COUNT(SLT0_INT_FREQUENCY) < 0x1000000)) |
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| 181 | slt->tcr = SLT_TSR_COUNT(SLT0_INT_FREQUENCY); |
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| 182 | |
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| 183 | if(slt_no == SLT1) |
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| 184 | /* Calculate counter value 24 bit (must be greater than 255) => IPB_Clock=33MHz -> Int. every 7,75us - 508ms */ |
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| 185 | if((SLT_TSR_COUNT(SLT1_INT_FREQUENCY) > 0xFF) && (SLT_TSR_COUNT(SLT1_INT_FREQUENCY) < 0x1000000)) |
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| 186 | slt->tcr = SLT_TSR_COUNT(SLT1_INT_FREQUENCY); |
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| 187 | |
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| 188 | } |
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| 189 | |
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| 190 | |
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| 191 | /* |
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| 192 | * Enable MPC5x00 slt interrupt |
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| 193 | */ |
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| 194 | void mpc5200_enable_slt_int(uint32_t slt_no) |
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| 195 | { |
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| 196 | struct mpc5200_slt *slt = (struct mpc5200_slt *)(&mpc5200.slt[slt_no]); |
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| 197 | |
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| 198 | slt->cntrl |= SLT_CNTRL_TIMEN | SLT_CNTRL_INTEN; |
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| 199 | |
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| 200 | } |
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| 201 | |
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| 202 | |
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| 203 | /* |
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| 204 | * Disable MPC5x00 slt interrupt |
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| 205 | */ |
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| 206 | void mpc5200_disable_slt_int(uint32_t slt_no) |
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| 207 | { |
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| 208 | struct mpc5200_slt *slt = (struct mpc5200_slt *)(&mpc5200.slt[slt_no]); |
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| 209 | |
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| 210 | slt->cntrl &= ~(SLT_CNTRL_TIMEN | SLT_CNTRL_INTEN); |
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| 211 | |
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| 212 | } |
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| 213 | |
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| 214 | |
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| 215 | /* |
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| 216 | * Check MPC5x00 slt status |
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| 217 | */ |
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| 218 | uint32_t mpc5200_check_slt_status(uint32_t slt_no) |
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| 219 | { |
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| 220 | struct mpc5200_slt *slt = (struct mpc5200_slt *)(&mpc5200.slt[slt_no]); |
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| 221 | |
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| 222 | if(((slt->cntrl) & (SLT_CNTRL_TIMEN | SLT_CNTRL_INTEN)) == (SLT_CNTRL_TIMEN | SLT_CNTRL_INTEN)) |
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| 223 | return 1; |
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| 224 | else |
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| 225 | return 0; |
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| 226 | |
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| 227 | } |
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| 228 | |
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| 229 | /* |
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| 230 | * switch MPC5x00 slt on |
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| 231 | */ |
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| 232 | void sltOn(const rtems_irq_connect_data* irq) |
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| 233 | { |
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| 234 | uint32_t slt_no = 0; |
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| 235 | |
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| 236 | if((irq->name) == BSP_SIU_IRQ_SL_TIMER0) |
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| 237 | slt_no = 0; |
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| 238 | |
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| 239 | if((irq->name) == BSP_SIU_IRQ_SL_TIMER1) |
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| 240 | slt_no = 1; |
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| 241 | |
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| 242 | mpc5200_set_slt_count((uint32_t)slt_no); |
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| 243 | mpc5200_enable_slt_int((uint32_t)slt_no); |
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| 244 | |
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| 245 | } |
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| 246 | |
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| 247 | /* |
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| 248 | * switch MPC5x00 slt off |
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| 249 | */ |
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| 250 | void sltOff(const rtems_irq_connect_data* irq) |
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| 251 | { |
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| 252 | uint32_t slt_no = 0; |
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| 253 | |
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| 254 | if((irq->name) == BSP_SIU_IRQ_SL_TIMER0) |
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| 255 | slt_no = 0; |
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| 256 | |
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| 257 | if((irq->name) == BSP_SIU_IRQ_SL_TIMER1) |
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| 258 | slt_no = 1; |
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| 259 | |
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| 260 | mpc5200_disable_slt_int((uint32_t)slt_no); |
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| 261 | |
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| 262 | } |
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| 263 | |
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| 264 | /* |
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| 265 | * get status of MPC5x00 slt |
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| 266 | */ |
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| 267 | int sltIsOn(const rtems_irq_connect_data* irq) |
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| 268 | { |
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| 269 | uint32_t slt_no = 0; |
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| 270 | |
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| 271 | if((irq->name) == BSP_SIU_IRQ_SL_TIMER0) |
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| 272 | slt_no = 0; |
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| 273 | |
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| 274 | if((irq->name) == BSP_SIU_IRQ_SL_TIMER1) |
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| 275 | slt_no = 1; |
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| 276 | |
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| 277 | if(mpc5200_check_slt_status(slt_no)) |
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| 278 | return 1; |
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| 279 | else |
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| 280 | return 0; |
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| 281 | } |
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| 282 | |
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| 283 | /* |
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| 284 | * MPC5x00 slt0 irq connect data |
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| 285 | */ |
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| 286 | static rtems_irq_connect_data slt0_IrqData = |
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| 287 | { |
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| 288 | BSP_SIU_IRQ_SL_TIMER0, |
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| 289 | mpc5200_slt0_isr, |
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| 290 | (rtems_irq_hdl_param) NULL, |
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| 291 | (rtems_irq_enable)sltOn, |
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| 292 | (rtems_irq_disable)sltOff, |
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| 293 | (rtems_irq_is_enabled)sltIsOn |
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| 294 | }; |
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| 295 | |
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| 296 | /* |
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| 297 | * MPC5x00 slt1 irq connect data |
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| 298 | */ |
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| 299 | static rtems_irq_connect_data slt1_IrqData = |
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| 300 | { |
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| 301 | BSP_SIU_IRQ_SL_TIMER1, |
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| 302 | mpc5200_slt1_isr, |
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| 303 | (rtems_irq_hdl_param) NULL, |
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| 304 | (rtems_irq_enable)sltOn, |
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| 305 | (rtems_irq_disable)sltOff, |
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| 306 | (rtems_irq_is_enabled)sltIsOn |
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| 307 | }; |
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| 308 | |
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| 309 | /* |
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| 310 | * call MPC5x00 slt install routines |
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| 311 | */ |
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| 312 | void Install_slt(rtems_device_minor_number slt_no) |
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| 313 | { |
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| 314 | |
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| 315 | mpc5200_init_slt((uint32_t)slt_no); |
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| 316 | mpc5200_set_slt_count((uint32_t)slt_no); |
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| 317 | |
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| 318 | } |
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| 319 | |
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| 320 | /* |
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| 321 | * MPC5x00 slt device driver initialize |
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| 322 | */ |
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| 323 | rtems_device_driver slt_initialize |
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| 324 | ( |
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| 325 | rtems_device_major_number major, |
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| 326 | rtems_device_minor_number minor, |
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| 327 | void *pargp |
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| 328 | ) |
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| 329 | { |
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| 330 | |
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| 331 | /* force minor according to definitions in bsp.h */ |
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| 332 | if(USE_SLICETIMER_0) |
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| 333 | { |
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| 334 | |
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| 335 | Install_slt(0); |
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| 336 | |
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| 337 | if(!BSP_install_rtems_irq_handler(&slt0_IrqData)) |
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| 338 | { |
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| 339 | |
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| 340 | printk("Unable to connect PSC Irq handler\n"); |
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| 341 | rtems_fatal_error_occurred(1); |
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| 342 | |
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| 343 | } |
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| 344 | |
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| 345 | } |
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| 346 | |
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| 347 | if(USE_SLICETIMER_1) |
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| 348 | { |
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| 349 | |
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| 350 | Install_slt(1); |
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| 351 | |
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| 352 | if(!BSP_install_rtems_irq_handler(&slt1_IrqData)) |
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| 353 | { |
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| 354 | |
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| 355 | printk("Unable to connect PSC Irq handler\n"); |
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| 356 | rtems_fatal_error_occurred(1); |
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| 357 | |
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| 358 | } |
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| 359 | |
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| 360 | } |
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| 361 | |
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| 362 | return RTEMS_SUCCESSFUL; |
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| 363 | |
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| 364 | } |
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| 365 | |
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