1 | /*===============================================================*\ |
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2 | | Project: RTEMS generic MPC5200 BSP | |
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3 | +-----------------------------------------------------------------+ |
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4 | | Partially based on the code references which are named below. | |
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5 | | Adaptions, modifications, enhancements and any recent parts of | |
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6 | | the code are: | |
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7 | | Copyright (c) 2005 | |
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8 | | Embedded Brains GmbH | |
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9 | | Obere Lagerstr. 30 | |
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10 | | D-82178 Puchheim | |
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11 | | Germany | |
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12 | | rtems@embedded-brains.de | |
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13 | +-----------------------------------------------------------------+ |
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14 | | The license and distribution terms for this file may be | |
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15 | | found in the file LICENSE in this distribution or at | |
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16 | | | |
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17 | | http://www.rtems.com/license/LICENSE. | |
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18 | | | |
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19 | +-----------------------------------------------------------------+ |
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20 | | this file contains definitions for the M93Cxx EEPROM devices | |
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21 | \*===============================================================*/ |
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22 | /***********************************************************************/ |
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23 | /* */ |
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24 | /* Module: m93cxx.h */ |
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25 | /* Date: 07/17/2003 */ |
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26 | /* Purpose: RTEMS M93C64-based header file */ |
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27 | /* */ |
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28 | /*---------------------------------------------------------------------*/ |
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29 | /* */ |
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30 | /* Description: M93C46 is a serial microwire EEPROM which contains */ |
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31 | /* 1Kbit (128 bytes/64 words) of non-volatile memory. */ |
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32 | /* The device can be configured for byte- or word- */ |
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33 | /* access. The driver provides a file-like interface */ |
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34 | /* to this memory. */ |
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35 | /* */ |
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36 | /* MPC5x00 PIN settings: */ |
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37 | /* */ |
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38 | /* PSC3_6 (output) -> MC93C46 serial data in (D) */ |
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39 | /* PSC3_7 (input) -> MC93C46 serial data out (Q) */ |
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40 | /* PSC3_8 (output) -> MC93C46 chip select input (S) */ |
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41 | /* PSC3_9 (output) -> MC93C46 serial clock (C) */ |
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42 | /* */ |
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43 | /*---------------------------------------------------------------------*/ |
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44 | /* */ |
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45 | /* Code */ |
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46 | /* References: none */ |
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47 | /* Module: */ |
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48 | /* Project: */ |
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49 | /* Version */ |
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50 | /* Date: */ |
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51 | /* Author: */ |
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52 | /* Copyright: */ |
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53 | /* */ |
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54 | /*---------------------------------------------------------------------*/ |
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55 | /* */ |
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56 | /* Partially based on the code references which are named above. */ |
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57 | /* Adaptions, modifications, enhancements and any recent parts of */ |
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58 | /* the code are under the right of */ |
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59 | /* */ |
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60 | /* IPR Engineering, Dachauer Straße 38, D-80335 München */ |
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61 | /* Copyright(C) 2003 */ |
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62 | /* */ |
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63 | /*---------------------------------------------------------------------*/ |
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64 | /* */ |
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65 | /* IPR Engineering makes no representation or warranties with */ |
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66 | /* respect to the performance of this computer program, and */ |
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67 | /* specifically disclaims any responsibility for any damages, */ |
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68 | /* special or consequential, connected with the use of this program. */ |
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69 | /* */ |
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70 | /*---------------------------------------------------------------------*/ |
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71 | /* */ |
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72 | /* Version history: 1.0 */ |
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73 | /* */ |
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74 | /***********************************************************************/ |
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75 | |
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76 | #ifndef __M93CXX_H__ |
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77 | #define __M93CXX_H__ |
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78 | |
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79 | #ifdef __cplusplus |
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80 | extern "C" { |
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81 | #endif |
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82 | |
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83 | static void m93cxx_enable_write(void); |
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84 | static void m93cxx_disable_write(void); |
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85 | static void m93cxx_write_byte(uint32_t, uint8_t); |
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86 | static uint8_t m93cxx_read_byte(uint32_t); |
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87 | void wait_usec(unsigned long); |
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88 | |
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89 | #define M93CXX_MODE_WORD |
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90 | /*#define M93C46_MODE_BYTE*/ |
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91 | #define M93C46 |
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92 | #define M93C46_NVRAM_SIZE 128 |
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93 | |
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94 | #define GPIO_PSC3_6 (1 << 12) |
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95 | #define GPIO_PSC3_7 (1 << 13) |
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96 | #define GPIO_PSC3_8 (1 << 26) |
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97 | #define GPIO_PSC3_9 (1 << 26) |
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98 | |
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99 | #define START_BIT 0x1 |
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100 | #define EWDS_OPCODE 0x0 |
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101 | #define WRAL_OPCODE 0x1 |
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102 | #define ERAL_OPCODE 0x2 |
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103 | #define EWEN_OPCODE 0x3 |
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104 | #define WRITE_OPCODE 0x4 |
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105 | #define READ_OPCODE 0x8 |
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106 | #define ERASE_OPCODE 0xC |
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107 | |
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108 | #define WAIT(i) wait_usec(i) |
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109 | |
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110 | #define ENABLE_CHIP_SELECT mpc5200.gpiosido |= GPIO_PSC3_8 |
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111 | #define DISABLE_CHIP_SELECT mpc5200.gpiosido &= ~GPIO_PSC3_8 |
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112 | #define SET_DATA_BIT_HIGH mpc5200.gpiosdo |= GPIO_PSC3_6 |
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113 | #define SET_DATA_BIT_LOW mpc5200.gpiosdo &= ~GPIO_PSC3_6 |
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114 | |
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115 | #ifdef M93CXX_MODE_BYTE |
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116 | #define GET_DATA_BYTE_SHIFT(val) ((val) |= ((mpc5200.gpiosdi & GPIO_PSC3_7) >> 13)); \ |
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117 | ((val) <<= 1) |
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118 | #define SET_DATA_BYTE_SHIFT(val) (((val) & 0x80) ? (mpc5200.gpiosdo |= GPIO_PSC3_6) : (mpc5200.gpiosdo &= ~GPIO_PSC3_6)); \ |
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119 | ((val) <<= 1) |
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120 | #else |
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121 | #define GET_DATA_WORD_SHIFT(val) ((val) |= ((mpc5200.gpiosdi & GPIO_PSC3_7) >> 13)); \ |
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122 | ((val) <<= 1) |
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123 | #define SET_DATA_WORD_SHIFT(val) (((val) & 0x8000) ? (mpc5200.gpiosdo |= GPIO_PSC3_6) : (mpc5200.gpiosdo &= ~GPIO_PSC3_6)); \ |
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124 | ((val) <<= 1) |
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125 | #endif |
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126 | |
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127 | #define MASK_HEAD_SHIFT(head) ((((head) & 0x80000000) >> 31) ? (mpc5200.gpiosdo |= GPIO_PSC3_6) : (mpc5200.gpiosdo &= ~GPIO_PSC3_6)); \ |
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128 | ((head) <<= 1) |
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129 | #define DO_CLOCK_CYCLE mpc5200.gpiowdo |= GPIO_PSC3_9; \ |
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130 | WAIT(1000); \ |
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131 | mpc5200.gpiowdo &= ~GPIO_PSC3_9 |
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132 | #define CHECK_WRITE_BUSY while(!(mpc5200.gpiosdi & GPIO_PSC3_7)) |
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133 | |
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134 | |
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135 | #ifdef M93CXX_MODE_BYTE |
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136 | #ifdef M93C46 |
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137 | #define M93C46_EWDS ((START_BIT << 31) | (EWDS_OPCODE << 27)) |
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138 | #define M93C46_WRAL ((START_BIT << 31) | (WRAL_OPCODE << 27)) |
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139 | #define M93C46_ERAL ((START_BIT << 31) | (ERAL_OPCODE << 27)) |
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140 | #define M93C46_EWEN ((START_BIT << 31) | (EWEN_OPCODE << 27)) |
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141 | #define M93C46_READ(addr) ((START_BIT << 31) | (READ_OPCODE << 27) | ((addr) << 22)) |
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142 | #define M93C46_WRITE(addr) ((START_BIT << 31) | (WRITE_OPCODE << 27) | ((addr) << 22)) |
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143 | #define M93C46_ERASE(addr) ((START_BIT << 31) | (ERASE_OPCODE << 27) | ((addr) << 22)) |
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144 | #define M93C46_CLOCK_CYCLES 10 |
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145 | #endif |
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146 | #else |
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147 | #ifdef M93C46 |
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148 | #define M93C46_EWDS ((START_BIT << 31) | (EWDS_OPCODE << 27)) |
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149 | #define M93C46_WRAL ((START_BIT << 31) | (WRAL_OPCODE << 27)) |
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150 | #define M93C46_ERAL ((START_BIT << 31) | (ERAL_OPCODE << 27)) |
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151 | #define M93C46_EWEN ((START_BIT << 31) | (EWEN_OPCODE << 27)) |
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152 | #define M93C46_READ(addr) ((START_BIT << 31) | (READ_OPCODE << 27) | ((addr) << 23)) |
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153 | #define M93C46_WRITE(addr) ((START_BIT << 31) | (WRITE_OPCODE << 27) | ((addr) << 23)) |
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154 | #define M93C46_ERASE(addr) ((START_BIT << 31) | (ERASE_OPCODE << 27) | ((addr) << 23)) |
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155 | #define M93C46_CLOCK_CYCLES 9 |
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156 | #endif |
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157 | #endif |
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158 | |
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159 | #ifdef __cplusplus |
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160 | } |
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161 | #endif |
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162 | |
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163 | #endif /* __M93CXX_H__ */ |
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