| 1 | /*===============================================================*\ |
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| 2 | | Project: RTEMS generic MPC5200 BSP | |
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| 3 | +-----------------------------------------------------------------+ |
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| 4 | | Partially based on the code references which are named below. | |
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| 5 | | Adaptions, modifications, enhancements and any recent parts of | |
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| 6 | | the code are: | |
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| 7 | | Copyright (c) 2005 | |
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| 8 | | Embedded Brains GmbH | |
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| 9 | | Obere Lagerstr. 30 | |
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| 10 | | D-82178 Puchheim | |
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| 11 | | Germany | |
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| 12 | | rtems@embedded-brains.de | |
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| 13 | +-----------------------------------------------------------------+ |
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| 14 | | The license and distribution terms for this file may be | |
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| 15 | | found in the file LICENSE in this distribution or at | |
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| 16 | | | |
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| 17 | | http://www.rtems.com/license/LICENSE. | |
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| 18 | | | |
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| 19 | +-----------------------------------------------------------------+ |
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| 20 | | this file declares stuff for the mscan driver | |
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| 21 | \*===============================================================*/ |
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| 22 | #ifndef __MSCAN_H__ |
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| 23 | #define __MSCAN_H__ |
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| 24 | |
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| 25 | #ifdef __cplusplus |
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| 26 | extern "C" { |
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| 27 | #endif |
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| 28 | |
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| 29 | #define MIN_NO_OF_TQ 7 |
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| 30 | #define NO_OF_TABLE_ENTRIES 4 |
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| 31 | #define TSEG_1 1 |
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| 32 | #define TSEG_2 2 |
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| 33 | #define SJW 3 |
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| 34 | |
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| 35 | #define MSCAN_MAX_DATA_BYTES 8 |
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| 36 | #define MSCAN_RX_BUFF_NUM 4 |
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| 37 | #define MSCAN_TX_BUFF_NUM 3 |
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| 38 | |
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| 39 | |
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| 40 | #define MSCAN_A_DEV_NAME "/dev/mscana" |
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| 41 | #define MSCAN_B_DEV_NAME "/dev/mscanb" |
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| 42 | #define MSCAN_0_DEV_NAME "/dev/mscan0" |
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| 43 | #define MSCAN_1_DEV_NAME "/dev/mscan1" |
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| 44 | #define MSCAN_A 0 |
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| 45 | #define MSCAN_B 1 |
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| 46 | |
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| 47 | #define MSCAN_NON_INITIALIZED_MODE 0 |
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| 48 | #define MSCAN_INITIALIZED_MODE 1 |
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| 49 | #define MSCAN_INIT_NORMAL_MODE 2 |
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| 50 | #define MSCAN_NORMAL_MODE 4 |
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| 51 | #define MSCAN_SLEEP_MODE 8 |
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| 52 | |
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| 53 | #define CAN_BIT_RATE_MAX 1000000 |
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| 54 | #define CAN_BIT_RATE_MIN 100000 |
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| 55 | |
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| 56 | #define CAN_BIT_RATE 100000 |
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| 57 | #define CAN_MAX_NO_OF_TQ 25 |
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| 58 | #define CAN_MAX_NO_OF_TQ_TSEG1 15 |
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| 59 | #define CAN_MAX_NO_OF_TQ_TSEG2 7 |
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| 60 | #define CAN_MAX_NO_OF_TQ_SJW 2 |
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| 61 | |
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| 62 | #define MSCAN_SET_RX_ID 1 |
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| 63 | #define MSCAN_GET_RX_ID 2 |
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| 64 | #define MSCAN_SET_RX_ID_MASK 3 |
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| 65 | #define MSCAN_GET_RX_ID_MASK 4 |
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| 66 | #define MSCAN_SET_TX_ID 5 |
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| 67 | #define MSCAN_GET_TX_ID 6 |
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| 68 | |
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| 69 | #define TOUCAN_MSCAN_INIT 7 |
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| 70 | #define MSCAN_SET_BAUDRATE 8 |
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| 71 | #define SET_TX_BUF_NO 9 |
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| 72 | |
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| 73 | #define MSCAN_RX_BUFF_NOACTIVE (0 << 4) |
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| 74 | #define MSCAN_RX_BUFF_EMPTY (1 << 6) |
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| 75 | #define MSCAN_RX_BUFF_FULL (1 << 5) |
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| 76 | #define MSCAN_RX_BUFF_OVERRUN ((MSCAN_RX_BUFF_EMPTY) | (MSCAN_RX_BUFF_FULL)) |
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| 77 | #define MSCAN_RX_BUFF_BUSY (1 << 4) |
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| 78 | |
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| 79 | #define MSCAN_MBUFF_MASK 0x07 |
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| 80 | |
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| 81 | #define MSCAN_TX_BUFF0 (1 << 0) |
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| 82 | #define MSCAN_TX_BUFF1 (1 << 1) |
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| 83 | #define MSCAN_TX_BUFF2 (1 << 2) |
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| 84 | |
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| 85 | #define MSCAN_IDE (1 << 0) |
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| 86 | #define MSCAN_RTR (1 << 1) |
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| 87 | #define MSCAN_READ_RXBUFF_0 (1 << 2) |
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| 88 | #define MSCAN_READ_RXBUFF_1 (1 << 2) |
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| 89 | #define MSCAN_READ_RXBUFF_2 (1 << 2) |
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| 90 | #define MSCAN_READ_RXBUFF_3 (1 << 2) |
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| 91 | |
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| 92 | #define CTL0_RXFRM (1 << 7) |
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| 93 | #define CTL0_RXACT (1 << 6) |
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| 94 | #define CTL0_CSWAI (1 << 5) |
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| 95 | #define CTL0_SYNCH (1 << 4) |
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| 96 | #define CTL0_TIME (1 << 3) |
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| 97 | #define CTL0_WUPE (1 << 2) |
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| 98 | #define CTL0_SLPRQ (1 << 1) |
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| 99 | #define CTL0_INITRQ (1 << 0) |
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| 100 | |
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| 101 | #define CTL1_CANE (1 << 7) |
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| 102 | #define CTL1_CLKSRC (1 << 6) |
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| 103 | #define CTL1_LOOPB (1 << 5) |
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| 104 | #define CTL1_LISTEN (1 << 4) |
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| 105 | #define CTL1_WUPM (1 << 2) |
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| 106 | #define CTL1_SLPAK (1 << 1) |
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| 107 | #define CTL1_INITAK (1 << 0) |
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| 108 | |
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| 109 | #define BTR0_SJW(btr0) ((btr0) << 6) |
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| 110 | #define BTR0_BRP(btr0) ((btr0) << 0) |
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| 111 | |
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| 112 | #define BTR1_SAMP (1 << 7) |
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| 113 | #define BTR1_TSEG_22_20(btr1) ((btr1) << 4) |
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| 114 | #define BTR1_TSEG_13_10(btr1) ((btr1) << 0) |
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| 115 | |
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| 116 | #define RFLG_WUPIF (1 << 7) |
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| 117 | #define RFLG_CSCIF (1 << 6) |
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| 118 | #define RFLG_RSTAT (3 << 4) |
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| 119 | #define RFLG_TSTAT (3 << 2) |
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| 120 | #define RFLG_OVRIF (1 << 1) |
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| 121 | #define RFLG_RXF (1 << 0) |
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| 122 | #define RFLG_GET_RX_STATE(rflg) (((rflg) >> 4) & 0x03) |
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| 123 | #define RFLG_GET_TX_STATE(rflg) (((rflg) >> 2) & 0x03) |
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| 124 | |
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| 125 | #define MSCAN_STATE_OK 0 |
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| 126 | #define MSCAN_STATE_ERR 1 |
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| 127 | #define MSCAN_STATE_WRN 2 |
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| 128 | #define MSCAN_STATE_BUSOFF 3 |
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| 129 | |
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| 130 | #define RIER_WUPIE (1 << 7) |
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| 131 | #define RIER_CSCIE (1 << 6) |
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| 132 | #define RIER_RSTAT(rier) ((rier) << 4) |
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| 133 | #define RIER_TSTAT(rier) ((rier) << 2) |
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| 134 | #define RIER_OVRIE (1 << 1) |
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| 135 | #define RIER_RXFIE (1 << 0) |
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| 136 | |
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| 137 | #define TFLG_TXE2 (1 << 2) |
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| 138 | #define TFLG_TXE1 (1 << 1) |
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| 139 | #define TFLG_TXE0 (1 << 0) |
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| 140 | |
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| 141 | #define TIER_TXEI2 (1 << 2) |
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| 142 | #define TIER_TXEI1 (1 << 1) |
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| 143 | #define TIER_TXEI0 (1 << 0) |
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| 144 | |
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| 145 | #define TARQ_ABTRQ2 (1 << 2) |
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| 146 | #define TARQ_ABTRQ1 (1 << 1) |
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| 147 | #define TARQ_ABTRQ0 (1 << 0) |
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| 148 | |
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| 149 | #define TAAK_ABTRQ2 (1 << 2) |
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| 150 | #define TAAK_ABTRQ1 (1 << 1) |
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| 151 | #define TAAK_ABTRQ0 (1 << 0) |
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| 152 | |
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| 153 | #define BSEL_TX2 (1 << 2) |
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| 154 | #define BSEL_TX1 (1 << 1) |
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| 155 | #define BSEL_TX0 (1 << 0) |
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| 156 | |
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| 157 | #define IDAC_IDAM1 (1 << 5) |
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| 158 | #define IDAC_IDAM0 (1 << 4) |
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| 159 | #define IDAC_IDHIT(idac) ((idac) & 0x7) |
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| 160 | |
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| 161 | #define TX_MBUF_SEL(buf_no) (1 << (buf_no)) |
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| 162 | #define TX_DATA_LEN(len) ((len) & 0x0F) |
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| 163 | |
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| 164 | #define TX_MBUF_EMPTY(val) (1 << (val)) |
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| 165 | |
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| 166 | #define TXIDR1_IDE (1 << 3) |
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| 167 | #define TXIDR1_SRR (1 << 4) |
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| 168 | |
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| 169 | #define TXIDR3_RTR (1 << 0) |
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| 170 | #define TXIDR1_RTR (1 << 4) |
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| 171 | |
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| 172 | #define RXIDR1_IDE (1 << 3) |
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| 173 | #define RXIDR1_SRR (1 << 4) |
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| 174 | |
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| 175 | #define RXIDR3_RTR (1 << 0) |
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| 176 | #define RXIDR1_RTR (1 << 4) |
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| 177 | |
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| 178 | #define SET_IDR0(u16) ((uint8_t)((u16) >> 3)) |
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| 179 | #define SET_IDR1(u16) ((uint8_t)(((u16) & 0x0007) << 5)) |
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| 180 | |
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| 181 | #define SET_IDR2(u16) SET_IDR0(u16) |
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| 182 | #define SET_IDR3(u16) SET_IDR1(u16) |
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| 183 | |
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| 184 | #define SET_IDR4(u16) SET_IDR0(u16) |
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| 185 | #define SET_IDR5(u16) SET_IDR1(u16) |
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| 186 | |
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| 187 | #define SET_IDR6(u16) SET_IDR0(u16) |
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| 188 | #define SET_IDR7(u16) SET_IDR1(u16) |
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| 189 | |
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| 190 | #define GET_IDR0(u16) ((uint16_t) ((u16) << 3)) |
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| 191 | #define GET_IDR1(u16) ((uint16_t)(((u16) >> 5)&0x0007)) |
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| 192 | |
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| 193 | #define GET_IDR2(u16) GET_IDR0(u16) |
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| 194 | #define GET_IDR3(u16) GET_IDR1(u16) |
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| 195 | |
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| 196 | #define GET_IDR4(u16) GET_IDR0(u16) |
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| 197 | #define GET_IDR5(u16) GET_IDR1(u16) |
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| 198 | |
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| 199 | #define GET_IDR6(u16) GET_IDR0(u16) |
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| 200 | #define GET_IDR7(u16) GET_IDR1(u16) |
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| 201 | |
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| 202 | #define SET_IDMR0(u16) ((uint8_t)((u16) >> 3)) |
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| 203 | #define SET_IDMR1(u16) ((uint8_t)((((u16) & 0x0007) << 5))|0x001F) |
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| 204 | |
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| 205 | #define SET_IDMR2(u16) SET_IDMR0(u16) |
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| 206 | #define SET_IDMR3(u16) SET_IDMR1(u16) |
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| 207 | |
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| 208 | #define SET_IDMR4(u16) SET_IDMR0(u16) |
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| 209 | #define SET_IDMR5(u16) SET_IDMR1(u16) |
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| 210 | |
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| 211 | #define SET_IDMR6(u16) SET_IDMR0(u16) |
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| 212 | #define SET_IDMR7(u16) SET_IDMR1(u16) |
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| 213 | |
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| 214 | #define GET_IDMR0(u16) ((uint16_t) ((u16) << 3)) |
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| 215 | #define GET_IDMR1(u16) ((uint16_t)(((u16) >> 5)&0x0007)) |
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| 216 | |
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| 217 | #define GET_IDMR2(u16) GET_IDMR0(u16) |
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| 218 | #define GET_IDMR3(u16) GET_IDMR1(u16) |
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| 219 | |
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| 220 | #define GET_IDMR4(u16) GET_IDMR0(u16) |
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| 221 | #define GET_IDMR5(u16) GET_IDMR1(u16) |
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| 222 | |
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| 223 | #define GET_IDMR6(u16) GET_IDMR0(u16) |
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| 224 | #define GET_IDMR7(u16) GET_IDMR1(u16) |
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| 225 | |
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| 226 | #define NO_OF_MSCAN_RX_BUFF 20 |
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| 227 | #define MSCAN_MESSAGE_SIZE(size) (((size)%CPU_ALIGNMENT) ? (((size) + CPU_ALIGNMENT)-((size) + CPU_ALIGNMENT)%CPU_ALIGNMENT) : (size)) |
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| 228 | |
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| 229 | #define TX_BUFFER_0 0 |
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| 230 | #define TX_BUFFER_1 1 |
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| 231 | #define TX_BUFFER_2 2 |
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| 232 | |
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| 233 | #define RX_BUFFER_0 0 |
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| 234 | #define RX_BUFFER_1 1 |
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| 235 | #define RX_BUFFER_2 2 |
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| 236 | #define RX_BUFFER_3 3 |
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| 237 | |
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| 238 | #define NO_OF_MSCAN_TX_BUFF 20 |
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| 239 | #define RING_BUFFER_EMPTY(rbuff) ((((rbuff)->head) == ((rbuff)->tail)) ? TRUE : FALSE) |
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| 240 | #define RING_BUFFER_FULL(rbuff) ((((rbuff)->head) == ((rbuff)->tail)) ? TRUE : FALSE) |
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| 241 | |
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| 242 | |
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| 243 | typedef struct _mscan_handle |
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| 244 | { |
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| 245 | uint8_t mscan_channel; |
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| 246 | void (*toucan_callback)(int16_t); |
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| 247 | } mscan_handle; |
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| 248 | |
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| 249 | struct can_message |
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| 250 | { |
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| 251 | /* uint16_t mess_len; */ |
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| 252 | uint16_t mess_id; |
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| 253 | uint16_t mess_time_stamp; |
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| 254 | uint8_t mess_data[MSCAN_MAX_DATA_BYTES]; |
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| 255 | uint8_t mess_len; |
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| 256 | uint32_t toucan_tx_id; |
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| 257 | }; |
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| 258 | |
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| 259 | volatile struct ring_buf |
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| 260 | { |
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| 261 | volatile struct can_message *buf_ptr; |
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| 262 | volatile struct can_message *head_ptr; |
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| 263 | volatile struct can_message *tail_ptr; |
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| 264 | }; |
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| 265 | |
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| 266 | struct mpc5200_rx_cntrl |
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| 267 | { |
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| 268 | struct can_message can_rx_message[MSCAN_RX_BUFF_NUM]; |
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| 269 | }; |
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| 270 | |
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| 271 | struct mscan_channel_info |
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| 272 | { |
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| 273 | volatile struct mpc5200_mscan *regs; |
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| 274 | uint32_t int_rx_err; |
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| 275 | rtems_id rx_qid; |
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| 276 | uint32_t rx_qname; |
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| 277 | rtems_id tx_rb_sid; |
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| 278 | uint32_t tx_rb_sname; |
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| 279 | uint8_t id_extended; |
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| 280 | uint8_t mode; |
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| 281 | uint8_t tx_buf_no; |
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| 282 | volatile struct ring_buf tx_ring_buf; |
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| 283 | }; |
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| 284 | |
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| 285 | struct mscan_rx_parms |
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| 286 | { |
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| 287 | struct can_message *rx_mess; |
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| 288 | uint32_t rx_timeout; |
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| 289 | uint8_t rx_flags; |
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| 290 | }; |
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| 291 | |
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| 292 | struct mscan_tx_parms |
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| 293 | { |
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| 294 | struct can_message *tx_mess; |
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| 295 | uint32_t tx_id; |
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| 296 | }; |
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| 297 | |
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| 298 | struct mscan_ctrl_parms |
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| 299 | { |
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| 300 | uint32_t ctrl_id; |
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| 301 | uint32_t ctrl_id_mask; |
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| 302 | uint8_t ctrl_reg_no; |
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| 303 | uint8_t ctrl_tx_buf_no; |
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| 304 | uint32_t ctrl_can_bitrate; |
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| 305 | void (*toucan_cb_fnc)(int16_t); |
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| 306 | }; |
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| 307 | |
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| 308 | |
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| 309 | extern void CanInterrupt_A(int16_t); |
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| 310 | extern void CanInterrupt_B(int16_t); |
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| 311 | |
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| 312 | |
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| 313 | rtems_device_driver mscan_initialize( rtems_device_major_number, |
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| 314 | rtems_device_minor_number, |
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| 315 | void * |
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| 316 | ); |
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| 317 | |
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| 318 | rtems_device_driver mscan_open( rtems_device_major_number, |
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| 319 | rtems_device_minor_number, |
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| 320 | void * |
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| 321 | ); |
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| 322 | |
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| 323 | rtems_device_driver mscan_close( rtems_device_major_number, |
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| 324 | rtems_device_minor_number, |
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| 325 | void * |
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| 326 | ); |
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| 327 | |
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| 328 | rtems_device_driver mscan_read( rtems_device_major_number, |
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| 329 | rtems_device_minor_number, |
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| 330 | void * |
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| 331 | ); |
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| 332 | |
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| 333 | rtems_device_driver mscan_write( rtems_device_major_number, |
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| 334 | rtems_device_minor_number, |
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| 335 | void * |
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| 336 | ); |
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| 337 | |
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| 338 | rtems_device_driver mscan_control( rtems_device_major_number, |
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| 339 | rtems_device_minor_number, |
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| 340 | void * |
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| 341 | ); |
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| 342 | |
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| 343 | |
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| 344 | #define MSCAN_DRIVER_TABLE_ENTRY \ |
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| 345 | { mscan_initialize, mscan_open, mscan_close, \ |
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| 346 | mscan_read, mscan_write, mscan_control } |
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| 347 | |
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| 348 | /*MSCAN driver internal functions */ |
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| 349 | void mscan_hardware_initialize(rtems_device_major_number, uint32_t, void *); |
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| 350 | void mpc5200_mscan_int_enable(volatile struct mpc5200_mscan *); |
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| 351 | void mpc5200_mscan_int_disable(volatile struct mpc5200_mscan *); |
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| 352 | void mpc5200_mscan_enter_sleep_mode(volatile struct mpc5200_mscan *); |
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| 353 | void mpc5200_mscan_exit_sleep_mode(volatile struct mpc5200_mscan *); |
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| 354 | void mpc5200_mscan_enter_init_mode(volatile struct mpc5200_mscan *); |
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| 355 | void mpc5200_mscan_exit_init_mode(volatile struct mpc5200_mscan *); |
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| 356 | void mpc5200_mscan_wait_sync(volatile struct mpc5200_mscan *); |
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| 357 | void mpc5200_mscan_perform_init_mode_settings(volatile struct mpc5200_mscan *); |
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| 358 | void mpc5200_mscan_perform_normal_mode_settings(volatile struct mpc5200_mscan *); |
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| 359 | rtems_status_code mpc5200_mscan_set_mode(rtems_device_minor_number, uint8_t); |
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| 360 | rtems_status_code mscan_channel_initialize(rtems_device_major_number, rtems_device_minor_number); |
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| 361 | uint8_t prescaler_calculation(uint32_t, uint32_t, uint8_t *); |
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| 362 | void mpc5200_mscan_perform_bit_time_settings(volatile struct mpc5200_mscan *, uint32_t, uint32_t); |
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| 363 | |
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| 364 | |
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| 365 | #ifdef __cplusplus |
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| 366 | } |
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| 367 | #endif |
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| 368 | |
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| 369 | #endif /* __MSCAN_H__ */ |
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