1 | /*===============================================================*\ |
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2 | | Project: RTEMS generic MPC5200 BSP | |
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3 | +-----------------------------------------------------------------+ |
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4 | | Partially based on the code references which are named below. | |
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5 | | Adaptions, modifications, enhancements and any recent parts of | |
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6 | | the code are: | |
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7 | | Copyright (c) 2005 | |
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8 | | Embedded Brains GmbH | |
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9 | | Obere Lagerstr. 30 | |
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10 | | D-82178 Puchheim | |
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11 | | Germany | |
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12 | | rtems@embedded-brains.de | |
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13 | +-----------------------------------------------------------------+ |
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14 | | The license and distribution terms for this file may be | |
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15 | | found in the file LICENSE in this distribution or at | |
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16 | | | |
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17 | | http://www.rtems.com/license/LICENSE. | |
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18 | | | |
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19 | +-----------------------------------------------------------------+ |
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20 | | this file contains the IRQ controller/system initialization | |
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21 | \*===============================================================*/ |
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22 | /***********************************************************************/ |
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23 | /* */ |
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24 | /* Module: irq_init.c */ |
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25 | /* Date: 07/17/2003 */ |
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26 | /* Purpose: RTEMS MPC5x00 CPU interrupt initialization */ |
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27 | /* */ |
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28 | /*---------------------------------------------------------------------*/ |
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29 | /* */ |
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30 | /* Description: This file contains the implementation of rtems */ |
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31 | /* initialization related to interrupt handling. */ |
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32 | /* */ |
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33 | /*---------------------------------------------------------------------*/ |
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34 | /* */ |
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35 | /* Code */ |
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36 | /* References: MBX8xx CPU interrupt initialization */ |
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37 | /* Module: irq_init.c */ |
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38 | /* Project: RTEMS 4.6.0pre1 / MBX8xx BSP */ |
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39 | /* Version 1.1 */ |
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40 | /* Date: 04/06/2001 */ |
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41 | /* */ |
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42 | /* Author(s) / Copyright(s): */ |
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43 | /* */ |
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44 | /* CopyRight (C) 2001 valette@crf.canon.fr */ |
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45 | /* */ |
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46 | /* The license and distribution terms for this file may be */ |
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47 | /* found in found in the file LICENSE in this distribution or at */ |
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48 | /* http://www.OARcorp.com/rtems/license.html. */ |
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49 | /* */ |
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50 | /*---------------------------------------------------------------------*/ |
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51 | /* */ |
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52 | /* Partially based on the code references which are named above. */ |
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53 | /* Adaptions, modifications, enhancements and any recent parts of */ |
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54 | /* the code are under the right of */ |
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55 | /* */ |
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56 | /* IPR Engineering, Dachauer StraÃe 38, D-80335 MÃŒnchen */ |
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57 | /* Copyright(C) 2003 */ |
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58 | /* */ |
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59 | /*---------------------------------------------------------------------*/ |
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60 | /* */ |
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61 | /* IPR Engineering makes no representation or warranties with */ |
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62 | /* respect to the performance of this computer program, and */ |
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63 | /* specifically disclaims any responsibility for any damages, */ |
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64 | /* special or consequential, connected with the use of this program. */ |
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65 | /* */ |
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66 | /*---------------------------------------------------------------------*/ |
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67 | /* */ |
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68 | /* Version history: 1.0 */ |
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69 | /* */ |
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70 | /***********************************************************************/ |
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71 | |
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72 | #include <bsp.h> |
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73 | #include <rtems.h> |
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74 | #include "../irq/irq.h" |
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75 | #include <rtems/bspIo.h> |
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76 | #include <libcpu/raw_exception.h> |
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77 | #include "../include/mpc5200.h" |
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78 | |
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79 | extern unsigned int external_exception_vector_prolog_code_size; |
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80 | extern void external_exception_vector_prolog_code(); |
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81 | extern unsigned int decrementer_exception_vector_prolog_code_size; |
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82 | extern void decrementer_exception_vector_prolog_code(); |
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83 | extern unsigned int system_management_exception_vector_prolog_code_size; |
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84 | extern void system_management_exception_vector_prolog_code(); |
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85 | |
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86 | extern void BSP_panic(char *s); |
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87 | extern void _BSP_Fatal_error(unsigned int v); |
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88 | /* |
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89 | volatile unsigned int ppc_cached_irq_mask; |
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90 | */ |
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91 | |
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92 | /* |
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93 | * default on/off function |
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94 | */ |
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95 | static void nop_func(){} |
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96 | /* |
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97 | * default isOn function |
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98 | */ |
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99 | static int not_connected() {return 0;} |
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100 | /* |
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101 | * default possible isOn function |
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102 | */ |
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103 | static int connected() {return 1;} |
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104 | |
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105 | static rtems_irq_connect_data rtemsIrq[BSP_IRQ_NUMBER]; |
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106 | static rtems_irq_global_settings initial_config; |
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107 | |
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108 | static rtems_irq_connect_data defaultIrq = |
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109 | { |
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110 | /* vectorIdex, hdl , param, on , off , isOn */ |
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111 | 0, nop_func, NULL , nop_func, nop_func, not_connected }; |
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112 | |
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113 | static rtems_irq_prio irqPrioTable[BSP_SIU_IRQ_NUMBER] = |
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114 | { |
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115 | /* per. int. priorities (0-7) / 4bit coding / msb is HI/LO selection */ |
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116 | /* msb = 0 -> non-critical per. int. is routed to main int. (LO_int) */ |
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117 | /* msb = 1 -> critical per. int. is routed to critical int. (HI_int) */ |
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118 | 0xF, 0, 0, 0, /* smart_comm (do not change!), psc1, psc2, psc3 */ |
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119 | 0, 0, 0, 0, /* irda, eth, usb, ata */ |
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120 | 0, 0, 0, 0, /* pci_ctrl, pci_sc_rx, pci_sc_tx, res */ |
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121 | 0, 0, 0, 0, /* res, spi_modf, spi_spif, i2c1 */ |
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122 | 0, 0, 0, 0, /* i2c, can1, can2, ir_rx */ |
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123 | 0, 0, /* ir_rx, xlb_arb */ |
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124 | /* main interrupt priorities (0-7) / 4bit coding / msb is INT/SMI selection */ |
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125 | /* msb = 0 -> main int. is routed to processor INT (low vector base 0x500 ) */ |
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126 | /* msb = 1 -> main int. is routed to processor SMI (low vector base 0x1400 ) */ |
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127 | 0, 0, /* slice_tim2, irq1 */ |
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128 | 0, 0, 0, 0, /* irq2, irq3, lo_int, rtc_pint */ |
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129 | 0, 0, 0, 0, /* rtc_sint, gpio_std, gpio_wkup, tmr0 */ |
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130 | 0, 0, 0, 0, /* tmr1, tmr2, tmr3, tmr4 */ |
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131 | 0, 0, 0, /* tmr5, tmr6, tmr7 */ |
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132 | /* critical interrupt priorities (0-3) / 2bit coding / no special purpose of msb */ |
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133 | 0, /* irq0 */ |
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134 | 0, 0, 0 /* slice_tim1, hi_int, ccs_wkup */ |
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135 | }; |
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136 | |
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137 | uint32_t irqMaskTable[BSP_PER_IRQ_NUMBER + BSP_MAIN_IRQ_NUMBER]; |
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138 | |
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139 | |
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140 | /* |
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141 | * setup irqMaskTable to support a priorized/nested interrupt environment |
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142 | */ |
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143 | void setup_irqMaskTable(void) |
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144 | { |
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145 | rtems_irq_prio prio = 0; |
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146 | uint32_t i = 0, j = 0, mask = 0; |
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147 | |
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148 | /* set up the priority dependent masks for peripheral interrupts */ |
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149 | for(i = BSP_PER_IRQ_LOWEST_OFFSET; i <= BSP_PER_IRQ_MAX_OFFSET; i++) |
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150 | { |
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151 | |
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152 | prio = irqPrioTable[i]; |
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153 | mask = 0; |
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154 | |
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155 | for(j = BSP_PER_IRQ_LOWEST_OFFSET; j <= BSP_PER_IRQ_MAX_OFFSET; j++) |
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156 | { |
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157 | |
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158 | if(prio > irqPrioTable[j]) |
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159 | mask |= (1 << (31 - j + BSP_PER_IRQ_LOWEST_OFFSET)); |
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160 | |
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161 | if((prio == irqPrioTable[j]) && (j >= i)) |
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162 | mask |= (1 << (31 - j + BSP_PER_IRQ_LOWEST_OFFSET)); |
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163 | |
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164 | } |
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165 | |
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166 | irqMaskTable[i] = mask; |
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167 | |
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168 | } |
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169 | |
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170 | |
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171 | /* set up the priority dependent masks for main interrupts */ |
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172 | for(i = BSP_MAIN_IRQ_LOWEST_OFFSET; i <= BSP_MAIN_IRQ_MAX_OFFSET; i++) |
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173 | { |
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174 | |
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175 | prio = irqPrioTable[i]; |
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176 | mask = 0; |
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177 | |
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178 | for(j = BSP_MAIN_IRQ_LOWEST_OFFSET; j <= BSP_MAIN_IRQ_MAX_OFFSET; j++) |
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179 | { |
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180 | |
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181 | if(prio > irqPrioTable[j]) |
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182 | mask |= (1 << (16 - j + BSP_MAIN_IRQ_LOWEST_OFFSET)); |
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183 | |
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184 | if((prio == irqPrioTable[j]) && (j >= i)) |
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185 | mask |= (1 << (16 - j + BSP_MAIN_IRQ_LOWEST_OFFSET)); |
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186 | |
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187 | } |
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188 | |
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189 | irqMaskTable[i] = mask; |
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190 | |
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191 | } |
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192 | |
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193 | } |
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194 | |
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195 | |
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196 | /* |
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197 | * Initialize MPC5x00 SIU interrupt management |
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198 | */ |
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199 | void BSP_SIU_irq_init(void) |
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200 | { |
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201 | |
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202 | /* disable all peripheral interrupts */ |
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203 | mpc5200.per_mask = 0xFFFFFC00; |
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204 | |
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205 | /* peripheral interrupt priorities according to reset value */ |
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206 | mpc5200.per_pri_1 = 0xF0000000; |
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207 | mpc5200.per_pri_2 = 0x00000000; |
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208 | mpc5200.per_pri_3 = 0x00000000; |
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209 | |
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210 | /* disable external interrupts IRQ0-4 / critical interrupts are routed to core_int */ |
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211 | mpc5200.ext_en_type = 0x0F000001; |
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212 | |
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213 | /* disable main interrupts / crit. int. priorities according to reset values */ |
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214 | mpc5200.crit_pri_main_mask = 0x0001FFFF; |
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215 | |
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216 | /* main priorities according to reset value */ |
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217 | mpc5200.main_pri_1 = 0; |
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218 | mpc5200.main_pri_2 = 0; |
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219 | |
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220 | /* reset all status indicators */ |
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221 | mpc5200.csa = 0x0001FFFF; |
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222 | mpc5200.msa = 0x0001FFFF; |
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223 | mpc5200.psa = 0x003FFFFF; |
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224 | mpc5200.psa_be = 0x03000000; |
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225 | |
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226 | setup_irqMaskTable(); |
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227 | |
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228 | } |
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229 | |
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230 | void BSP_rtems_irq_mng_init(unsigned cpuId) |
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231 | { |
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232 | rtems_raw_except_connect_data vectorDesc; |
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233 | int i; |
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234 | |
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235 | BSP_SIU_irq_init(); |
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236 | /* |
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237 | * Initialize Rtems management interrupt table |
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238 | */ |
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239 | /* |
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240 | * re-init the rtemsIrq table |
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241 | */ |
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242 | for (i = 0; i < BSP_IRQ_NUMBER; i++) |
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243 | { |
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244 | rtemsIrq[i] = defaultIrq; |
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245 | rtemsIrq[i].name = i; |
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246 | } |
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247 | /* |
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248 | * Init initial Interrupt management config |
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249 | */ |
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250 | initial_config.irqNb = BSP_IRQ_NUMBER; |
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251 | initial_config.defaultEntry = defaultIrq; |
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252 | initial_config.irqHdlTbl = rtemsIrq; |
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253 | initial_config.irqBase = BSP_ASM_IRQ_VECTOR_BASE; |
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254 | initial_config.irqPrioTbl = irqPrioTable; |
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255 | |
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256 | if (!BSP_rtems_irq_mngt_set(&initial_config)) |
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257 | { |
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258 | /* |
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259 | * put something here that will show the failure... |
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260 | */ |
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261 | BSP_panic("Unable to initialize RTEMS interrupt Management!!! System locked\n"); |
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262 | } |
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263 | |
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264 | /* |
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265 | * We must connect the raw irq handler for the two |
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266 | * expected interrupt sources : decrementer and external interrupts. |
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267 | */ |
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268 | vectorDesc.exceptIndex = ASM_DEC_VECTOR; |
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269 | vectorDesc.hdl.vector = ASM_DEC_VECTOR; |
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270 | vectorDesc.hdl.raw_hdl = decrementer_exception_vector_prolog_code; |
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271 | vectorDesc.hdl.raw_hdl_size = (unsigned) &decrementer_exception_vector_prolog_code_size; |
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272 | vectorDesc.on = nop_func; |
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273 | vectorDesc.off = nop_func; |
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274 | vectorDesc.isOn = connected; |
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275 | |
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276 | if (!mpc60x_set_exception (&vectorDesc)) |
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277 | { |
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278 | BSP_panic("Unable to initialize RTEMS decrementer raw exception\n"); |
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279 | } |
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280 | |
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281 | vectorDesc.exceptIndex = ASM_EXT_VECTOR; |
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282 | vectorDesc.hdl.vector = ASM_EXT_VECTOR; |
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283 | vectorDesc.hdl.raw_hdl = external_exception_vector_prolog_code; |
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284 | vectorDesc.hdl.raw_hdl_size = (unsigned) &external_exception_vector_prolog_code_size; |
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285 | |
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286 | if (!mpc60x_set_exception (&vectorDesc)) |
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287 | { |
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288 | BSP_panic("Unable to initialize RTEMS external raw exception\n"); |
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289 | } |
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290 | |
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291 | vectorDesc.exceptIndex = ASM_SYSMGMT_VECTOR; |
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292 | vectorDesc.hdl.vector = ASM_SYSMGMT_VECTOR; |
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293 | vectorDesc.hdl.raw_hdl = system_management_exception_vector_prolog_code; |
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294 | vectorDesc.hdl.raw_hdl_size = (unsigned) &system_management_exception_vector_prolog_code_size; |
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295 | |
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296 | if (!mpc60x_set_exception (&vectorDesc)) |
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297 | { |
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298 | BSP_panic("Unable to initialize RTEMS system management raw exception\n"); |
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299 | } |
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300 | |
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301 | } |
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302 | |
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