1 | /*===============================================================*\ |
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2 | | Project: RTEMS generic MPC5200 BSP | |
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3 | +-----------------------------------------------------------------+ |
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4 | | Partially based on the code references which are named below. | |
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5 | | Adaptions, modifications, enhancements and any recent parts of | |
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6 | | the code are: | |
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7 | | Copyright (c) 2005 | |
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8 | | Embedded Brains GmbH | |
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9 | | Obere Lagerstr. 30 | |
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10 | | D-82178 Puchheim | |
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11 | | Germany | |
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12 | | rtems@embedded-brains.de | |
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13 | +-----------------------------------------------------------------+ |
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14 | | The license and distribution terms for this file may be | |
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15 | | found in the file LICENSE in this distribution or at | |
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16 | | | |
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17 | | http://www.rtems.com/license/LICENSE. | |
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18 | | | |
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19 | +-----------------------------------------------------------------+ |
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20 | | this file contains declarations for the irq controller handler | |
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21 | \*===============================================================*/ |
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22 | /***********************************************************************/ |
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23 | /* */ |
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24 | /* Module: irq.h */ |
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25 | /* Date: 07/17/2003 */ |
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26 | /* Purpose: RTEMS MPC5x00 CPU interrupt header file */ |
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27 | /* */ |
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28 | /*---------------------------------------------------------------------*/ |
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29 | /* */ |
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30 | /* Description: This include file describe the data structure and */ |
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31 | /* the functions implemented by rtems to write */ |
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32 | /* interrupt handlers. */ |
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33 | /* */ |
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34 | /*---------------------------------------------------------------------*/ |
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35 | /* */ |
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36 | /* Code */ |
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37 | /* References: MPC8260ads CPU interrupt header file */ |
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38 | /* Module: irq.h */ |
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39 | /* Project: RTEMS 4.6.0pre1 / MCF8260ads BSP */ |
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40 | /* Version 1.1 */ |
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41 | /* Date: 10/10/2002 */ |
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42 | /* */ |
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43 | /* Author(s) / Copyright(s): */ |
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44 | /* */ |
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45 | /* Copyright (C) 1999 valette@crf.canon.fr */ |
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46 | /* */ |
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47 | /* This code is heavilly inspired by the public specification of */ |
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48 | /* STREAM V2 that can be found at: */ |
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49 | /* */ |
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50 | /* <http://www.chorus.com/Documentation/index.html> by following */ |
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51 | /* the STREAM API Specification Document link. */ |
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52 | /* */ |
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53 | /* Modified for mpc8260 by Andy Dachs <a.dachs@sstl.co.uk> */ |
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54 | /* Surrey Satellite Technology Limited */ |
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55 | /* The interrupt handling on the mpc8260 seems quite different from */ |
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56 | /* the 860 (I don't know the 860 well). Although some interrupts */ |
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57 | /* are routed via the CPM irq and some are direct to the SIU they */ |
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58 | /* all appear logically the same.Therefore I removed the distinction */ |
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59 | /* between SIU and CPM interrupts. */ |
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60 | /* */ |
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61 | /* The license and distribution terms for this file may be */ |
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62 | /* found in found in the file LICENSE in this distribution or at */ |
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63 | /* http://www.OARcorp.com/rtems/license.html. */ |
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64 | /* */ |
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65 | /*---------------------------------------------------------------------*/ |
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66 | /* */ |
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67 | /* Partially based on the code references which are named above. */ |
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68 | /* Adaptions, modifications, enhancements and any recent parts of */ |
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69 | /* the code are under the right of */ |
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70 | /* */ |
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71 | /* IPR Engineering, Dachauer Straße 38, D-80335 München */ |
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72 | /* Copyright(C) 2003 */ |
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73 | /* */ |
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74 | /*---------------------------------------------------------------------*/ |
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75 | /* */ |
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76 | /* IPR Engineering makes no representation or warranties with */ |
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77 | /* respect to the performance of this computer program, and */ |
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78 | /* specifically disclaims any responsibility for any damages, */ |
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79 | /* special or consequential, connected with the use of this program. */ |
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80 | /* */ |
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81 | /*---------------------------------------------------------------------*/ |
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82 | /* */ |
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83 | /* Version history: 1.0 */ |
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84 | /* */ |
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85 | /***********************************************************************/ |
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86 | |
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87 | #ifndef LIBBSP_POWERPC_MPC5200_IRQ_IRQ_H |
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88 | #define LIBBSP_POWERPC_MPC5200_IRQ_IRQ_H |
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89 | |
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90 | #define CHK_CE_SHADOW(pmce) ((pmce) & 0x00000001) |
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91 | #define CHK_CSE_STICKY(pmce) (((pmce) >> 10) & 0x00000001) |
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92 | #define CHK_MSE_STICKY(pmce) (((pmce) >> 21) & 0x00000001) |
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93 | #define CHK_PSE_STICKY(pmce) (((pmce) >> 29) & 0x00000001) |
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94 | #define CLR_CSE_STICKY(pmce) ((pmce) |= (1 << 29 )) |
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95 | #define CLR_MSE_STICKY(pmce) ((pmce) |= (1 << 21 )) |
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96 | #define CLR_PSE_STICKY(pmce) ((pmce) |= (1 << 10 )) |
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97 | #define CSE_SOURCE(source) (((source) >> 8) & 0x00000003) |
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98 | #define MSE_SOURCE(source) (((source) >> 16) & 0x0000001F) |
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99 | #define PSE_SOURCE(source) (((source) >> 24) & 0x0000001F) |
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100 | |
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101 | /* |
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102 | * Base index for the module specific irq handlers |
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103 | */ |
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104 | #define BSP_ASM_IRQ_VECTOR_BASE 0 |
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105 | #define BSP_PER_VECTOR_BASE BSP_ASM_IRQ_VECTOR_BASE /* 0 */ |
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106 | /* |
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107 | * Peripheral IRQ handlers related definitions |
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108 | */ |
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109 | #define BSP_PER_IRQ_NUMBER 22 |
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110 | #define BSP_PER_IRQ_LOWEST_OFFSET BSP_PER_VECTOR_BASE /* 0 */ |
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111 | #define BSP_PER_IRQ_MAX_OFFSET BSP_PER_IRQ_LOWEST_OFFSET + BSP_PER_IRQ_NUMBER - 1 /* 21 */ |
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112 | /* |
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113 | * Main IRQ handlers related definitions |
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114 | */ |
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115 | #define BSP_MAIN_IRQ_NUMBER 17 |
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116 | #define BSP_MAIN_IRQ_LOWEST_OFFSET BSP_PER_IRQ_MAX_OFFSET + 1 /* 22 */ |
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117 | #define BSP_MAIN_IRQ_MAX_OFFSET BSP_MAIN_IRQ_LOWEST_OFFSET + BSP_MAIN_IRQ_NUMBER - 1 /* 38 */ |
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118 | /* |
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119 | * Critical IRQ handlers related definitions |
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120 | */ |
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121 | #define BSP_CRIT_IRQ_NUMBER 4 |
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122 | #define BSP_CRIT_IRQ_LOWEST_OFFSET BSP_MAIN_IRQ_MAX_OFFSET + 1 /* 39 */ |
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123 | #define BSP_CRIT_IRQ_MAX_OFFSET BSP_CRIT_IRQ_LOWEST_OFFSET + BSP_CRIT_IRQ_NUMBER - 1 /* 42 */ |
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124 | /* |
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125 | * Summary of SIU interrupts |
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126 | */ |
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127 | #define BSP_SIU_IRQ_NUMBER BSP_CRIT_IRQ_MAX_OFFSET + 1 /* 43 */ |
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128 | #define BSP_SIU_IRQ_LOWEST_OFFSET BSP_PER_IRQ_LOWEST_OFFSET /* 0 */ |
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129 | #define BSP_SIU_IRQ_MAX_OFFSET BSP_CRIT_IRQ_MAX_OFFSET /* 42 */ |
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130 | /* |
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131 | * Processor IRQ handlers related definitions |
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132 | */ |
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133 | #define BSP_PROCESSOR_IRQ_NUMBER 3 |
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134 | #define BSP_PROCESSOR_IRQ_LOWEST_OFFSET BSP_CRIT_IRQ_MAX_OFFSET + 1 /* 44 */ |
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135 | #define BSP_PROCESSOR_IRQ_MAX_OFFSET BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1 /* 46 */ |
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136 | /* |
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137 | * Summary |
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138 | */ |
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139 | #define BSP_IRQ_NUMBER BSP_PROCESSOR_IRQ_MAX_OFFSET + 1 /* 47 */ |
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140 | #define BSP_LOWEST_OFFSET BSP_PER_IRQ_LOWEST_OFFSET /* 0 */ |
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141 | #define BSP_MAX_OFFSET BSP_PROCESSOR_IRQ_MAX_OFFSET /* 46 */ |
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142 | |
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143 | #ifndef ASM |
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144 | |
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145 | /* |
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146 | extern volatile unsigned int ppc_cached_irq_mask; |
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147 | */ |
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148 | |
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149 | /* |
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150 | * index table for the module specific handlers, a few entries are only placeholders |
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151 | */ |
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152 | typedef enum |
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153 | { |
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154 | BSP_SIU_IRQ_SMARTCOMM = BSP_PER_IRQ_LOWEST_OFFSET + 0, |
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155 | BSP_SIU_IRQ_PSC1 = BSP_PER_IRQ_LOWEST_OFFSET + 1, |
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156 | BSP_SIU_IRQ_PSC2 = BSP_PER_IRQ_LOWEST_OFFSET + 2, |
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157 | BSP_SIU_IRQ_PSC3 = BSP_PER_IRQ_LOWEST_OFFSET + 3, |
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158 | BSP_SIU_IRQ_PSC6 = BSP_PER_IRQ_LOWEST_OFFSET + 4, |
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159 | BSP_SIU_IRQ_ETH = BSP_PER_IRQ_LOWEST_OFFSET + 5, |
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160 | BSP_SIU_IRQ_USB = BSP_PER_IRQ_LOWEST_OFFSET + 6, |
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161 | BSP_SIU_IRQ_ATA = BSP_PER_IRQ_LOWEST_OFFSET + 7, |
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162 | BSP_SIU_IRQ_PCI_CRT = BSP_PER_IRQ_LOWEST_OFFSET + 8, |
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163 | BSP_SIU_IRQ_PCI_SC_RX = BSP_PER_IRQ_LOWEST_OFFSET + 9, |
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164 | BSP_SIU_IRQ_PCI_SC_TX = BSP_PER_IRQ_LOWEST_OFFSET + 10, |
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165 | BSP_SIU_IRQ_PSC4 = BSP_PER_IRQ_LOWEST_OFFSET + 11, |
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166 | BSP_SIU_IRQ_PSC5 = BSP_PER_IRQ_LOWEST_OFFSET + 12, |
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167 | BSP_SIU_IRQ_SPI_MODF = BSP_PER_IRQ_LOWEST_OFFSET + 13, |
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168 | BSP_SIU_IRQ_SPI_SPIF = BSP_PER_IRQ_LOWEST_OFFSET + 14, |
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169 | BSP_SIU_IRQ_I2C1 = BSP_PER_IRQ_LOWEST_OFFSET + 15, |
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170 | BSP_SIU_IRQ_I2C2 = BSP_PER_IRQ_LOWEST_OFFSET + 16, |
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171 | BSP_SIU_IRQ_MSCAN1 = BSP_PER_IRQ_LOWEST_OFFSET + 17, |
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172 | BSP_SIU_IRQ_MSCAN2 = BSP_PER_IRQ_LOWEST_OFFSET + 18, |
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173 | BSP_SIU_IRQ_IR_RX = BSP_PER_IRQ_LOWEST_OFFSET + 19, |
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174 | BSP_SIU_IRQ_IR_TX = BSP_PER_IRQ_LOWEST_OFFSET + 20, |
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175 | BSP_SIU_IRQ_XLB_ARB = BSP_PER_IRQ_LOWEST_OFFSET + 21, |
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176 | |
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177 | BSP_SIU_IRQ_SL_TIMER1 = BSP_MAIN_IRQ_LOWEST_OFFSET + 0, /* handler entry only used in case of SMI */ |
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178 | BSP_SIU_IRQ_IRQ1 = BSP_MAIN_IRQ_LOWEST_OFFSET + 1, |
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179 | BSP_SIU_IRQ_IRQ2 = BSP_MAIN_IRQ_LOWEST_OFFSET + 2, |
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180 | BSP_SIU_IRQ_IRQ3 = BSP_MAIN_IRQ_LOWEST_OFFSET + 3, |
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181 | BSP_SIU_IRQ_LO_INT = BSP_MAIN_IRQ_LOWEST_OFFSET + 4, /* handler entry never used (only placeholder) */ |
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182 | BSP_SIU_IRQ_RTC_PER = BSP_MAIN_IRQ_LOWEST_OFFSET + 5, |
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183 | BSP_SIU_IRQ_RTC_STW = BSP_MAIN_IRQ_LOWEST_OFFSET + 6, |
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184 | BSP_SIU_IRQ_GPIO_STD = BSP_MAIN_IRQ_LOWEST_OFFSET + 7, |
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185 | BSP_SIU_IRQ_GPIO_WKUP = BSP_MAIN_IRQ_LOWEST_OFFSET + 8, |
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186 | BSP_SIU_IRQ_TMR0 = BSP_MAIN_IRQ_LOWEST_OFFSET + 9, |
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187 | BSP_SIU_IRQ_TMR1 = BSP_MAIN_IRQ_LOWEST_OFFSET + 10, |
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188 | BSP_SIU_IRQ_TMR2 = BSP_MAIN_IRQ_LOWEST_OFFSET + 1, |
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189 | BSP_SIU_IRQ_TMR3 = BSP_MAIN_IRQ_LOWEST_OFFSET + 12, |
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190 | BSP_SIU_IRQ_TMR4 = BSP_MAIN_IRQ_LOWEST_OFFSET + 13, |
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191 | BSP_SIU_IRQ_TMR5 = BSP_MAIN_IRQ_LOWEST_OFFSET + 14, |
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192 | BSP_SIU_IRQ_TMR6 = BSP_MAIN_IRQ_LOWEST_OFFSET + 15, |
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193 | BSP_SIU_IRQ_TMR7 = BSP_MAIN_IRQ_LOWEST_OFFSET + 16, |
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194 | |
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195 | BSP_SIU_IRQ_IRQ0 = BSP_CRIT_IRQ_LOWEST_OFFSET + 0, |
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196 | BSP_SIU_IRQ_SL_TIMER0 = BSP_CRIT_IRQ_LOWEST_OFFSET + 1, |
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197 | BSP_SIU_IRQ_HI_INT = BSP_CRIT_IRQ_LOWEST_OFFSET + 2, /* handler entry never used (only placeholder) */ |
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198 | BSP_SIU_IRQ_CSS_WKUP = BSP_CRIT_IRQ_LOWEST_OFFSET + 3, |
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199 | |
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200 | BSP_DECREMENTER = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 0, |
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201 | BSP_SYSMGMT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 1, |
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202 | BSP_EXT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 2 |
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203 | |
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204 | }rtems_irq_symbolic_name; |
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205 | |
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206 | #define BSP_CRIT_IRQ_PRIO_LEVELS 4 |
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207 | /*#define BSP_PERIODIC_TIMER BSP_DECREMENTER*/ |
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208 | #define BSP_PERIODIC_TIMER BSP_SIU_IRQ_TMR6 |
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209 | /*#define CPM_INTERRUPT*/ |
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210 | |
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211 | |
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212 | /* |
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213 | * Type definition for RTEMS managed interrupts |
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214 | */ |
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215 | typedef unsigned char rtems_irq_prio; |
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216 | struct __rtems_irq_connect_data__; /* forward declaratiuon */ |
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217 | |
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218 | typedef unsigned int rtems_irq_number; |
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219 | typedef void *rtems_irq_hdl_param; |
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220 | typedef void (*rtems_irq_hdl) (rtems_irq_hdl_param); |
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221 | typedef void (*rtems_irq_enable) (const struct __rtems_irq_connect_data__*); |
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222 | typedef void (*rtems_irq_disable) (const struct __rtems_irq_connect_data__*); |
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223 | typedef int (*rtems_irq_is_enabled) (const struct __rtems_irq_connect_data__*); |
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224 | |
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225 | typedef struct __rtems_irq_connect_data__ { |
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226 | /* |
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227 | * IRQ line |
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228 | */ |
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229 | rtems_irq_number name; |
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230 | /* |
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231 | * handler. See comment on handler properties below in function prototype. |
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232 | */ |
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233 | rtems_irq_hdl hdl; |
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234 | /* |
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235 | * Handler handle to store private data |
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236 | */ |
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237 | rtems_irq_hdl_param handle; |
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238 | /* |
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239 | * function for enabling interrupts at device level (ONLY!). |
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240 | * The BSP code will automatically enable it at i8259s level. |
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241 | * RATIONALE : anyway such code has to exist in current driver code. |
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242 | * It is usually called immediately AFTER connecting the interrupt handler. |
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243 | * RTEMS may well need such a function when restoring normal interrupt |
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244 | * processing after a debug session. |
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245 | * |
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246 | */ |
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247 | rtems_irq_enable on; |
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248 | /* |
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249 | * function for disabling interrupts at device level (ONLY!). |
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250 | * The code will disable it at i8259s level. RATIONALE : anyway |
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251 | * such code has to exist for clean shutdown. It is usually called |
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252 | * BEFORE disconnecting the interrupt. RTEMS may well need such |
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253 | * a function when disabling normal interrupt processing for |
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254 | * a debug session. May well be a NOP function. |
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255 | */ |
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256 | rtems_irq_disable off; |
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257 | /* |
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258 | * function enabling to know what interrupt may currently occur |
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259 | * if someone manipulates the i8259s interrupt mask without care... |
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260 | */ |
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261 | rtems_irq_is_enabled isOn; |
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262 | |
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263 | #ifdef BSP_SHARED_HANDLER_SUPPORT |
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264 | /* |
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265 | * Set to -1 for vectors forced to have only 1 handler |
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266 | */ |
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267 | void *next_handler; |
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268 | #endif |
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269 | |
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270 | } rtems_irq_connect_data; |
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271 | |
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272 | typedef struct { |
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273 | /* |
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274 | * size of all the table fields (*Tbl) described below. |
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275 | */ |
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276 | unsigned int irqNb; |
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277 | /* |
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278 | * Default handler used when disconnecting interrupts. |
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279 | */ |
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280 | rtems_irq_connect_data defaultEntry; |
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281 | /* |
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282 | * Table containing initials/current value. |
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283 | */ |
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284 | rtems_irq_connect_data* irqHdlTbl; |
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285 | /* |
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286 | * actual value of BSP_PER_IRQ_VECTOR_BASE... |
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287 | */ |
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288 | rtems_irq_symbolic_name irqBase; |
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289 | /* |
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290 | * software priorities associated with interrupts. |
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291 | * if irqPrio [i] > intrPrio [j] it means that |
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292 | * interrupt handler hdl connected for interrupt name i |
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293 | * will not be interrupted by the handler connected for interrupt j |
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294 | * The interrupt source will be physically masked at i8259 level. |
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295 | */ |
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296 | rtems_irq_prio* irqPrioTbl; |
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297 | }rtems_irq_global_settings; |
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298 | |
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299 | |
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300 | |
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301 | /*-------------------------------------------------------------------------+ |
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302 | | Function Prototypes. |
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303 | +--------------------------------------------------------------------------*/ |
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304 | /* |
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305 | * ------------------------ PPC CPM Mngt Routines ------- |
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306 | */ |
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307 | |
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308 | /* |
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309 | * function to disable a particular irq. After calling |
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310 | * this function, even if the device asserts the interrupt line it will |
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311 | * not be propagated further to the processor |
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312 | */ |
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313 | int BSP_irq_disable_at_siu (const rtems_irq_symbolic_name irqLine); |
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314 | /* |
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315 | * function to enable a particular irq. After calling |
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316 | * this function, if the device asserts the interrupt line it will |
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317 | * be propagated further to the processor |
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318 | */ |
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319 | int BSP_irq_enable_at_siu (const rtems_irq_symbolic_name irqLine); |
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320 | /* |
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321 | * function to acknoledge a particular irq. After calling |
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322 | * this function, if a device asserts an enabled interrupt line it will |
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323 | * be propagated further to the processor. Mainly usefull for people |
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324 | * writting raw handlers as this is automagically done for rtems managed |
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325 | * handlers. |
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326 | */ |
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327 | int BSP_irq_ack_at_siu (const rtems_irq_symbolic_name irqLine); |
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328 | /* |
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329 | * function to check if a particular irq is enabled. After calling |
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330 | */ |
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331 | int BSP_irq_enabled_at_siu (const rtems_irq_symbolic_name irqLine); |
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332 | |
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333 | |
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334 | |
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335 | /* |
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336 | * ------------------------ RTEMS Single Irq Handler Mngt Routines ---------------- |
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337 | */ |
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338 | /* |
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339 | * function to connect a particular irq handler. This hanlder will NOT be called |
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340 | * directly as the result of the corresponding interrupt. Instead, a RTEMS |
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341 | * irq prologue will be called that will : |
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342 | * |
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343 | * 1) save the C scratch registers, |
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344 | * 2) switch to a interrupt stack if the interrupt is not nested, |
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345 | * 4) modify them to disable the current interrupt at SIU level (and may |
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346 | * be others depending on software priorities) |
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347 | * 5) aknowledge the SIU', |
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348 | * 6) demask the processor, |
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349 | * 7) call the application handler |
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350 | * |
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351 | * As a result the hdl function provided |
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352 | * |
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353 | * a) can perfectly be written is C, |
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354 | * b) may also well directly call the part of the RTEMS API that can be used |
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355 | * from interrupt level, |
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356 | * c) It only responsible for handling the jobs that need to be done at |
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357 | * the device level including (aknowledging/re-enabling the interrupt at device, |
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358 | * level, getting the data,...) |
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359 | * |
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360 | * When returning from the function, the following will be performed by |
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361 | * the RTEMS irq epilogue : |
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362 | * |
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363 | * 1) masks the interrupts again, |
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364 | * 2) restore the original SIU interrupt masks |
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365 | * 3) switch back on the orinal stack if needed, |
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366 | * 4) perform rescheduling when necessary, |
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367 | * 5) restore the C scratch registers... |
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368 | * 6) restore initial execution flow |
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369 | * |
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370 | */ |
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371 | int BSP_install_rtems_irq_handler (const rtems_irq_connect_data*); |
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372 | /* |
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373 | * function to get the current RTEMS irq handler for ptr->name. It enables to |
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374 | * define hanlder chain... |
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375 | */ |
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376 | int BSP_get_current_rtems_irq_handler (rtems_irq_connect_data* ptr); |
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377 | /* |
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378 | * function to get disconnect the RTEMS irq handler for ptr->name. |
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379 | * This function checks that the value given is the current one for safety reason. |
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380 | * The user can use the previous function to get it. |
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381 | */ |
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382 | int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data*); |
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383 | |
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384 | |
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385 | void BSP_rtems_irq_mng_init(unsigned cpuId); |
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386 | |
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387 | int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config); |
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388 | |
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389 | #endif |
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390 | |
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391 | #endif |
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